CN105551994A - Method for verifying tunnelling oxide layer reliability of flash memory - Google Patents
Method for verifying tunnelling oxide layer reliability of flash memory Download PDFInfo
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- CN105551994A CN105551994A CN201610088127.2A CN201610088127A CN105551994A CN 105551994 A CN105551994 A CN 105551994A CN 201610088127 A CN201610088127 A CN 201610088127A CN 105551994 A CN105551994 A CN 105551994A
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- tunnel oxide
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
Abstract
The invention discloses a method for verifying tunnelling oxide layer reliability of a flash memory. The method comprises following steps: forming an N trap in a silicon wafer; depositing a tunnelling oxide layer, annealing; depositing a floating gate layer and a silicon nitride layer; forming a shallow isolation groove through photoetching and dry etching, filling an oxide layer; removing part of the oxide layer through wet etching so as to form a shallow isolation structure; removing the silicon nitride layer by hot phosphoric acid, depositing a gate layer; forming a field effect transistor instrument and forming a side wall and an electrode through photoetching and dry etching; and carrying out a tunnelling oxide layer reliability test to the finished test instrument. The quality of the tunnelling oxide layer can be verified rapidly in a short time, thus obtaining a test feedback result; improved can be carried out on the basis of the test feedback result; the technology feedback time and the research and development cycle are greatly shortened; and the technology development speed is effectively accelerated.
Description
Technical field
The present invention relates to silicon semiconductor device manufacturing process technology field, more specifically, relate to a kind of method verifying flash memory tunnel oxide reliability.
Background technology
Flash memory (Flashmemory) has been widely used in (such as smart card, storage card etc.) on various storage medium now, is a kind of very important semiconductor device.Tunnel oxide (tunneloxide) is most important processing step during flash memory makes, and its quality directly has influence on the performance of flash memory.A lot of processing step (such as STI fills, annealing etc.) all can affect the performance of tunnel oxide.
In semiconductor device, reliability is very important parameter.General device (logic, high tension apparatus etc.) all will reach some device reliability standards such as hot electron HCI (Hotcarrierinjection), grid oxygen quality GOI (GateoxideIntegrity) etc.Flash memory is as memory device, and reliability standard is stricter than general logical device.
In flash memory, have much special technology assessment standard, wherein first important parameter is data retention (DataRetention).Normally use in order to ensure device, generally need to make data keep reaching 10 years under normal temperature condition.General tunnel oxide and dielectric oxide layer (ONO) all can affect data retention.Second important parameter is durability (Endurance).In order to ensure useful life, generally need the number of times of read-write repeatedly reaching 100K.And the most important processing step affecting durability is exactly the quality of tunnel oxide.If tunnel oxide poor quality, just have electronics and be trapped in tunnel oxide in read-write process, in long-time read-write repeatedly, electric charge is cumulative, threshold voltage window (Vtwindow) can be made in the course of time to close, cause component failure.
In flash technology, a lot of step can affect the quality of tunnel oxide, such as active area etching (AAetch), and shallow-trench isolation fills (STIfilling), tunnel oxide annealing (anneal) etc.
The method of general survey tunnel oxide quality is the method with testing electrical property (QBD).Refer to Fig. 1, Fig. 1 is a kind of tunnel oxide test structure.As shown in Figure 1, the general principle of its test utilizes capacitance structure electrical to test tunnel oxide.Test structure is sandwich structure, and top is grid G ate, and below is substrate S ubstrate, and centre is tunnel oxide.When testing, respectively at grid G ate and substrate S ubstrate making alive, if (be generally 1 μ A/cm when electric leakage reaches some levels
2), just think tunnel oxide breakdown (oxidebreakdown).If to be pressurized to breakdown time more of a specified duration, illustrate that the quality of tunnel oxide is better.
Under normal conditions, in order to improve tunnel oxide quality, need to do a lot of process optimization to improve, but need within about about 50-60 days, just to complete whole process cycle (roll off the production line to from silicon chip and complete testing electrical property), and much will arrive testing electrical property about the experimental result improving tunnel oxide quality and terminated just can obtain, time can be relatively more of a specified duration, and this is by the research and development progress of the whole project of impact.
Summary of the invention
The object of the invention is to the above-mentioned defect overcoming prior art existence, provide a kind of method verifying flash memory tunnel oxide reliability, to shorten the process exploitation time.
For achieving the above object, technical scheme of the present invention is as follows:
Verify a method for flash memory tunnel oxide reliability, comprise the following steps:
Step S01: form N trap by ion implantation in silicon chip, then deposit tunnel oxide on silicon chip and anneal, then deposits floating gate layer and silicon nitride layer;
Step S02: by photoetching and be dry-etched in silicon chip and form shallow-trench isolation groove;
Step S03: the oxide layer of carrying out shallow-trench isolation groove is filled;
Step S04: remove portion of oxide layer by wet etching, stops at floating gate layer, forms shallow groove isolation structure;
Step S05: adopt hot phosphoric acid to remove silicon nitride layer, and depositing layers;
Step S06: form field effect transistor device by photoetching and dry etching;
Step S07: form side wall;
Step S08: form electrode in surfaces of active regions, completes test component preparation;
Step S09: tunnel oxide reliability testing is carried out to test component.
Preferably, in step S01, adopt three passage phosphonium ions to inject and form N traps, in order to regulating threshold voltage of element and carry out device isolation, prevent electric leakage.
Preferably, in step S01, adopt ISSG process deposits tunnel oxide, and adopt N
2o atmosphere is annealed.
Preferably, in step S02, when dry etching forms shallow-trench isolation groove, by etching active area, tunnel oxide, floating gate layer and silicon nitride layer simultaneously, to guarantee pattern and the degree of depth of formed shallow-trench isolation groove.
Preferably, in step S03, the oxide layer adopting HARP technique to carry out shallow-trench isolation groove is filled.
Preferably, in step S04, when removing portion of oxide layer by wet etching, its etch amount should ensure effective isolation and the coupling efficiency of device.
Preferably, described floating gate layer and gate layer material are polysilicon.
Preferably, in step S06, utilize grid layer mask to carry out photoetching and dry etching, form the field effect transistor device as test component.
Preferably, in step S07, by deposited silicon nitride and silica to form side wall.
Preferably, in step S08, form nickel-silicon compound electrode in surfaces of active regions.
As can be seen from technique scheme, the present invention proposes a kind of short processes flow process (ShortloopFlow), by adopting twice lithography step, only need twenties step process flow processs just can form device test structure, as long as making rolls off the production line to from silicon chip complete whole flow process approximately about the 6 days time, so just can the quality of fast verification tunnel oxide at short notice, obtain testing feedback result, and can continue to improve in feedback result, thus substantially reduce process feedback time and R&D cycle, effectively accelerate process exploitation speed.
Accompanying drawing explanation
Fig. 1 is a kind of tunnel oxide test structure;
Fig. 2 is a kind of method flow diagram verifying flash memory tunnel oxide reliability of the present invention;
Fig. 3-Figure 10 is the processing step schematic diagram making test component in a preferred embodiment of the present invention according to the method for Fig. 2.
Embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in further detail.
It should be noted that, in following embodiment, when describing embodiments of the present invention in detail, in order to clearly represent structure of the present invention so that explanation, special to the structure in accompanying drawing not according to general scale, and carried out partial enlargement, distortion and simplify processes, therefore, should avoid being understood in this, as limitation of the invention.
In following the specific embodiment of the present invention, refer to Fig. 2, Fig. 2 is a kind of method flow diagram verifying flash memory tunnel oxide reliability of the present invention; Meanwhile, refer to Fig. 3-Figure 10, Fig. 3-Figure 10 is the processing step schematic diagram making test component in a preferred embodiment of the present invention according to the method for Fig. 2.As shown in Figure 2, a kind of method verifying flash memory tunnel oxide reliability of the present invention, comprises the following steps:
Step S01: form N trap by ion implantation in silicon chip, then deposit tunnel oxide on silicon chip and anneal, then deposits floating gate layer and silicon nitride layer.
Refer to Fig. 3.The present invention can adopt without limitation crystal orientation be the P-type silicon sheet of <110> as substrate to carry out technological process.First, silicon chip 100 forms N trap (NWell) by ion implantation, such as, adopt phosphonium ion to inject and form N trap.As preferred embodiment, the phosphonium ion of three passages can be adopted to inject and to form N trap, in order to regulating threshold voltage of element and carry out device isolation, prevent electric leakage.
Then, can adopt such as ISSG (In-SituSteamGeneration, situ steam method of formation) technique on silicon chip, deposit one deck tunnel oxide 101, its thickness is preferably 7-11nm, such as, can be 7.5nm.Then, N can be adopted
2o atmosphere is annealed for tunnel oxide, to improve the quality of tunnel oxide.
Next, tunnel oxide deposits floating gate layer 102 and silicon nitride layer 103 successively.Wherein, floating gate layer material can adopt polysilicon; Silicon nitride layer is used for as the grinding barrier layer after follow-up filling oxide layer.
Step S02: by photoetching and be dry-etched in silicon chip and form shallow-trench isolation groove.
Refer to Fig. 4.Next, by photoetching and dry etching, in silicon chip, form shallow-trench isolation groove 104.When dry etching forms shallow-trench isolation groove, active area, tunnel oxide, floating gate layer and silicon nitride layer to be etched, to guarantee pattern and the degree of depth of formed shallow-trench isolation groove simultaneously.
Step S03: the oxide layer of carrying out shallow-trench isolation groove is filled.
Refer to Fig. 5.Next, such as HARP (highAspectRatioProcess, high-aspect-ratio chemical vapour deposition (CVD)) technique can be adopted, filling oxide layer 105, such as silica material in shallow-trench isolation groove, and until silicon nitride layer be covered.Then, carry out the planarization of oxide layer 105 by CMP, concordant with silicon nitride layer.
Step S04: remove portion of oxide layer by wet etching, stops at floating gate layer, forms shallow groove isolation structure.
Refer to Fig. 6.Next, the portion of oxide layer 105 of filling in shallow-trench isolation groove is removed by wet etching, in order to improve the coupling efficiency of flush memory device.Etching stopping at floating gate layer, and forms shallow groove isolation structure 106.Its etch amount should ensure effective isolation and the coupling efficiency of device, and wet etching amount is few, and coupling efficiency can be caused not high, and device speed is slow; Wet etching amount can cause again grid and active area conducting too much, therefore needs to find suitable process window.
Step S05: adopt hot phosphoric acid to remove silicon nitride layer, and depositing layers.
Refer to Fig. 7.Next, hot phosphoric acid can be adopted to be removed by silicon nitride layer 103, then, floating gate layer 102 continue depositing layers 107.Gate layer material can adopt polysilicon.
Step S06: form field effect transistor device by photoetching and dry etching.
Refer to Fig. 8.Next, grid layer mask can be utilized to carry out photoetching and dry etching, form the field effect transistor device architecture as test component.
Step S07: form side wall.
Refer to Fig. 9.Then, deposited silicon nitride and silica material, and form sidewall structure 108 by the CMOS side wall technique of standard in grid both sides.
Step S08: form electrode in surfaces of active regions, completes test component preparation.
Refer to Figure 10.Next, make electrode 109 in order to conduction in surfaces of active regions, such as, nickel-silicon compound (NiSi) can be adopted to make electrode.So far, complete the present invention and verify preparation to test component in the method for flash memory tunnel oxide reliability.
Step S09: tunnel oxide reliability testing is carried out to test component.
After the test component that completes, existing method can be adopted, test component be carried out to the test of tunnel oxide reliability, such as, by the method for testing electrical property (QBD), test the reliability of tunnel oxide.
In sum, the present invention proposes a kind of short processes flow process (ShortloopFlow), by adopting twice lithography step, only need twenties step process flow processs just can form device test structure, as long as making rolls off the production line to from silicon chip complete whole flow process approximately about the 6 days time, so just can the quality of fast verification tunnel oxide at short notice, obtain testing feedback result, and can continue to improve in feedback result, thus substantially reduce process feedback time and R&D cycle, effectively accelerate process exploitation speed.
Above-describedly be only the preferred embodiments of the present invention; described embodiment is also not used to limit scope of patent protection of the present invention; therefore the equivalent structure that every utilization specification of the present invention and accompanying drawing content are done changes, and in like manner all should be included in protection scope of the present invention.
Claims (10)
1. verify a method for flash memory tunnel oxide reliability, it is characterized in that, comprise the following steps:
Step S01: form N trap by ion implantation in silicon chip, then deposit tunnel oxide on silicon chip and anneal, then deposits floating gate layer and silicon nitride layer;
Step S02: by photoetching and be dry-etched in silicon chip and form shallow-trench isolation groove;
Step S03: the oxide layer of carrying out shallow-trench isolation groove is filled;
Step S04: remove portion of oxide layer by wet etching, stops at floating gate layer, forms shallow groove isolation structure;
Step S05: adopt hot phosphoric acid to remove silicon nitride layer, and depositing layers;
Step S06: form field effect transistor device by photoetching and dry etching;
Step S07: form side wall;
Step S08: form electrode in surfaces of active regions, completes test component preparation;
Step S09: tunnel oxide reliability testing is carried out to test component.
2. the method for checking flash memory tunnel oxide reliability according to claim 1, is characterized in that, in step S01, adopts three passage phosphonium ions to inject and forms N traps, in order to regulating threshold voltage of element and carry out device isolation, prevents electric leakage.
3. the method for checking flash memory tunnel oxide reliability according to claim 1, is characterized in that, in step S01, adopts ISSG process deposits tunnel oxide, and adopts N
2o atmosphere is annealed.
4. the method for checking flash memory tunnel oxide reliability according to claim 1, it is characterized in that, in step S02, when dry etching forms shallow-trench isolation groove, by etching active area, tunnel oxide, floating gate layer and silicon nitride layer simultaneously, to guarantee pattern and the degree of depth of formed shallow-trench isolation groove.
5. the method for checking flash memory tunnel oxide reliability according to claim 1, is characterized in that, in step S03, the oxide layer adopting HARP technique to carry out shallow-trench isolation groove is filled.
6. the method for checking flash memory tunnel oxide reliability according to claim 1, is characterized in that, in step S04, when removing portion of oxide layer by wet etching, its etch amount should ensure effective isolation and the coupling efficiency of device.
7. the method for checking flash memory tunnel oxide reliability according to claim 1, it is characterized in that, described floating gate layer and gate layer material are polysilicon.
8. the method for checking flash memory tunnel oxide reliability according to claim 1, is characterized in that, in step S06, utilizes grid layer mask to carry out photoetching and dry etching, forms the field effect transistor device as test component.
9. the method for checking flash memory tunnel oxide reliability according to claim 1, is characterized in that, in step S07, by deposited silicon nitride and silica to form side wall.
10. the method for checking flash memory tunnel oxide reliability according to claim 1, is characterized in that, in step S08, forms nickel-silicon compound electrode in surfaces of active regions.
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| CN108614197A (en) * | 2018-04-19 | 2018-10-02 | 武汉新芯集成电路制造有限公司 | A kind of electric leakage independent positioning method for floating boom |
| CN111883485A (en) * | 2020-08-28 | 2020-11-03 | 上海华力微电子有限公司 | Method for manufacturing semiconductor structure |
| CN112447258A (en) * | 2019-09-05 | 2021-03-05 | 上海交通大学 | Method and system for measuring intrinsic breakdown time of flash memory device |
| CN113013323A (en) * | 2019-12-19 | 2021-06-22 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure, forming method thereof and semiconductor device |
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