CN111883419A - Method for manufacturing CMOS device - Google Patents
Method for manufacturing CMOS device Download PDFInfo
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- CN111883419A CN111883419A CN202010841923.5A CN202010841923A CN111883419A CN 111883419 A CN111883419 A CN 111883419A CN 202010841923 A CN202010841923 A CN 202010841923A CN 111883419 A CN111883419 A CN 111883419A
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- silicon nitride
- cmos device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02345—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light
- H01L21/02348—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light treatment by exposure to UV light
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
Abstract
The application discloses a manufacturing method of a CMOS device, and relates to the field of semiconductor manufacturing. The manufacturing method of the CMOS device comprises the steps of providing a substrate with the CMOS device; repeating the deposition and UV light irradiation processes for N times, and forming a silicon nitride film with preset thickness and preset density on the substrate; wherein, the deposition and UV light irradiation process comprises the following steps: depositing silicon nitride, wherein the deposition thickness of the silicon nitride is less than the predetermined thickness; irradiating the deposited silicon nitride on the substrate with UV light; the problem that the reliability of the CMOS device is affected due to the fact that the silicon nitride film deposited on the interlayer dielectric layer directly contacts the CMOS device is solved, and the effect of improving the reliability of the CMOS device is achieved.
Description
Technical Field
The application relates to the field of semiconductor manufacturing, in particular to a manufacturing method of a CMOS device.
Background
With the development of integrated circuits in time, the size of semiconductor devices is continuously reduced, and the reliability problem is more and more called as a main factor limiting the application of MOSFET devices.
The reliability of NMOS devices is generally referred to as HCI (Hot Carrier Injection), and the reliability of PMOS devices is generally referred to as NBTI (Negative Bias Temperature Instability effect). HCI and NBTI are both limited by Si-SiO2Si-H bonds at the interface, under the action of thermal electrons or holesAnd (3) breakage occurs, because H atoms are unstable, two H atoms meet and are combined into hydrogen molecules to diffuse, so that an interface Dit (trap) is generated, and the reliability of an NMOS (N-channel metal oxide semiconductor) device or a PMOS (P-channel metal oxide semiconductor) device is influenced.
Disclosure of Invention
In order to solve the related problems, the present application provides a method of fabricating a CMOS device. The technical scheme is as follows:
in one aspect, an embodiment of the present application provides a method for manufacturing a CMOS device, where the method includes:
providing a substrate with a CMOS device;
repeating the deposition and UV light irradiation processes for N times, and forming a silicon nitride film with preset thickness and preset density on the substrate; wherein, the deposition and UV light irradiation process comprises the following steps:
depositing silicon nitride, wherein the deposition thickness of the silicon nitride is less than the predetermined thickness;
irradiating the deposited silicon nitride on the substrate with UV light.
Optionally, the method further includes:
forming a contact hole on the substrate;
by using D2And carrying out annealing treatment.
Optionally, during the deposition of silicon nitride, the rf energy and/or the reaction temperature are controlled according to the predetermined densification degree.
Optionally, the reaction temperature is less than 400 ℃ during the deposition of the silicon nitride.
Optionally, N is an integer greater than or equal to 2.
Optionally, in the use of D2And D enters the CMOS device to form a Si-D bond in the annealing process.
Optionally, forming a contact hole on the substrate includes:
forming contact holes in the interlayer dielectric layer through photoetching and etching processes, wherein the contact holes are used for leading out a grid electrode, a source electrode and a drain electrode of the CMOS device;
wherein the interlayer dielectric layer is at least composed of the silicon nitride film.
Optionally, the CMOS device is an NMOS device or a PMOS device.
The technical scheme at least comprises the following advantages:
according to the manufacturing method of the CMOS device, after the CMOS device structure is formed on the substrate, the Si-H bonds generated in the silicon nitride deposition process are released in time through the process steps of circularly depositing the silicon nitride and irradiating the silicon nitride by UV light, the effect of reducing the Si-H bonds is achieved, the NBTI or HCI of the CMOS device is improved, the problem that the reliability of the CMOS device is affected due to the fact that a silicon nitride film deposited on an interlayer dielectric layer directly contacts the CMOS device is solved, and the reliability of the CMOS device is improved.
Further, after contact control is formed, D is utilized2Annealing is performed and D penetrates through the silicon nitride film into the CMOS device to form a more stable Si-D, which also contributes to improving HCI or NBTI lifetime.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a flowchart of a method for manufacturing a CMOS device according to an embodiment of the present disclosure;
FIG. 2 is a schematic diagram of a prior art CMOS device;
FIG. 3 is a schematic diagram of a CMOS device provided by an embodiment of the present application;
FIG. 4 is a flow chart of a method of fabricating a CMOS device according to another embodiment of the present application;
FIG. 5 is a chart comparing HCI performance of NMOS devices provided by embodiments of the present application;
FIG. 6 is a graph comparing NBTI performance of PMOS devices provided by embodiments of the present application.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
Referring to fig. 1, a flow chart of a method for manufacturing a CMOS device according to an embodiment of the present application is shown, where the method at least includes the following steps:
And 102, repeating the deposition and UV light irradiation processes for N times, and forming a silicon nitride film with a preset thickness and preset density on the substrate.
Each deposition and UV irradiation process comprises the following 2 steps:
and s1, depositing silicon nitride, wherein the deposition thickness of the silicon nitride is less than the preset thickness.
s2, irradiating the deposited silicon nitride on the substrate with UV light.
The predetermined thickness and the predetermined densification of the silicon nitride film to be deposited, and the number of repetitions N are predetermined.
N is a positive integer.
The thickness of the silicon nitride deposited for N times is equal to the preset thickness, and if N is larger than or equal to 2, the thickness of the silicon nitride deposited for each time is smaller than the preset thickness.
After depositing a layer of silicon nitride on the substrate, moving the substrate to a UV light irradiation area, and irradiating the silicon nitride layer deposited on the substrate by using UV light to release Si-H bonds formed in the silicon nitride deposition process.
The density of the silicon nitride film can be reduced by irradiating the deposited silicon nitride film with UV light, so that the silicon nitride film is looser.
In one example, as shown in fig. 2, the silicon nitride film 21 covered on the CMOS device is deposited by using the prior art, and the density of the silicon nitride film 21 is higher; in another example, as shown in fig. 3, a silicon nitride film 31 covering a CMOS device is deposited by the method provided in the embodiment of the present application, the density of the silicon nitride film 31 is lower, and the silicon nitride film 31 is more loose; comparing fig. 2 and 3, H is difficult to penetrate through the silicon nitride film shown in fig. 2, and H is easier to penetrate through the silicon nitride film 31 shown in fig. 3.
In summary, according to the method for manufacturing the CMOS device provided by the embodiment of the present application, after the CMOS device structure is formed on the substrate, Si-H bonds generated during the deposition of silicon nitride are released in time by the process steps of cyclically depositing silicon nitride and irradiating the silicon nitride with UV light, so that the effect of reducing the Si-H bonds is achieved, which is beneficial to improving NBTI or HCI of the CMOS device, and improving the reliability of the CMOS device.
Referring to fig. 4, a flow chart of a method for manufacturing a CMOS device according to another embodiment of the present application is shown, the method at least includes the following steps:
Optionally, the CMOS device is an NMOS device or a PMOS device.
A plurality of NMOS devices are manufactured on the substrate, or a plurality of PMOS devices are manufactured on the substrate, or a plurality of NMOS devices and PMOS devices are simultaneously manufactured on the substrate.
And 402, repeating the deposition and UV light irradiation processes for N times, and forming a silicon nitride film with a preset thickness and preset density on the substrate.
The deposition and UV light irradiation process comprises the following steps:
and s1, depositing silicon nitride, wherein the deposition thickness of the silicon nitride is less than the preset thickness.
s2, irradiating the deposited silicon nitride on the substrate with UV light.
N is an integer of 2 or more.
In one example, N is 3, the step is implemented by depositing silicon nitride for the 1 st time, the thickness of the silicon nitride deposited on the substrate is less than the predetermined thickness, and irradiating the substrate deposited with a layer of silicon nitride by using UV light; depositing silicon nitride on the substrate for the 2 nd time, wherein the silicon nitride deposited for the 2 nd time covers the silicon nitride deposited for the 1 st time, the thickness of the silicon nitride already deposited on the substrate is less than the preset thickness, and irradiating the silicon nitride deposited for the 2 nd time by using UV light; depositing silicon nitride for the 3 rd time, covering the silicon nitride deposited for the 2 nd time by the deposited silicon nitride for the 3 rd time, wherein the thickness of the silicon nitride deposited for the 3 rd time on the substrate is equal to the preset thickness, and irradiating the silicon nitride deposited for the 3 rd time by using UV light.
During the deposition of silicon nitride, the RF energy and/or the reaction temperature are controlled according to a predetermined densification. Such as: controlling the radio frequency energy in the process of depositing the silicon nitride to enable the density of the deposited silicon nitride to be preset density; or controlling the reaction temperature in the process of depositing the silicon nitride to ensure that the density of the deposited silicon nitride is the preset density; or, the density of the deposited silicon nitride is set to be the preset density by controlling the radio frequency energy and the reaction temperature in the process of depositing the silicon nitride.
During the deposition of silicon nitride, the reaction temperature is less than 400 ℃.
The stress of the silicon nitride film can be adjusted by controlling the reaction temperature, the UV light irradiation power and the number of times of UV light irradiation, so as to reduce the influence of the stress on the short channel device.
In step 403, contact holes are formed in the substrate.
And forming contact holes in the interlayer dielectric layer through a photoetching process and an etching process, wherein the contact holes are used for leading out a grid electrode, a source electrode and a drain electrode of the CMOS device.
The interlayer dielectric layer is at least composed of a silicon nitride film.
If the interlayer dielectric layer is composed of a silicon nitride film and other dielectric layers, after the step 402, other dielectric layers are formed on the silicon nitride film, and then the step 403 is performed.
In the utilization of D2During the annealing process, D (deuterium) enters the CMOS device to form Si-D bonds.
The silicon nitride film is looser due to the reduction of the density of the silicon nitride film irradiated by UV light, and D is utilized2During annealing, D can penetrate through the silicon nitride film to replace Si-H bonds in the CMOS device, so that more stable Si-D bonds are formed.
In one example, the CMOS device is an NMOS device, and HCI performance tests are performed on the NMOS device manufactured by the prior art and the NMOS device manufactured by the method provided in the embodiment of the present application, with the test voltage VD of 7.2V, as shown in fig. 5, a curve 51 corresponds to the NMOS device manufactured by the prior art, a curve 52 corresponds to the NMOS device manufactured by the method provided in the embodiment of the present application, an ordinate is a current loss ratio idsat (drop), an abscissa is time (h), and the curve 51 reaches earlier than the curve 52 when the current loss ratio is 10%, so the HCI performance of the NMOS device manufactured by the method provided in the embodiment of the present application is better.
In another example, the CMOS device is a PMOS device, and NBTI performance test is performed on the NMOS device manufactured by the prior art and the PMOS device manufactured by the method provided in the embodiment of the present application, where the test voltage VG is 1.5VDD, the test temperature is 150 ℃, as shown in fig. 6, a curve 61 corresponds to the PMOS device manufactured by the prior art, a curve 62 corresponds to the PMOS device manufactured by the method provided in the embodiment of the present application, an ordinate is a current loss ratio idsat (drop), an abscissa is time(s), and the current loss ratio of the curve 61 is higher than that of the curve 62, so the NBTI performance of the PMOS device manufactured by the method provided in the embodiment of the present application is better.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.
Claims (8)
1. A method of fabricating a CMOS device, the method comprising:
providing a substrate with a CMOS device;
repeating the deposition and UV light irradiation processes for N times, and forming a silicon nitride film with preset thickness and preset density on the substrate;
wherein, the deposition and UV light irradiation process comprises the following steps:
depositing silicon nitride, wherein the deposition thickness of the silicon nitride is less than the predetermined thickness;
irradiating the deposited silicon nitride on the substrate with UV light.
2. The method of claim 1, further comprising:
forming a contact hole on the substrate;
by using D2And carrying out annealing treatment.
3. The method according to claim 1, wherein during the deposition of silicon nitride, the radiofrequency energy and/or the reaction temperature are controlled according to the predetermined densification.
4. A method according to claim 1 or 3, characterized in that the reaction temperature during the deposition of the silicon nitride is less than 400 ℃.
5. The method of claim 1, wherein N is an integer greater than or equal to 2.
6. Method according to claim 2, characterized in that D is being utilized2And D enters the CMOS device to form a Si-D bond in the annealing process.
7. The method of claim 2, wherein forming a contact hole on the substrate comprises:
forming contact holes in the interlayer dielectric layer through photoetching and etching processes, wherein the contact holes are used for leading out a grid electrode, a source electrode and a drain electrode of the CMOS device;
wherein the interlayer dielectric layer is at least composed of the silicon nitride film.
8. The method of claim 1, wherein the CMOS device is an NMOS device or a PMOS device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202010841923.5A CN111883419A (en) | 2020-08-18 | 2020-08-18 | Method for manufacturing CMOS device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010841923.5A CN111883419A (en) | 2020-08-18 | 2020-08-18 | Method for manufacturing CMOS device |
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| CN111883419A true CN111883419A (en) | 2020-11-03 |
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| CN202010841923.5A Pending CN111883419A (en) | 2020-08-18 | 2020-08-18 | Method for manufacturing CMOS device |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101496145A (en) * | 2006-06-20 | 2009-07-29 | 应用材料股份有限公司 | Method to increase silicon nitride tensile stress using nitrogen plasma in-situ treatment and ex-situ UV cure |
| CN102376754A (en) * | 2010-08-19 | 2012-03-14 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device structure and manufacturing method for the same |
| CN105895634A (en) * | 2015-01-26 | 2016-08-24 | 中芯国际集成电路制造(上海)有限公司 | Cmos device and manufacturing method thereof |
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2020
- 2020-08-18 CN CN202010841923.5A patent/CN111883419A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101496145A (en) * | 2006-06-20 | 2009-07-29 | 应用材料股份有限公司 | Method to increase silicon nitride tensile stress using nitrogen plasma in-situ treatment and ex-situ UV cure |
| CN102376754A (en) * | 2010-08-19 | 2012-03-14 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device structure and manufacturing method for the same |
| CN105895634A (en) * | 2015-01-26 | 2016-08-24 | 中芯国际集成电路制造(上海)有限公司 | Cmos device and manufacturing method thereof |
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