CN111880076A - Signal test point detection method, system and related assembly - Google Patents
Signal test point detection method, system and related assembly Download PDFInfo
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- CN111880076A CN111880076A CN202010674399.7A CN202010674399A CN111880076A CN 111880076 A CN111880076 A CN 111880076A CN 202010674399 A CN202010674399 A CN 202010674399A CN 111880076 A CN111880076 A CN 111880076A
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- 238000012360 testing method Methods 0.000 title claims abstract description 115
- 238000001514 detection method Methods 0.000 title claims abstract description 90
- 238000000034 method Methods 0.000 claims description 18
- 238000004590 computer program Methods 0.000 claims description 11
- 230000008569 process Effects 0.000 claims description 9
- 230000008859 change Effects 0.000 claims description 5
- 230000015654 memory Effects 0.000 claims description 4
- 230000009286 beneficial effect Effects 0.000 abstract description 4
- 238000005259 measurement Methods 0.000 description 8
- 238000013461 design Methods 0.000 description 4
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
- G01R31/281—Specific types of tests or tests for a specific type of fault, e.g. thermal mapping, shorts testing
- G01R31/2813—Checking the presence, location, orientation or value, e.g. resistance, of components or conductors
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
- G01R31/2803—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP] by means of functional tests, e.g. logic-circuit-simulation or algorithms therefor
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Abstract
The application discloses a signal test point detection method, which is applied to a detection tool and comprises the following steps: acquiring a PCB file; receiving a signal line selection instruction and SI information, and determining a signal line and a receiving end chip in a PCB file according to the signal line selection instruction and the SI information; and acquiring test information of the signal line, and adding the test points on the signal line according to the test information and the wiring length specification of the test points from the receiving end chip. The signal testing point detection method and device can reduce the influence on the signal integrity performance, and the signal testing point detection is completed through the detection tool, so that compared with manual detection, a large number of working hours can be reduced, and the detection efficiency and reliability are improved. The application also discloses a signal test point detection system, electronic equipment and a computer readable storage medium, which have the beneficial effects.
Description
Technical Field
The present disclosure relates to the field of signal detection, and in particular, to a method and a system for detecting a signal test point and related components.
Background
In the development of servers, memories and the like, signal testing is an essential loop for ensuring the normal operation of hardware systems. However, in some cases, signal testing cannot be performed, for example, in some signals requiring an oscilloscope to perform point testing, if a trace and a chip on a PCB (printed circuit Board) are designed on the same layer, and a via hole of the layer is not replaced and a test point is not added on the trace, the oscilloscope cannot perform point testing. Based on this, signals needing the oscilloscope to perform point measurement need to be manually gathered, the measurement points are determined on the signal lines, and the PCB design is performed according to the requirements of the SI.
Therefore, how to provide a solution to the above technical problem is a problem that needs to be solved by those skilled in the art.
Disclosure of Invention
The application aims to provide a signal test point detection method, a signal test point detection system, an electronic device and a computer readable storage medium, which can reduce the influence on the signal integrity performance, and the detection of the signal test point is completed by a detection tool, so that compared with manual detection, a large amount of working hours can be reduced, and the detection efficiency and reliability are improved.
In order to solve the above technical problem, the present application provides a method for detecting a signal test point, which is applied to a detection tool, and includes:
acquiring a PCB file;
receiving a signal line selection instruction and SI information, and determining a signal line and a receiving end chip in the PCB file according to the signal line selection instruction and the SI information;
and acquiring test information of the signal wire, and adding the test points on the signal wire according to the test information and the routing length specification of the distance between the test points and the receiving end chip.
Preferably, the test information includes one or more of ID information, connection layer information, layer-change via information, measurement point information, and connected chip pin information.
Preferably, the signal test point detection method further includes:
and generating marking information of the signal wire according to the test information and/or the routing length specification, and storing the marking information into a database.
Preferably, the process of generating the marking information of the signal line according to the test information and/or the routing length specification specifically includes:
when the layer changing through hole information is 0 and no measuring point exists, generating a first mark;
when the layer-changing via hole information is 0 and the routing length from the measuring point to the receiving end chip is greater than the routing length specification, generating the first mark;
and when the layer-changing via hole information is not 0, the routing length of the via hole from the receiving end chip is greater than the routing length specification, and the routing length from the measuring point to the receiving end chip is greater than the routing length specification, generating the first mark.
Preferably, the signal test point detection method further includes:
and displaying the signal lines corresponding to all the first marks.
Preferably, the signal test point detection method further includes:
determining a measuring point adding area on the signal line according to the position of the receiving end chip;
correspondingly, the process of adding the measuring points on the signal line according to the test information and the routing length specification of the measuring points from the receiving end chip specifically comprises the following steps:
and adding the measuring points on the measuring point adding area according to the test information and the routing length specification of the measuring points from the receiving end chip, and updating the test information of the signal line.
Preferably, the signal test point detection method further includes:
information corresponding to the detection result of the signal line is generated.
In order to solve the above technical problem, the present application further provides a signal test point detection system, which is applied to a detection tool, and includes:
the acquisition module is used for acquiring the PCB file;
the determining module is used for receiving a signal line selection instruction and SI information and determining a signal line and a receiving end chip in the PCB file according to the signal line selection instruction and the SI information;
and the adding module is used for acquiring the test information of the signal wire and adding the measuring points on the signal wire according to the test information and the routing length specification of the measuring points from the receiving end chip.
In order to solve the above technical problem, the present application further provides an electronic device, including:
a memory for storing a computer program;
a processor for implementing the steps of the signal test point detection method as described in any one of the above when executing the computer program.
To solve the above technical problem, the present application further provides a computer-readable storage medium, on which a computer program is stored, and the computer program, when executed by a processor, implements the steps of the signal test point detection method as described in any one of the above.
The application provides a signal test point detection method, firstly, a PCB file is obtained through a detection tool, so that information of all signal lines on the PCB is determined, the comprehensiveness of detection on the signal line test points is guaranteed, the omission phenomenon cannot occur, then the detection tool determines a target signal line and a receiving end chip according to a signal line selection instruction and SI information, the positions of the test points are selected on the signal line according to the wiring length specification of the test points from the receiving end chip, the influence on the signal integrity performance is reduced, the detection of the signal test points is completed through the detection tool, compared with manual detection, a large number of working hours can be reduced, and the detection efficiency and reliability are improved. The application also provides a signal test point detection system, an electronic device and a computer readable storage medium, which have the same beneficial effects as the signal test point detection method.
Drawings
In order to more clearly illustrate the embodiments of the present application, the drawings needed for the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings can be obtained by those skilled in the art without inventive effort.
Fig. 1 is a flowchart illustrating steps of a method for detecting a signal test point according to the present application;
FIG. 2 is a schematic view of a display interface of a detection tool provided herein;
fig. 3 is a schematic structural diagram of a signal test point detection system provided in the present application.
Detailed Description
The core of the application is to provide a signal test point detection method, a system, an electronic device and a computer readable storage medium, which can reduce the influence on the signal integrity performance, and the detection of the signal test point is completed by a detection tool, so that compared with manual detection, a large amount of working hours can be reduced, and the detection efficiency and reliability are improved.
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1, fig. 1 is a flowchart illustrating steps of a signal test point detection method applied to a detection tool, where the signal test point detection method includes:
s101: acquiring a PCB file;
s102: receiving a Signal line selection instruction and SI (Signal Integrity) information, and determining a Signal line and a receiving end chip in a PCB file according to the Signal line selection instruction and the SI information;
specifically, when the detection tool of the present application is operating, the PCB file can be acquired, so as to acquire all information of the PCB, such as signal line information, PCB layer information, via hole information, and the like. The user can input a signal line selection instruction, and the signal line selection instruction can include a keyword corresponding to the signal line, so that the detection tool can filter out the signal line selected by the user according to the keyword for subsequent detection. Of course, the signal line selection instruction may also include a complete signal line name, the detection tool selects a signal line according to the complete signal line name, and after the signal line is selected, the detection tool outputs chip information connected to the signal line. After the signal line and the receiving end chip are determined, a user inputs the wiring length specification of the distance between the measuring point and the receiving end chip so that the detection tool can carry out subsequent detection operation after receiving the wiring length specification.
S103: and acquiring test information of the signal line, and adding the test points on the signal line according to the test information and the wiring length specification of the test points from the receiving end chip.
Specifically, after a signal line is determined, test information of the signal line is obtained, where the test information includes, but is not limited to, ID information, layer-change via information (connection layer, coordinates, etc.), test point information (layer, coordinates, etc.), connected chip pins, and the like.
As a preferred embodiment, the signal test point detecting method further includes:
and generating marking information of the signal wire according to the test information and/or the routing length specification, and storing the marking information into a database.
As a preferred embodiment, the process of generating the marking information of the signal line according to the test information and/or the routing length specification specifically includes:
when the layer changing via hole information is 0 and no measuring point exists, generating a first mark;
when the layer-changing via hole information is 0 and the length of the routing from the measuring point to the receiving end chip is greater than the routing length specification, generating a first mark;
and when the layer-changing via hole information is not 0, the routing length of the via hole from the receiving end chip is greater than the routing length specification, and the routing length from the measuring point to the receiving end chip is greater than the routing length specification, generating a first mark.
Specifically, the layer change via information may specifically refer to the number of layer change vias, and if the number of layer change vias is 0, it indicates that the trace and the chip are on the same layer, and checks whether there is a measurement point, and if not, marks "via 0, testpoint 0, Fail", and records in the database, and if there is a measurement point, queries the level of the measurement point, obtains the trace length from the measurement point to the receiving chip, and compares the trace length with the trace length specification, and if greater than the trace length specification, marks "via 0, testpoint 1, Fail", and records in the database, and if less than or equal to the trace length specification, marks "via 0, testpoint 1, Pass", and records in the database. If the number of the via holes is not 0, the routing length of the via holes from the receiving end chip is inquired and compared with the routing length specification, if the routing length is smaller than or equal to the routing length specification, the routing length is marked as 'via 1, Pass', and the routing length is recorded in a database. If the length of the wire is greater than the wiring length standard, the information of the measuring point is continuously checked, if the length of the wire is greater than the wiring length standard, the wiring length from the measuring point to the receiving chip is inquired and compared with the wiring length standard, and if the length of the wire is greater than the wiring length standard, the information is marked as 'via 1, test 1 and fail', and the information is recorded in a database. If the distance is less than or equal to the route length specification, the distance is marked as 'via 1, test 1, Pass', and the distance is recorded in a database. The mark with fail in the mark is the first mark.
After the detection, as a preferred embodiment, the information of all signal lines marked as fail can be displayed on a display interface, so that a user can conveniently view and add test points later, and the information displayed on the display interface can include, but is not limited to, signal line names Net Name, Layer, test points Testpoint, Via information Via, Length of trace, and mark Result, as shown in fig. 2.
Further, a user can select signal lines needing to add a measuring point at present according to all signal lines of fail prompted on the display interface to generate a corresponding selection instruction, after the detection tool receives the selection instruction, the signal lines can be controlled to be highlighted and positioned near a receiving end, namely, a measuring point adding area on the signal lines is determined, measuring points are added on the measuring point adding area, the wiring length from the measuring points to pins of a receiving chip is calculated, if the wiring length is larger than the wiring length specification, prompt information of adding errors is popped up, the user can delete re-adding, if the wiring length is smaller than or equal to the wiring length specification, the correct prompt information is popped up and added, and the next signal line is continuously clicked to carry out the same operation until all the selected signal lines complete measuring point adding.
As a preferred embodiment, in order to ensure the reliability of adding the measurement point, the user may further output a rechecking instruction, so that the detection tool may recheck the selected signal line after receiving the rechecking instruction, if the signal line is not in conformity, the information corresponding to the signal line may be displayed on the display interface, the user may continue to perfect the design, and if the signal line is in conformity with the design requirements, the prompt information corresponding to all the design requirements may be popped up.
As a preferred embodiment, the test point information and the inspection result information of the selected signal line can be stored in a document, so that the subsequent reference is facilitated, and the test point positioning by SI testers is facilitated.
It can be seen that, in this embodiment, a PCB file is obtained through a detection tool, so as to determine information of all signal lines on the PCB, and ensure the comprehensiveness of detection on signal line test points, and no omission occurs, then the detection tool determines a target signal line and a receiving end chip according to a signal line selection instruction and SI information, and selects positions of the test points on the signal line according to a routing length specification of the test points from the receiving end chip, so as to reduce the influence on signal integrity performance, and the detection of the signal test points is completed by the detection tool.
Referring to fig. 3, fig. 3 is a schematic structural diagram of a signal test point detection system applied to a detection tool, the signal test point detection system including:
the acquisition module 1 is used for acquiring a PCB file;
the determining module 2 is used for receiving the signal line selection instruction and the SI information and determining a signal line and a receiving end chip in the PCB file according to the signal line selection instruction and the SI information;
and the adding module 3 is used for acquiring the test information of the signal line and adding the measuring points on the signal line according to the test information and the wiring length specification of the measuring points from the receiving end chip.
It can be seen that, in this embodiment, a PCB file is obtained through a detection tool, so as to determine information of all signal lines on the PCB, and ensure the comprehensiveness of detection on signal line test points, and no omission occurs, then the detection tool determines a target signal line and a receiving end chip according to a signal line selection instruction and SI information, and selects positions of the test points on the signal line according to a routing length specification of the test points from the receiving end chip, so as to reduce the influence on signal integrity performance, and the detection of the signal test points is completed by the detection tool.
In a preferred embodiment, the test information includes one or more of ID information, connection level information, layer change via information, test point information, and connected chip pin information.
As a preferred embodiment, the signal test point detection system further comprises:
and the marking module is used for generating marking information of the signal wire according to the test information and/or the routing length specification and storing the marking information into a database.
As a preferred embodiment, the process of generating the marking information of the signal line according to the test information and/or the routing length specification specifically includes:
when the layer changing via hole information is 0 and no measuring point exists, generating a first mark;
when the layer-changing via hole information is 0 and the length of the routing from the measuring point to the receiving end chip is greater than the routing length specification, generating a first mark;
and when the layer-changing via hole information is not 0, the routing length of the via hole from the receiving end chip is greater than the routing length specification, and the routing length from the measuring point to the receiving end chip is greater than the routing length specification, generating a first mark.
As a preferred embodiment, the signal test point detection system further comprises:
and the display module is used for displaying the signal lines corresponding to all the first marks.
As a preferred embodiment, the signal test point detection system further comprises:
the processing module is used for determining a measuring point adding area on the signal line according to the position of the receiving end chip;
correspondingly, the adding module 3 is specifically configured to:
and adding the measuring points on the measuring point adding area according to the test information and the wiring length specification of the measuring point distance receiving end chip, and updating the test information of the signal line.
As a preferred embodiment, the signal test point detection system further comprises:
and a result generation module for generating information corresponding to the detection result of the signal line.
In another aspect, the present application further provides an electronic device, including:
a memory for storing a computer program;
a processor for implementing the steps of the signal test point detection method as described in any one of the above embodiments when executing the computer program.
For an introduction of an electronic device provided in the present application, please refer to the above embodiments, which are not described herein again.
The electronic equipment provided by the application has the same beneficial effects as the signal test point detection method.
In another aspect, the present application further provides a computer-readable storage medium, on which a computer program is stored, and the computer program, when executed by a processor, implements the steps of the signal test point detection method as described in any one of the above embodiments.
For the introduction of a computer-readable storage medium provided in the present application, please refer to the above embodiments, which are not described herein again.
The computer-readable storage medium provided by the application has the same beneficial effects as the signal test point detection method.
It is further noted that, in the present specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A signal test point detection method is applied to a detection tool and comprises the following steps:
acquiring a PCB file;
receiving a signal line selection instruction and SI information, and determining a signal line and a receiving end chip in the PCB file according to the signal line selection instruction and the SI information;
and acquiring test information of the signal wire, and adding the test points on the signal wire according to the test information and the routing length specification of the distance between the test points and the receiving end chip.
2. The method of claim 1, wherein the test information comprises one or more of ID information, connection plane information, layer change via information, site information, and connected chip pin information.
3. The signal test point detection method of claim 2, further comprising:
and generating marking information of the signal wire according to the test information and/or the routing length specification, and storing the marking information into a database.
4. The method for detecting signal test points according to claim 3, wherein the process of generating the marking information of the signal lines according to the test information and/or the trace length specification specifically comprises:
when the layer changing through hole information is 0 and no measuring point exists, generating a first mark;
when the layer-changing via hole information is 0 and the routing length from the measuring point to the receiving end chip is greater than the routing length specification, generating the first mark;
and when the layer-changing via hole information is not 0, the routing length of the via hole from the receiving end chip is greater than the routing length specification, and the routing length from the measuring point to the receiving end chip is greater than the routing length specification, generating the first mark.
5. The signal test point detection method of claim 4, further comprising:
and displaying the signal lines corresponding to all the first marks.
6. The signal test point detection method of claim 1, further comprising:
determining a measuring point adding area on the signal line according to the position of the receiving end chip;
correspondingly, the process of adding the measuring points on the signal line according to the test information and the routing length specification of the measuring points from the receiving end chip specifically comprises the following steps:
and adding the measuring points on the measuring point adding area according to the test information and the routing length specification of the measuring points from the receiving end chip, and updating the test information of the signal line.
7. The signal test point detection method of any one of claims 1-6, further comprising:
information corresponding to the detection result of the signal line is generated.
8. A signal test point detection system for use in a detection tool, comprising:
the acquisition module is used for acquiring the PCB file;
the determining module is used for receiving a signal line selection instruction and SI information and determining a signal line and a receiving end chip in the PCB file according to the signal line selection instruction and the SI information;
and the adding module is used for acquiring the test information of the signal wire and adding the measuring points on the signal wire according to the test information and the routing length specification of the measuring points from the receiving end chip.
9. An electronic device, comprising:
a memory for storing a computer program;
a processor for implementing the steps of the signal test point detection method according to any one of claims 1 to 7 when executing said computer program.
10. A computer-readable storage medium, having stored thereon a computer program which, when being executed by a processor, carries out the steps of the signal test point detection method according to any one of claims 1 to 7.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010674399.7A CN111880076B (en) | 2020-07-14 | 2020-07-14 | Signal test point detection method, system and related assembly |
| PCT/CN2021/077383 WO2022012048A1 (en) | 2020-07-14 | 2021-02-23 | Signal test point detection method and system, and related components |
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| CN202010674399.7A CN111880076B (en) | 2020-07-14 | 2020-07-14 | Signal test point detection method, system and related assembly |
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| WO2022012048A1 (en) * | 2020-07-14 | 2022-01-20 | 苏州浪潮智能科技有限公司 | Signal test point detection method and system, and related components |
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| WO2022012048A1 (en) * | 2020-07-14 | 2022-01-20 | 苏州浪潮智能科技有限公司 | Signal test point detection method and system, and related components |
| CN112881899A (en) * | 2021-02-26 | 2021-06-01 | 合肥联宝信息技术有限公司 | Test point positioning method, device and equipment and readable storage medium |
| CN112881899B (en) * | 2021-02-26 | 2022-07-29 | 合肥联宝信息技术有限公司 | Test point positioning method, device and equipment and readable storage medium |
| CN113702801A (en) * | 2021-07-09 | 2021-11-26 | 苏州浪潮智能科技有限公司 | Signal measurement method and device of chip and related assembly |
| CN114137388A (en) * | 2021-11-25 | 2022-03-04 | 深圳市征阳电路科技有限公司 | Circuit board signal tracing detection system |
| CN114137388B (en) * | 2021-11-25 | 2024-05-28 | 深圳市三田技术科技有限公司 | Circuit board signal trace-searching detection system |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2022012048A1 (en) | 2022-01-20 |
| CN111880076B (en) | 2022-11-18 |
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