CN101470167A - Test point configuration method - Google Patents
Test point configuration method Download PDFInfo
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- CN101470167A CN101470167A CNA2007103073733A CN200710307373A CN101470167A CN 101470167 A CN101470167 A CN 101470167A CN A2007103073733 A CNA2007103073733 A CN A2007103073733A CN 200710307373 A CN200710307373 A CN 200710307373A CN 101470167 A CN101470167 A CN 101470167A
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Abstract
The invention provides a configuration method of test points, applied for printed circuit board with a plurality of through holes. The configuration method of test points is characterized by comprising: measuring the distances among each through holes and other through holes; according to the distances, adding first test points for each through hole or making the conductive wires connected with each through hole being high light; finely adjusting the conductive wires of high light to add second test points on the conductive wires.
Description
Technical field
The present invention relates to a kind of test point collocation method, particularly relate to a kind of test point collocation method of printed circuit board (PCB).
Background technology
Along with the prosperity day by day of electronic technology, electronic product also becomes people's necessity in life.And the printed circuit board (PCB) essential part of all electronic products especially.Yet because the electronic product function becomes increasingly complex, quality requirements is also more and more higher, and therefore, printed circuit board (PCB) is simple unlike usual electronic product.Increasing lead (wire), perforation (via) and printed circuit board (PCB) institute must carrying electronic package also get more and more.
In traditional technical field, for can testing printed circuit board, the engineering staff can add many test points (test point) on printed circuit board (PCB) usually.And this increases the action of test point, is mostly to utilize manually, according to the layout state of actual printed circuit board (PCB), increases the test point of different sizes.Owing to increase these test points is to utilize the area that strengthens Copper Foil on the perforation on the lead, therefore, has design specifications inspection (designrule check, problem DRC).For fear of the problem that this design specifications is checked, not all test point can be added on the perforation smoothly, therefore also must be by the position of manually adjusting lead and perforation.So not only the labor intensive cost when a large amount of production, can form leakage because of artificial carelessness again.
Summary of the invention
The present invention proposes a kind of configuration method of test points, automatically the suitable test point of configuration on printed circuit board (PCB).
The present invention proposes a kind of configuration method of test points, is suitable for printed circuit board (PCB), and printed circuit board (PCB) wherein has a plurality of perforations.The step that the invention is characterized in its described configuration method of test points comprises: at first, measure the spacing between each perforation and other perforation, then, according to these spacings, add first test point or the highlighted lead that is connected with each perforation at this perforation respectively.And, the lead that fine setting is highlighted, using increases by second test point on lead.
In one embodiment of this invention, it is described according to these spacings, adds that at each perforation the step of first test point or the highlighted lead that is connected with each perforation comprises: at first, judge that whether these spacings are all greater than first scope, if judged result is for being then to add first test point at each perforation; And if judged result is not, the lead that then highlighted (highlight) is connected with each perforation.
In one embodiment of this invention, wherein saidly judge that whether these spacings all comprise greater than the step of first scope: at first, judge the zone under each perforation; And, belong to the first area if judge each perforation, and during all greater than first fiducial value, then add first test point at each perforation with the pairing spacing of each perforation.And if judge that each perforation belongs to second area, and the pairing spacing of each perforation then adds first test point at each perforation all greater than second fiducial value.
In one embodiment of this invention, wherein said first area is bearing ball grid array (ball gridarray, the BGA) zone of packaged chip, and first fiducial value is 39.37 Mills.
In one embodiment of this invention, wherein said second fiducial value is more than or equal to 50 Mills.
In one embodiment of this invention, wherein said by the fine setting lead, the step that increases by second test point on lead also comprises: judge whether to have living space and finely tune above-mentioned lead.
In one embodiment of this invention, wherein saidly judge that this lead step of finely tuning of whether having living space also comprises: at first, judge whether this lead is the high speed signal lead; If judge that this lead is the high speed signal lead, whether can stride layer after then judging the perforation of finely tuning this lead simultaneously, and judge whether the conductor length behind the fine setting lead surpasses preset length, and judge whether can occur behind this lead of fine setting design specifications check wrong (design rulecheck, DRC).Opposite, if judge when this lead is not the high speed signal lead, judge then whether this lead of fine setting design specifications can occur and check mistake.
Among the embodiment that the present invention carries, the step of wherein said configuration method of test points also comprises: the aperture that dwindles perforation.
In one embodiment of this invention, the step of this lead that wherein said fine setting is highlighted also comprises: at respectively this perforation chronological order that adds this first test point, then search the lead that is highlighted in second scope of each perforation more in regular turn.
Above-mentioned explanation only is the general introduction of technical solution of the present invention, for can clearer understanding technological means of the present invention, and can be implemented according to the content of instructions, below with preferred embodiment of the present invention and conjunction with figs. describe in detail as after.
Description of drawings
Fig. 1 is the step synoptic diagram of configuration method of test points one embodiment.
Fig. 2 is the step synoptic diagram of another embodiment of configuration method of test points.
Embodiment
Below in conjunction with accompanying drawing and preferred embodiment, to its feature of configuration method of test points and the effect thereof that foundation the present invention proposes, describe in detail as after.
Below please refer to Fig. 1, Fig. 1 is the step synoptic diagram of an embodiment of configuration method of test points.Wherein the step of configuration method of test points 100 is, at first: measure the mutual spacing (S110) of all perforations on the printed circuit board (PCB).At this, also can be only do to measure at the distance between near perforation just passable, if the distance between two perforations can select not do measurement during significantly much larger than a scope (for example being 50 Mills).Then, then according to measured spacing of coming out, determine whether to add test point or want the lead (S120) that highlighted this perforation connected.Wherein, when measured spacing of coming out all greater than a value range, then can on this perforation, add a test point.And if measured spacing of coming out and during not all greater than above-mentioned scope, the lead that highlighted this perforation connected then, make that it can be conspicuous by identification.
What deserves to be mentioned is that at this above-mentioned mentioned scope is set up on their own by the user.For instance, if can there be fiducial value more among a small circle the perforation position when being used for bearing ball grid array packaging chip regional.Requirement according to the chip of general BGA Package is 39.37 Mills.If not and the position is in this when zone, then this scope fiducial value can be bigger, is generally 50 ~ 70 Mills.
The step of the above-mentioned configuration method of test points that continues is finely tuned at the lead that these are highlighted again, and the purpose of fine setting is to be to move out enough big space, increases test point (S130).And this test point that increases through fine setting comprises and being increased on the lead, also can be increased on the perforation that lead connects therewith.
In addition, in the action of fine setting lead, can be restricted because of the attribute of lead.The most basic is general lead, and this general lead is put only need be limited in and design specifications can not be occurred and check wrong getting final product.And another kind of special lead is exactly the high speed signal lead about transmitting high-frequency signal.When adjusting this lead, generally include following restriction: the first, can not stride layer through the high speed signal lead after the fine setting.This high speed signal lead is because transmitting high-frequency signal wishes do not have excessive impedance on its delivering path, usually to avoid transmitting the distorted signals of being shone.Therefore, do not wish that this lead can stride layer.The second, the conductor length behind the high speed signal lead cannot not surpass preset length after adjustment, be in order to lower the impedance in the transmission path equally.The 3rd, finely tune this high speed signal lead after, can not occur design specifications equally and check mistake.
And if through behind the fine setting lead, still can't have enough space to increase test point, then can dwindle the aperture of perforation, the aperture of general perforation has 35 Mills, 30 Mills and 26 Mills to provide selection for three kinds.
Below will reintroduce an embodiment and further specify the configuration method of test points that this is put forward.
Please refer to Fig. 2, Fig. 2 is the step synoptic diagram of another embodiment of configuration method of test points.When step begins, measure the spacing between all perforations, perforation wherein if with other perforation all remain on more than 50 Mills apart from the time, just add test point (S210) at this perforation.To add not then that then the lead height that perforation connected of test point puts forward (S220).Then, numbering in regular turn at the perforation that adds test point (for example has 20 perforations, then numbering these perforations is 1 ~ No. 20), this method of numbering in regular turn can be any, that is for example carried in the present embodiment numbers (S230), (can certainly change into from right to left, wait from the bottom to top) according to perforation from left to right, from top to bottom in the position of printed circuit board (PCB).Again according to the order of numbering, come on every side in 50 Mills, to make not have and to find the lead (S240) that is highlighted at perforation (for example earlier at No. 1 perforation).If find, then this lead is finely tuned (S250).If can not find, then continue to come (for example being No. 2 perforations) to carry out execution in step S240 at the perforation (S2A0) of next one numbering.
And then above-mentioned steps, if enough spaces are arranged finely tunes, then can increase test point (S270) smoothly, if there are not enough spaces to finely tune, whether the zone of then judging this perforation place is to be used for the zone (S260) of bearing ball grid array packaging chip.If, then change the original sentence to disconnected perforation with other whether all remain on 39.37 Mills above apart from the time.If then can increase test point (S280) smoothly.
Then judging whether to handle all perforations (S290) (present embodiment is 20 perforations), if just can finish action to this printed circuit board (PCB) configuration testing point, if not, then recover execution in step 2A0.
Replenish a bit more in addition,, find that the lead that is highlighted in addition is not processed to, the scope of 50 Mills among the step S240 can be increased (for example being 100 Mills), continue execution in step S240 again if handle the perforation of all numberings.
The above, it only is preferred embodiment of the present invention, be not that the present invention is done any pro forma restriction, though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention, any those skilled in the art, in not breaking away from the technical solution of the present invention scope, when the structure that can utilize above-mentioned announcement and technology contents are made a little change or be modified to the equivalent embodiment of equivalent variations, but every content that does not break away from technical solution of the present invention, according to technical spirit of the present invention to any simple modification that above embodiment did, equivalent variations and modification all still belong in the scope of technical solution of the present invention.
Claims (9)
1, a kind of configuration method of test points is suitable for a printed circuit board (PCB), and this printed circuit board (PCB) has a plurality of perforations, it is characterized in that the step of described configuration method of test points comprises:
Measure the respectively a plurality of spacings between this perforation and other perforation;
According to those spacings, add one first test point or a highlighted lead that is connected with this perforation respectively at this perforation respectively; And
This lead of being highlighted of fine setting, use on this lead or with perforation that this lead is connected on increase by one second test point.
2, configuration method of test points according to claim 1 is characterized in that describedly according to those spacings, adds that at this perforation respectively the step of this first test point or highlighted this lead that is connected with this perforation respectively comprises:
Judge that whether those spacings are all greater than one first scope;
If judged result is for being, then add this first test point at this perforation respectively; And
If judged result is not for, then highlighted this lead that is connected with this perforation respectively.
3, configuration method of test points according to claim 2 is characterized in that describedly judging that whether those spacings all comprise greater than the step of this first scope:
Judge the respectively affiliated zone of this perforation;
If judge that respectively this perforation belongs to a first area, and respectively pairing those spacings of this perforation then add this first test point at this perforation respectively all greater than one first fiducial value; And
If judge that respectively this perforation belongs to a second area, and respectively pairing those spacings of this perforation then add this first test point at this perforation respectively all greater than one second fiducial value.
4, configuration method of test points according to claim 3 it is characterized in that wherein this first area is the zone of bearing ball grid array packaging chip, and this first fiducial value is 39.37 Mills.
5, configuration method of test points according to claim 3 is characterized in that wherein this second fiducial value is more than or equal to 50 Mills.
6, configuration method of test points according to claim 1, it is characterized in that described by this lead of fine setting, on this lead or with perforation that this lead is connected on the step of this second test point of increase also comprise:
Judge whether this lead has living space and finely tune.
7, configuration method of test points according to claim 6 is characterized in that describedly judging that this lead step of finely tuning of whether having living space also comprises:
Judge whether this lead is a high speed signal lead;
If judging this lead be this high speed signal lead, whether can stride layer after then judging the perforation of this lead of fine setting, and judge whether the conductor length behind the fine setting lead surpasses preset length, and design specifications inspection mistake whether can occur after judging this lead of fine setting; And
If judge that this lead is not the high speed signal lead, judge then whether this lead of fine setting design specifications can occur and check mistake.
8, configuration method of test points according to claim 1 is characterized in that the step of described configuration method of test points also comprises:
Dwindle the aperture of those perforations.
9, configuration method of test points according to claim 1 is characterized in that the step of this lead that described fine setting is highlighted also comprises:
At respectively this perforation chronological order that adds this first test point; And
Search this lead that is highlighted in this perforation one second scope respectively in regular turn.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2007103073733A CN101470167A (en) | 2007-12-28 | 2007-12-28 | Test point configuration method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2007103073733A CN101470167A (en) | 2007-12-28 | 2007-12-28 | Test point configuration method |
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| Publication Number | Publication Date |
|---|---|
| CN101470167A true CN101470167A (en) | 2009-07-01 |
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| CNA2007103073733A Pending CN101470167A (en) | 2007-12-28 | 2007-12-28 | Test point configuration method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022012048A1 (en) * | 2020-07-14 | 2022-01-20 | 苏州浪潮智能科技有限公司 | Signal test point detection method and system, and related components |
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2007
- 2007-12-28 CN CNA2007103073733A patent/CN101470167A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022012048A1 (en) * | 2020-07-14 | 2022-01-20 | 苏州浪潮智能科技有限公司 | Signal test point detection method and system, and related components |
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Open date: 20090701 |