CN111858428B - Server and communication management circuit of BIOS thereof - Google Patents
Server and communication management circuit of BIOS thereof Download PDFInfo
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- CN111858428B CN111858428B CN202010595800.8A CN202010595800A CN111858428B CN 111858428 B CN111858428 B CN 111858428B CN 202010595800 A CN202010595800 A CN 202010595800A CN 111858428 B CN111858428 B CN 111858428B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/32—Monitoring with visual or acoustical indication of the functioning of the machine
- G06F11/324—Display of status information
- G06F11/325—Display of status information by lamps or LED's
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/30—Authentication, i.e. establishing the identity or authorisation of security principals
- G06F21/44—Program or device authentication
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/60—Software deployment
- G06F8/65—Updates
Abstract
The invention discloses a server and a communication management circuit of a BIOS (basic input/output system), wherein a user can control a BMC (baseboard management controller) to send a first preset level to a level trigger circuit when the BIOS needs to be upgraded by the BMC, the level trigger circuit can trigger a link selection circuit to conduct a communication link between the BMC and the BIOS, the communication link between the CPU and the BIOS can be conducted by stopping sending the first preset level when the BIOS is not required to be upgraded by the BMC so as to facilitate normal startup of the server, since the communication management circuit in the present application includes only two-part circuits of level trigger circuit and link selection circuit, the execution of the code program is not involved, the development and the maintenance of the program are not needed at first, the cost is reduced, and when the configuration data of the BIOS is sent to the CPU, the time delay caused by the execution of the code program is reduced, and the CPU can improve the data receiving frequency, thereby improving the starting speed.
Description
Technical Field
The invention relates to the field of servers, in particular to a communication management circuit of a BIOS (basic input/output system), and further relates to a server.
Background
The BIOS (Basic Input Output System) is an important component in the server, and the BIOS stores the configuration data required by the CPU to execute the server startup, when the server is started, the CPU needs to acquire configuration data from the BIOS and complete a starting process of the server, and in the server in the prior art, data communication between the CPU and the BIOS can be realized by using a CPLD (Complex Programmable Logic Device) as a bridge, however, since the CPLD belongs to a device for executing a program, before the CPLD transmits the configuration data required by the CPU transmitted by the BIOS to the CPU, the CPLD needs to perform the operation of program codes in addition to the time delay of its own hardware circuit, which increases the time delay of transmitting data to the CPU, therefore, the CPU can acquire the configuration data and complete the startup only by reducing the data receiving frequency, so that the startup speed of the server becomes slow; moreover, technicians often need to upgrade programs of the BIOS through the BMC, and at this time, the CPLD is needed to transfer communication objects of the BIOS from the CPU to the BMC and back to the CPU after the upgrade is completed, which requires development and maintenance of corresponding programs inside the CPLD, and thus, the cost is high.
Therefore, how to provide a solution to the above technical problem is a problem that needs to be solved by those skilled in the art.
Disclosure of Invention
The invention aims to provide a communication management circuit of a BIOS (basic input output System), which does not need to develop and maintain programs, reduces the cost, reduces the time delay caused by the execution of code programs when the configuration data of the BIOS is sent to a CPU (central processing unit), and can improve the data receiving frequency of the CPU, thereby improving the starting speed; another object of the present invention is to provide a server including the communication management circuit of the above-mentioned BIOS, which does not need to develop and maintain a program, reduces the cost, and reduces the time delay caused by the execution of a code program when the configuration data of the BIOS is sent to the CPU, so that the CPU can increase the data receiving frequency, thereby increasing the boot speed.
To solve the above technical problem, the present invention provides a communication management circuit of BIOS, including:
the level trigger circuit is connected with a first control level end of the BMC and the link selection circuit and is used for generating a first trigger signal when the first control level end outputs a first preset level;
the link selection circuit is respectively connected with the communication end of the CPU, the communication end of the BMC and the communication end of the BIOS and is used for controlling the link between the communication end of the BMC and the communication end of the BIOS to be conducted when receiving the first trigger signal and controlling the link between the communication end of the CPU and the communication end of the BIOS to be conducted when not receiving the first trigger signal.
Preferably, the level trigger circuit is further connected with a second control level end of the security card;
the link selection circuit is also connected with the communication end of the security card;
the level trigger circuit is also used for generating a second trigger signal when receiving a second preset level sent by the second control level end;
the link selection circuit is further used for controlling the link conduction between the communication end of the security card and the communication end of the BIOS when receiving the second trigger signal;
the controlling the link conduction between the communication end of the CPU and the communication end of the BIOS when the first trigger signal is not received specifically includes:
when the first trigger signal and the second trigger signal are not received, controlling the link between the communication end of the CPU and the communication end of the BIOS to be conducted;
wherein the first trigger signal and the second trigger signal have different priorities.
Preferably, the priority of the first trigger signal is higher than the priority of the second trigger signal.
Preferably, the level trigger circuit and the link selection circuit are integrally a first signal switch;
a first level detection end of the first signal change-over switch is connected with a first control level end of the BMC, a first communication end of the first signal change-over switch is connected with a communication end of the BIOS, a second communication end of the first signal change-over switch is connected with a communication end of the CPU, and a third communication end of the first signal change-over switch is connected with a communication end of the BMC;
the first signal switch is configured to control the first communication terminal to be conducted with the third communication terminal when the first control level terminal outputs the first preset level, and control the first communication terminal to be conducted with the second communication terminal when the first control level terminal does not output the first preset level.
Preferably, the communication management circuit of the BIOS further includes a second signal switch;
a second level detection end of the second signal change-over switch is connected with a second control level end of the security card, a first communication end of the second signal change-over switch is connected with a second communication end of the first signal change-over switch, a second communication end of the second signal change-over switch is connected with a communication end of the security card, and a third communication end of the second signal change-over switch is connected with a communication end of the CPU;
the second signal switch is configured to control the first communication terminal to be conducted with the second communication terminal when the second control level terminal outputs a second preset level, and control the first communication terminal to be conducted with the third communication terminal when the second control level terminal does not output the second preset level.
Preferably, the communication management circuit of the BIOS further includes a prompting device connected to the second control level terminal;
and the prompting device is used for prompting that safety verification is carried out when the second control level end outputs the second preset level.
Preferably, the prompting device comprises a processor and a prompter;
and the processor is used for controlling the prompter to prompt that safety verification is carried out when the second preset level is output by the second control level end.
Preferably, the processor is the BMC.
Preferably, the prompter is a Light Emitting Diode (LED).
In order to solve the above technical problem, the present invention further provides a server including the communication management circuit of the BIOS according to any one of the above embodiments.
The invention provides a communication management circuit of a BIOS (basic input/output system). in the application, when a user needs to upgrade the BIOS through a BMC (baseboard management controller), the BMC can be controlled to send a first preset level to a level trigger circuit, the level trigger circuit can trigger a link selection circuit to conduct a communication link between the BMC and the BIOS, the communication link between the CPU and the BIOS can be conducted by stopping sending the first preset level when the BIOS is not required to be upgraded by the BMC so as to facilitate normal startup of the server, since the communication management circuit in the present application includes only two-part circuits of level trigger circuit and link selection circuit, the execution of the code program is not involved, the development and the maintenance of the program are not needed at first, the cost is reduced, and when the configuration data of the BIOS is sent to the CPU, the time delay caused by the execution of the code program is reduced, and the CPU can improve the data receiving frequency, thereby improving the starting speed.
The invention also provides a server which has the same beneficial effects as the communication management circuit of the BIOS.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed in the prior art and the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
FIG. 1 is a schematic structural diagram of a communication management circuit of a BIOS according to the present invention;
fig. 2 is a schematic structural diagram of another communication management circuit of the BIOS according to the present invention.
Detailed Description
The core of the invention is to provide a communication management circuit of BIOS, which does not need to develop and maintain programs, reduces the cost, reduces the time delay caused by the execution of code programs when the configuration data of BIOS is sent to the CPU, and the CPU can improve the data receiving frequency, thereby improving the starting speed; another core of the present invention is to provide a server including the communication management circuit of the above-mentioned BIOS, which does not require development and maintenance of a program, reduces cost, and reduces time delay caused by execution of a code program when sending configuration data of the BIOS to the CPU, so that the CPU can increase data reception frequency, thereby increasing the boot speed.
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a communication management circuit of a BIOS according to the present invention, the communication management circuit of the BIOS includes:
the level trigger circuit 1 is connected with a first control level terminal S1 of the BMC and the link selection circuit 2, and is configured to generate a first trigger signal when the first control level terminal S1 outputs a first preset level;
and the link selection circuit 2 is respectively connected with the communication end of the CPU, the communication end of the BMC and the communication end of the BIOS and is used for controlling the link between the communication end of the BMC and the communication end of the BIOS to be conducted when receiving the first trigger signal and controlling the link between the communication end of the CPU and the communication end of the BIOS to be conducted when not receiving the first trigger signal.
Specifically, in view of the technical problems in the background art, the embodiment of the present invention only includes two circuits, namely, the level trigger circuit 1 and the link selection circuit 2, and both of them do not execute a program, but only process a signal through a hardware circuit to implement switching of a communication link.
Specifically, when a user needs to update the BIOS, a first preset level may be sent to the level trigger circuit 1 through the BMC, then the level trigger circuit 1 may generate a first trigger signal, and the link selection circuit 2 may control the communication terminal of the BMC to be conducted with the communication terminal of the BIOS in response to the first trigger signal, at this time, the user may update the program in the BIOS through the BMC, after the update operation is completed, the user also needs to stop sending the first preset level to the level trigger circuit 1 through the BMC, so that the link selection circuit 2 controls the communication terminal of the CPU to be conducted with the communication terminal of the BIOS, and the CPU may smoothly obtain configuration data from the BIOS and complete a boot process in a boot process of the server.
The first preset level may be set autonomously, for example, the first preset level may be set to a high level or a low level, and the embodiment of the present invention is not limited herein.
After the time delay for forwarding the configuration data from the BIOS to the CPU is reduced, due to the reduction of the time delay, the low time delay can meet the shorter longest waiting time corresponding to the higher data receiving frequency, for example, when the SPI frequency of the CPU is AMHz, the longest waiting time corresponding to the CPU is B seconds, and B decreases as a result of the increase of a.
The invention provides a communication management circuit of a BIOS (basic input/output system). in the application, when a user needs to upgrade the BIOS through a BMC (baseboard management controller), the BMC can be controlled to send a first preset level to a level trigger circuit, the level trigger circuit can trigger a link selection circuit to conduct a communication link between the BMC and the BIOS, the communication link between the CPU and the BIOS can be conducted by stopping sending the first preset level when the BIOS is not required to be upgraded by the BMC so as to facilitate normal startup of the server, since the communication management circuit in the present application includes only two-part circuits of level trigger circuit and link selection circuit, the execution of the code program is not involved, the development and the maintenance of the program are not needed at first, the cost is reduced, and when the configuration data of the BIOS is sent to the CPU, the time delay caused by the execution of the code program is reduced, and the CPU can improve the data receiving frequency, thereby improving the starting speed.
For better explaining the embodiment of the present invention, please refer to fig. 2, fig. 2 is a schematic structural diagram of another communication management circuit of BIOS according to the present invention, and based on the above embodiment:
as a preferred embodiment, the level trigger circuit 1 is further connected to a second control level terminal S2 of the security card;
the link selection circuit 2 is also connected with a communication end of the security card;
the level trigger circuit 1 is further configured to generate a second trigger signal when receiving a second preset level sent by a second control level terminal S2;
the link selection circuit 2 is further configured to control a link between the communication end of the security card and the communication end of the BIOS to be conducted when receiving the second trigger signal;
when the first trigger signal is not received, the specific step of controlling the link conduction between the communication end of the CPU and the communication end of the BIOS is:
when the first trigger signal and the second trigger signal are not received, controlling the link between the communication end of the CPU and the communication end of the BIOS to be conducted;
the priorities of the first trigger signal and the second trigger signal are different.
Specifically, in the server with the security configuration, before the server is powered on, the security card needs to communicate with the BIOS for security verification, that is, hardware that needs to communicate with the BIOS is added with a security card, so the communication management circuit in the embodiment of the present invention additionally monitors the second control level terminal S2 of the security card, when the security card needs to communicate with the BIOS, the communication management circuit sends the second preset level to the level trigger circuit 1, at this time, the second trigger signal generated by the level trigger circuit 1 triggers the link selection circuit 2 to control the communication link between the BIOS and the security card to be turned on, and of course, after the security verification operation of the security card is finished, the sending of the second preset level may also be stopped, so as to recover the normal power on of the communication link between the CPU and the BIOS, without affecting the normal power on of the server.
In consideration of that, if the priorities of the first trigger signal and the second trigger signal are the same, the link selection circuit 2 cannot decide which link is turned on, so that the priorities of the first trigger signal and the second trigger signal need to be distinguished, and as to which link has a higher priority, the link selection circuit can be set autonomously.
Specifically, considering that the default level state of the second control level terminal S2 in the security card is a low level, the second preset level may be set to a high level, that is, the communication between the BIOS and the communication link of the BIOS is triggered by the high level when the security card needs to perform security verification, and the communication link between the CPU and the BIOS is conducted in the remaining default state, so that a part of energy may be saved.
As a preferred embodiment, the priority of the first trigger signal is higher than the priority of the second trigger signal.
Specifically, it is considered that if the priority of the second trigger signal is higher than the priority of the first trigger signal, the first trigger signal controls the BIOS to communicate with the BMC, that is, in the process of upgrading the program of the BIOS, the user starts the server under the unknown condition, and then the security card enables the level trigger circuit 1 to generate the second trigger signal through the second preset level, so that the communication between the BIOS and the BMC is terminated at this time, which directly results in the failure of upgrading.
Of course, the priority of the second trigger signal may also be higher than that of the first trigger signal, and the embodiment of the present invention is not limited herein.
As a preferred embodiment, the whole of the level trigger circuit 1 and the link selection circuit 2 is a first signal switch;
a first level detection end of the first signal change-over switch is connected with a first control level end S1 of the BMC, a first communication end A1 of the first signal change-over switch is connected with a communication end of the BIOS, a second communication end B1 of the first signal change-over switch is connected with a communication end of the CPU, and a third communication end B2 of the first signal change-over switch is connected with a communication end of the BMC;
the first signal switch is configured to control the first communication terminal and the third communication terminal to be conducted when the first control level terminal S1 outputs the first preset level, and to control the first communication terminal and the second communication terminal to be conducted when the first control level terminal S1 does not output the first preset level.
Specifically, the signal change-over switch has the advantages of small size, simple structure, low time delay, long service life and the like.
Of course, the level trigger circuit 1 and the link selection circuit 2 may be of other types besides the signal switch, and the embodiment of the present invention is not limited herein.
As a preferred embodiment, the communication management circuit of the BIOS further includes a second signal changeover switch;
the second level detection end of the second signal change-over switch is connected with the second control level end S2 of the safety card, the first communication end A2 of the second signal change-over switch is connected with the second communication end B1 of the first signal change-over switch, the second communication end B3 of the second signal change-over switch is connected with the communication end of the safety card, and the third communication end B4 of the second signal change-over switch is connected with the communication end of the CPU;
and a second signal switch for controlling the conduction between the first communication terminal and the second communication terminal when the second control level terminal S2 outputs the second preset level, and controlling the conduction between the first communication terminal and the third communication terminal when the second control level terminal S2 does not output the second preset level.
Specifically, the switching of the three-way communication link can be realized through the first signal selector switch and the second signal selector switch, and the three-way communication link has lower cost and smaller volume.
Of course, besides the two signal switch switches, the three-way communication link may also be switched by other types of circuits, and the embodiment of the present invention is not limited herein.
In a preferred embodiment, the communication management circuit of the BIOS further includes a prompting device connected to the second control level terminal S2;
the prompting device is used for prompting that the safety check is being carried out when the second control level terminal S2 outputs the second preset level.
Specifically, since the priority of the first trigger signal is higher, in order to prevent the security card from being interrupted by the BMC during the security verification, the prompting device may prompt that the security verification is being performed when the second preset level is detected, so as to remind the user that the BIOS cannot be upgraded at this time, thereby preventing interruption of the security verification process.
Specifically, the specific structure of the prompting device may be various, and the embodiment of the present invention is not limited herein.
As a preferred embodiment, the prompting device comprises a processor and a prompter;
and the processor is used for controlling the prompter to prompt that the safety check is carried out when the second control level terminal S2 outputs a second preset level.
Specifically, the combined structure of the processor and the prompter is simple, the size is small, and the service life is long.
Of course, besides the above forms, the specific structure of the prompting device may be of various types, and the embodiment of the present invention is not limited herein.
In a preferred embodiment, the processor is a BMC.
Specifically, the BMC is an original processor in the server, so that cost can be saved.
Of course, the processor may be of various types other than the BMC, and the embodiment of the present invention is not limited herein.
In a preferred embodiment, the indicator is a light emitting diode, LED.
Specifically, the LED has the advantages of small size, simple structure, and low cost.
Of course, besides the LED, the prompter may be of other types, and the embodiment of the present invention is not limited herein.
The invention also provides a server comprising the communication management circuit of the BIOS as in the previous embodiments.
For the introduction of the server provided by the present invention, please refer to the aforementioned embodiment of the communication management circuit of the BIOS, which is not described herein again.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. It is further noted that, in the present specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. The term "comprising", without further limitation, means that the element so defined is not excluded from the group consisting of additional identical elements in the process, method, article, or apparatus that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (9)
1. A communication management circuit of a BIOS, comprising:
the level trigger circuit is connected with a first control level end of the BMC and the link selection circuit and is used for generating a first trigger signal when the first control level end outputs a first preset level;
the link selection circuit is respectively connected with the communication end of the CPU, the communication end of the BMC and the communication end of the BIOS and is used for controlling the link between the communication end of the BMC and the communication end of the BIOS to be conducted when receiving the first trigger signal and controlling the link between the communication end of the CPU and the communication end of the BIOS to be conducted when not receiving the first trigger signal;
the level trigger circuit and the link selection circuit form a whole which is a first signal change-over switch;
a first level detection end of the first signal change-over switch is connected with a first control level end of the BMC, a first communication end of the first signal change-over switch is connected with a communication end of the BIOS, a second communication end of the first signal change-over switch is connected with a communication end of the CPU, and a third communication end of the first signal change-over switch is connected with a communication end of the BMC;
the first signal switch is configured to control the first communication terminal to be conducted with the third communication terminal when the first control level terminal outputs the first preset level, and control the first communication terminal to be conducted with the second communication terminal when the first control level terminal does not output the first preset level.
2. The communication management circuit of the BIOS of claim 1, wherein the level trigger circuit is further connected to a second control level terminal of the security card;
the link selection circuit is also connected with the communication end of the security card;
the level trigger circuit is also used for generating a second trigger signal when receiving a second preset level sent by the second control level end;
the link selection circuit is further used for controlling the link conduction between the communication end of the security card and the communication end of the BIOS when receiving the second trigger signal;
the controlling the link conduction between the communication end of the CPU and the communication end of the BIOS when the first trigger signal is not received specifically includes:
when the first trigger signal and the second trigger signal are not received, controlling the link between the communication end of the CPU and the communication end of the BIOS to be conducted;
wherein the first trigger signal and the second trigger signal have different priorities.
3. The BIOS communication management circuit of claim 2 wherein the first trigger signal has a higher priority than the second trigger signal.
4. The BIOS communication management circuit of claim 1 further comprising a second signal switch;
a second level detection end of the second signal change-over switch is connected with a second control level end of the security card, a first communication end of the second signal change-over switch is connected with a second communication end of the first signal change-over switch, a second communication end of the second signal change-over switch is connected with a communication end of the security card, and a third communication end of the second signal change-over switch is connected with a communication end of the CPU;
the second signal switch is configured to control the first communication terminal to be conducted with the second communication terminal when the second control level terminal outputs a second preset level, and control the first communication terminal to be conducted with the third communication terminal when the second control level terminal does not output the second preset level.
5. The BIOS communication management circuit of any one of claims 2-4 further comprising a hint device connected to the second control level terminal;
and the prompting device is used for prompting that safety verification is carried out when the second control level end outputs the second preset level.
6. The BIOS communication management circuit of claim 5 wherein the hinting means comprises a processor and a hint;
and the processor is used for controlling the prompter to prompt that safety verification is carried out when the second preset level is output by the second control level end.
7. The BIOS communication management circuit of claim 6 wherein the processor is the BMC.
8. The BIOS communication management circuit of claim 6 wherein the prompt is a Light Emitting Diode (LED).
9. A server, characterized by comprising the communication management circuit of the BIOS of any one of claims 1 to 8.
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| CN104503783A (en) * | 2014-12-11 | 2015-04-08 | 华为技术有限公司 | Method and server for presenting initialization degree of server hardware |
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| CN103488498B (en) * | 2013-09-03 | 2017-02-22 | 华为技术有限公司 | Computer booting method and computer |
| US9965367B2 (en) * | 2014-12-17 | 2018-05-08 | Quanta Computer Inc. | Automatic hardware recovery system |
| GB2545010B (en) * | 2015-12-03 | 2018-01-03 | Garrison Tech Ltd | Secure boot device |
| CN105975382B (en) * | 2016-05-13 | 2019-01-08 | 深圳市同泰怡信息技术有限公司 | A kind of alarm method that hardware configuration changes |
| CN107168829B (en) * | 2017-05-15 | 2021-02-09 | 苏州浪潮智能科技有限公司 | Method and system for ensuring safe and reliable operation of double BIOS of server system |
| CN107480011B (en) * | 2017-08-23 | 2020-11-06 | 英业达科技有限公司 | BIOS switching device |
| CN107908413A (en) * | 2017-11-20 | 2018-04-13 | 山东超越数控电子股份有限公司 | A kind of method of Domestic Platform remote maintenance mainboard BIOS |
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| CN104503783A (en) * | 2014-12-11 | 2015-04-08 | 华为技术有限公司 | Method and server for presenting initialization degree of server hardware |
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