CN105975382B - A kind of alarm method that hardware configuration changes - Google Patents
A kind of alarm method that hardware configuration changes Download PDFInfo
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- CN105975382B CN105975382B CN201610322400.3A CN201610322400A CN105975382B CN 105975382 B CN105975382 B CN 105975382B CN 201610322400 A CN201610322400 A CN 201610322400A CN 105975382 B CN105975382 B CN 105975382B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/32—Monitoring with visual or acoustical indication of the functioning of the machine
- G06F11/324—Display of status information
- G06F11/327—Alarm or error message display
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Abstract
The present invention relates to the alarm methods that computer field more particularly to a kind of hardware configuration change；Detecting system hardware changes this method in the power-offstate, includes power supply and without two kinds of off-modes of power supply；After hardware configuration changes, hardware triggered interrupts obtain platform configuration information by BIOS SMI program, complete the storage of configuration information by BMC and differentiation is shown, three, which cooperates, to be completed for platform configuration information to be promptly and accurately recorded on platform body；After hardware information changes, BIOS can according to demand, and setting courses of action versatile and flexible may be configured as no operation, perhaps show warning message be further continued for running or Break-Up System member to be managed confirm safety after be further continued for running；BMC storage information enters EEPROM, information can still be saved and not disappeared after power-off, and BMC display interface is research staff, tester, client provide unified information platform, improve communication efficiency, configuration varianceization is shown twice, and client hardware can be reminded to change point.
Description
Technical Field
The invention relates to the field of computers, in particular to an alarm method for hardware configuration change.
Background
In the research and development process of the server mainboard, a large number of compatibility tests are carried out, platform systems with various configurations are required to be formed by CPUs (central processing units), internal memories, different external cards and the like in various models, then tests such as long-time stability, pressure and the like are carried out, testers record platform configuration information, and once test problems occur, the test problems are conveniently traced and supplied to research and development personnel for analysis.
The server can also carry out a large number of tests before the terminal client is formally put into use, expansion cards can be increased or decreased manually after the terminal client is put into use, the change condition of the configuration information of the server also needs to be recorded, and once the server is unstable, the problem can be analyzed quickly by a system administrator.
However, in the current testing process, the testing machine and the machine configuration information record are separated, which results in the configuration information being easily lost or mixed up between different machines. Other personnel test or the user has changed the hardware configuration of platform in the use and probably can not be recorded, and different personnel obtain the configuration information of the board, also do not have unified information interface, but need to communicate and confirm repeatedly etc. these factors have undoubtedly increased the communication cost, have increased the degree of difficulty and the accuracy of obtaining the information of tracing back, have reduced the validity of testing.
Once the extended configuration causes the system to be unstable, the system administrator troubleshooting errors will reduce efficiency much. Once the existing expansion card in the server is damaged and cannot be used, a system administrator needs to be informed in time through a technical means, or the expansion card is removed or replaced, so that the instability of the system caused by the damaged card is avoided. The recording of the hardware configuration information may not be regarded by people, may not be recorded, or may not be recorded comprehensively due to professional level reasons, and when a system fails, effective information data cannot be provided for an analyst quickly. These all reduce the efficiency of operation.
Therefore, a motherboard or a method for reporting the change of the relevant personnel after the hardware configuration is changed is needed, so that the working efficiency of computer maintenance personnel is improved.
Disclosure of Invention
The invention aims to provide an alarm method for hardware configuration change, and aims to solve the problem that the configuration of a mainboard of an existing computer cannot be actively reported after being changed.
The invention is realized by the following steps: the alarm method for hardware configuration change is characterized by comprising the following steps:
A. a detection step: the detection step is that the configuration circuit detects whether the configuration of the mainboard is changed, if not, the operation is not carried out; if yes, sending an electric signal to the BIOS; the configuration circuit is arranged on the mainboard and converts the change of the mainboard configuration into an electric signal; BIOS (basic Input Output System) refers to a basic Input Output system, and is mainly used for initialization and detection of various hardware devices in the computer startup process
B. A reading step: the reading step is that the BIOS reads the configuration information of the mainboard after receiving the electric signal transmitted by the configuration circuit;
C. a storage step: the storage step is that the BIOS transmits the read mainboard configuration information to the BMC and stores the mainboard configuration information into the EEPROM of the BMC; bmc (baseboard Management controller) refers to a baseboard Management controller. The IPMI standard is built in a mainboard and supports the IPMI standard of the industry standard. The functions provided by the BMC include: local and remote diagnostics, console support, configuration management, hardware management, and troubleshooting.
D. A comparison step: and the comparison step is that the BMC reads the configuration information of the two groups of the latest mainboards in the EEPROM and identifies the changed configuration information. EEPROM is a non-volatile storage medium and is the main storage medium for BMC.
The further technical scheme of the invention is as follows: and the configuration circuit sends an electric signal to the BIOS after detecting that the level of the in-place signals of the CPU socket and the PCIE slot is changed.
The further technical scheme of the invention is as follows: the configuration circuit further comprises a standby power supply, and the standby power supply is connected with the CPU socket and the PCIE slot through a resistor R1; the CPU socket and the PCIE slot are grounded through a resistor R2; the resistance value of the R2 is more than 5 times of the resistance value of the R1.
The further technical scheme of the invention is as follows: the configuration circuit further comprises a real-time clock power supply, and the real-time clock power supply is connected with the CPU socket and the PCIE slot through a resistor R1. The real-time clock power supply is an RTC power supply for short, the voltage of the real-time clock power supply is 3.3V and is the same as that of a standby power supply, the reliability of the whole system is guaranteed by simultaneously connecting two power supplies, the system is generally supplied with power through the standby power supply, and the RTC power supply is used for supplying power when power failure or other special conditions occur.
The further technical scheme of the invention is as follows: the configuration circuit comprises a monostable Schmitt circuit connected with the CPU socket and the PCIE slot. The monostable schmitt circuit is a circuit obtained by combining a monostable circuit and a schmitt circuit. A monostable circuit (monostable circuit) is a basic pulse unit circuit having both steady and transient operating states. When no external signal is triggered, the circuit is in a steady state. Under the trigger of an applied signal, the circuit is overturned from a steady state to a transient state, and after a period of time, the circuit automatically returns to the steady state again. The duration of the transient time depends on the parameters of the circuit itself, and is independent of the duration of the trigger signal. The Schmitt trigger is used in the Schmitt circuit, has two stable states, but is different from the common trigger in that the Schmitt trigger adopts a potential triggering mode, and the state of the Schmitt trigger is maintained by the potential of an input signal; for input signals with two different changing directions of negative decreasing and positive increasing, the Schmitt trigger has different threshold voltages.
The further technical scheme of the invention is as follows: the monostable Schmitt circuit is connected with the PCH register. PCH (platform Controller hub) is an Intel corporation integrated south bridge.
The further technical scheme of the invention is as follows: the step A comprises the following sub-steps:
A1. maintaining the level of the monostable schmitt circuit high;
A2. the level of the in-place signals of the CPU socket and the PCIE slot changes to invert the monostable Schmitt circuit to temporarily output a low level, and then the high level is recovered;
A3. the status bit INTRD _ DET in the PCH register is set to 1 state upon receipt of a low level from the monostable schmitt circuit.
The further technical scheme of the invention is as follows: the step B comprises the following sub-steps:
B1. the BIOS detects a status bit INTRD _ DET in the PCH register;
B2. if the status bit INTRD _ DET in the PCH register is 0, no operation is performed, and if the status bit INTRD _ DET in the PCH register is 1, the process proceeds to step B3;
B3. and the BIOS enters an SMI interrupt program, and the SMI interrupt program is used for reading the mainboard configuration information by the BIOS.
The further technical scheme of the invention is as follows: the step B3 is followed by the step B4: the BIOS suspends the system and displays an administrator confirmation interface.
The further technical scheme of the invention is as follows: and C, transmitting the mainboard configuration information to the BMC through an IPMI interface. Ipmi (intelligent Platform Management interface) is an abbreviation of an intelligent Platform Management interface, which is an open standard hardware Management interface specification defining a specific method for communication of an embedded Management subsystem. IPMI information is communicated via the baseboard management controller BMC (located on IPMI compliant hardware components). Using low-level hardware intelligence management without operating system management, a user may monitor the physical health characteristics of the server, such as temperature, voltage, fan operating status, power status, etc., using IPMI. And more importantly, IPMI is an open free standard, which the user does not have to pay additional fees for using. There are two main advantages: first, this configuration allows out-of-band server management; second, the operating system does not have to be burdened with the task of transferring system state data.
The invention has the beneficial effects that: the method realizes the detection of the hardware change of the system in the shutdown state, and can accurately record the platform configuration information on the platform body in time. After the hardware information changes, the BIOS can flexibly and variously set an operation path according to requirements, and can be set to be no-operation, or display warning information to continue to operate, or suspend the system to continue to operate after the administrator confirms the safety. The BMC stores information and enters the EEPROM, the information can still be stored and does not disappear after power failure, a BMC display interface provides a unified information platform for research personnel, testing personnel and clients, communication efficiency is improved, differential display is configured twice, and hardware change points of the clients can be reminded.
Drawings
Fig. 1 is a configuration circuit required in the alarm method for hardware configuration change according to the embodiment of the present invention.
Fig. 2 is a flowchart of step B and step C in the method for alarming hardware configuration change according to the embodiment of the present invention.
Fig. 3 is a flowchart of step D in the method for alarming hardware configuration change according to the embodiment of the present invention.
Detailed Description
An example is shown in fig. 1.2.3.
In order to realize the scheme, the hardware module, the BIOS module and the BMC module are required to be matched together for completion, after the hardware module detects that the platform hardware changes, the BIOS module is informed in an interruption mode, the BIOS module acquires current system configuration information and transmits the current configuration information to the BMC module through the IPMI interface, and the BMC module stores the system configuration information into the EEPROM and displays the system configuration information on the BMC interface for a user to check. The hardware module mainly refers to a configuration circuit arranged on a mainboard. It should be noted that the setting method of the configuration circuit is not exclusive, and all circuits capable of implementing the idea of the method are within the protection scope of the present invention.
Fig. 1 is a configuration circuit required in the alarm method for hardware configuration change according to the embodiment of the present invention. As can be seen from the figure, in the configuration circuit in this embodiment, all CPU sockets and on-bit signals of PCIE expansion card slots are connected, and are connected to a 3.3V RTC (real time clock) power supply and a 3.3V Sus (standby) power supply through an R1 resistor, so as to perform pull-up setting. The advantage of connecting RTC power and standby power simultaneously is that when the system does not break off AC power, is supplied power for the circuit by AC power, and when AC breaks off, is supplied power for the power by RTC power, can save power for the RTC battery like this. Again, R2 resistor is connected to ground, R2 is much larger than R1, so the bit signal defaults to high when there is no CPU or PCIE device. The bit signals are all connected to monostable schmitt circuits and the processed output signal is connected to the intra # signal of the PCH. When a CPU or PCIE device is placed in a slot, an on-site signal is changed from a high level to a low level; when the CPU or the PCIE equipment is removed, the bit signal is changed from low level to high level. The monostable Schmitt circuit has the function that when all bit signal inputs are high level or low level, the monostable Schmitt circuit outputs high level; when a certain bit signal changes from high level to low level or from low level to high level, it temporarily outputs a low level and then returns to high level. INTRUDER # is powered by RTC power, and when the input goes low, the status bit INTRD _ DET in the PCH register is set for use by BIOS.
Fig. 2 is a flowchart of step B and step C in the method for alarming hardware configuration change according to the embodiment of the present invention.
After the BIOS program runs, firstly setting INTRD _ SEL in the register TCO2_ CNT to generate SMI interrupt when the state bit INTRD _ DET is set to 1, then the BIOS program will detect whether the state bit INTRD _ DET is set, if INTRD _ DET is set to 0, it indicates that the system platform has no change of CPU and PCIE devices, and the BIOS continues to perform other operations; if INTRD _ DET is set to 1, the system platform is indicated to have the operation of CPU and PCIE equipment change, an SMI interrupt program is triggered, in the interrupt program, BIOS reads CPU information, DIMM information, PCIE equipment information and hard disk information, then all the information is transmitted to a BMC module through an IPMI interface, after the transmission is completed, the BIOS can select no operation, can also select to display hardware change warning information on a display, can also select to pause the system, the execution is continued after the administrator confirms the safety, and finally the BIOS exits the SMI program and returns other operations.
Fig. 3 is a flowchart of step D in the method for alarming hardware configuration change according to the embodiment of the present invention.
The BMC continuously polls whether a BIOS sends a data receiving command, if the BIOS does not receive the data receiving command in the starting process and the BMC is not restarted, the BMC does not perform any operation, and if the BMC is restarted, the BMC reads the latest two groups of platform configuration information from the EEPROM and displays the latest two groups of platform configuration information for reference comparison; if a command of transmitting and receiving data by the BIOS is received in the starting process, the BMC stores the received platform configuration information into the EEPROM, then reads the EEPROM and displays the latest two groups of platform configuration information. The place where the latest configuration changes can be marked specially when the block is displayed, so that the user can conveniently look up the block in time.
The method detects the hardware change of the system in the shutdown state, including two shutdown states of power (S5) and no power (G3). After the hardware configuration changes, the hardware triggers interruption, the BIOS SMI program acquires the platform configuration information, the BMC completes the storage and differential display of the configuration information, and the three complete the timely and accurate recording of the platform configuration information on the platform body. After the hardware information changes, the BIOS can flexibly and variously set an operation path according to requirements, and can be set to be no-operation, or display warning information to continue to operate, or suspend the system to continue to operate after the administrator confirms the safety. The BMC stores information and enters the EEPROM, the information can still be stored and does not disappear after power failure, a BMC display interface provides a unified information platform for research personnel, testing personnel and clients, communication efficiency is improved, differential display is configured twice, and hardware change points of the clients can be reminded.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.
Claims (7)
1. A hardware configuration change alarm method is characterized by comprising the following steps:
A. a detection step: the detection step is that the configuration circuit detects whether the configuration of the mainboard is changed, if not, the operation is not carried out; if yes, sending an electric signal to the BIOS; the configuration circuit is arranged on the mainboard and converts the change of the mainboard configuration into an electric signal;
B. a reading step: the reading step is that the BIOS reads the configuration information of the mainboard after receiving the electric signal transmitted by the configuration circuit;
C. a storage step: the storage step is that the BIOS transmits the read mainboard configuration information to the BMC and stores the mainboard configuration information into the EEPROM of the BMC;
D. a comparison step: the comparison step is that the BMC reads the configuration information of the two groups of the latest mainboards in the EEPROM and identifies the changed configuration information;
wherein,
the configuration circuit sends an electric signal to the BIOS after detecting that the level of in-place signals of the CPU socket and the PCIE slot changes;
the configuration circuit further comprises a standby power supply, and the standby power supply is connected with the CPU socket and the PCIE slot through a resistor R1; the CPU socket and the PCIE slot are grounded through a resistor R2; the resistance value of the R2 is more than 5 times of the resistance value of the R1;
the configuration circuit further comprises a real-time clock power supply, and the real-time clock power supply is connected with the CPU socket and the PCIE slot through a resistor R1.
2. The hardware configuration change warning method according to claim 1, wherein: the configuration circuit comprises a monostable Schmitt circuit connected with the CPU socket and the PCIE slot.
3. The hardware configuration change warning method according to claim 2, wherein: the monostable Schmitt circuit is connected with the PCH register.
4. The hardware configuration change warning method according to claim 3, wherein: the step A comprises the following sub-steps:
A1. maintaining the level of the monostable schmitt circuit high;
A2. the level of the in-place signals of the CPU socket and the PCIE slot changes to invert the monostable Schmitt circuit to temporarily output a low level, and then the high level is recovered;
A3. the status bit INTRD _ DET in the PCH register is set to 1 state upon receipt of a low level from the monostable schmitt circuit.
5. The hardware configuration change warning method according to claim 4, wherein: the step B comprises the following sub-steps:
B1. the BIOS detects a status bit INTRD _ DET in the PCH register;
B2. if the status bit INTRD _ DET in the PCH register is 0, no operation is performed, and if the status bit INTRD _ DET in the PCH register is 1, the process proceeds to step B3;
B3. and the BIOS enters an SMI interrupt program, and the SMI interrupt program is used for reading the mainboard configuration information by the BIOS.
6. The hardware configuration change warning method according to claim 5, wherein: the step B3 is followed by the step B4: the BIOS suspends the system and displays an administrator confirmation interface.
7. The hardware configuration change warning method according to claim 6, wherein: and C, transmitting the mainboard configuration information to the BMC through an IPMI interface.
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| CN109086081B (en) * | 2018-06-29 | 2020-11-03 | 深圳市同泰怡信息技术有限公司 | Method, system and medium for instantly prompting in-place change of SATA (Serial advanced technology attachment) and NVMe (network video recorder) equipment |
| CN111858428B (en) * | 2020-06-24 | 2022-03-22 | 山东云海国创云计算装备产业创新中心有限公司 | Server and communication management circuit of BIOS thereof |
| CN111782287B (en) * | 2020-06-30 | 2023-03-21 | 联想(北京)有限公司 | Information prompting method and device and electronic equipment |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080126852A1 (en) * | 2006-08-14 | 2008-05-29 | Brandyberry Mark A | Handling Fatal Computer Hardware Errors |
| US20130339938A1 (en) * | 2012-06-15 | 2013-12-19 | Hon Hai Precision Industry Co., Ltd. | System and method for updating firmware |
| CN104035845A (en) * | 2013-11-28 | 2014-09-10 | 曙光信息产业(北京)有限公司 | Detection system and method for memory bank installation failure |
| CN104899055A (en) * | 2015-05-06 | 2015-09-09 | 深圳市国鑫恒宇科技有限公司 | BIOS control based ME updating system and updating method thereof |
| CN105389525A (en) * | 2015-12-11 | 2016-03-09 | 曙光信息产业股份有限公司 | Management method and system for blade server |
-
2016
- 2016-05-13 CN CN201610322400.3A patent/CN105975382B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080126852A1 (en) * | 2006-08-14 | 2008-05-29 | Brandyberry Mark A | Handling Fatal Computer Hardware Errors |
| US20130339938A1 (en) * | 2012-06-15 | 2013-12-19 | Hon Hai Precision Industry Co., Ltd. | System and method for updating firmware |
| CN104035845A (en) * | 2013-11-28 | 2014-09-10 | 曙光信息产业(北京)有限公司 | Detection system and method for memory bank installation failure |
| CN104899055A (en) * | 2015-05-06 | 2015-09-09 | 深圳市国鑫恒宇科技有限公司 | BIOS control based ME updating system and updating method thereof |
| CN105389525A (en) * | 2015-12-11 | 2016-03-09 | 曙光信息产业股份有限公司 | Management method and system for blade server |
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