CN111834300A - 半导体器件及其形成方法 - Google Patents

半导体器件及其形成方法 Download PDF

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Publication number
CN111834300A
CN111834300A CN201910314464.2A CN201910314464A CN111834300A CN 111834300 A CN111834300 A CN 111834300A CN 201910314464 A CN201910314464 A CN 201910314464A CN 111834300 A CN111834300 A CN 111834300A
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layer
sacrificial layer
region
liner
substrate
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周飞
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to CN201910314464.2A priority Critical patent/CN111834300A/zh
Priority to US16/851,645 priority patent/US20200335402A1/en
Publication of CN111834300A publication Critical patent/CN111834300A/zh
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Abstract

本发明提供半导体器件及其形成方法，包括提供衬底，所述衬底包括第一区和第二区，所述衬底上形成有第一牺牲层、位于所述第一牺牲层上的第一衬层、位于所述第一衬层上的第二牺牲层和位于所述第二牺牲层上的第二衬层；依次去除所述第二区的所述第二衬层、所述第二牺牲层、所述第一衬层、所述第一牺牲层以及部分厚度的所述衬底；在所述第二区的衬底上形成第三牺牲层、位于所述第三牺牲层上的第三衬层、位于所述第三衬层上的第四牺牲层和位于所述第四牺牲层上的第四衬层；所述第三牺牲层的厚度大于所述第一牺牲层的厚度；所述第四牺牲层的厚度大于所述第二牺牲层的厚度；本发明便于形成全包围栅结构时材料层的填充，提高半导体器件的性能与稳定性。

Description

半导体器件及其形成方法
技术领域
本发明涉及半导体制造技术领域，尤其涉及一种半导体器件及其形成方法。
背景技术
随着半导体制造技术的飞速发展，半导体器件朝着更高的元件密度，以及更高的集成度的方向发展。器件作为最基本的半导体器件，目前正被广泛应用，传统的平面器件对沟道电流的控制能力变弱，产生短沟道效应而导致漏电流，最终影响半导体器件的电学性能。
为了克服器件的短沟道效应，抑制漏电流，现有技术提出了鳍式场效应晶体管(Fin FET)，鳍式场效应晶体管是一种常见的多栅器件，鳍式场效应晶体管的结构包括：位于半导体衬底表面的鳍部和隔离层，所述隔离层覆盖部分所述鳍部的侧壁，且隔离层表面低于鳍部顶部；位于隔离层表面，以及鳍部的顶部和侧壁表面的栅极结构；位于所述栅极结构两侧的鳍部内的源区和漏区。
随着对器件性能不断提出的更高要求，催生了四面控制的全包围栅结构(Gate-all-around)。具有全包围栅极(Gate-all-around)结构的半导体器件拥有有效地限制短沟道效应(Short channel effect)的特殊性能，正是业界在遵循摩尔定律不断缩小器件尺寸的革新中所极其渴望的。
然而，现有技术形成的全包围栅极结构半导体器件的性能较差。
发明内容
本发明解决的问题是提供一种半导体器件及其形成方法，提高半导体器件的性能。
为解决上述问题，本发明提供半导体器件的形成方法，包括：提供衬底，所述衬底包括第一区和第二区，所述衬底上形成有第一牺牲层、位于所述第一牺牲层上的第一衬层、位于所述第一衬层上的第二牺牲层和位于所述第二牺牲层上的第二衬层；依次去除所述第二区的所述第二衬层、所述第二牺牲层、所述第一衬层、所述第一牺牲层以及部分厚度的所述衬底；在所述第二区的衬底上形成第三牺牲层、位于所述第三牺牲层上的第三衬层、位于所述第三衬层上的第四牺牲层和位于所述第四牺牲层上的第四衬层；所述第三牺牲层的厚度大于所述第一牺牲层的厚度；所述第四牺牲层的厚度大于所述第二牺牲层的厚度；刻蚀所述第一区的所述第二衬层、所述第二牺牲层、所述第一衬层、所述第一牺牲层以及部分厚度的衬底，形成第一区鳍部；同时刻蚀所述第二区的所述第四衬层、所述第四牺牲层、所述第三衬层、所述第三牺牲层以及部分厚度的衬底，形成第二区鳍部；去除所述第一区鳍部上的所述第一牺牲层，在所述第一区鳍部上形成第一沟槽；同时去除所述第一区鳍部上的所述第二牺牲层，在所述第一区鳍部上形成第二沟槽；同时去除所述第二区鳍部上的所述第三牺牲层，在所述第二区鳍部上形成第三沟槽；同时去除所述第二区鳍部上的所述第四牺牲层，在所述第二区鳍部上形成第四沟槽。
可选的，所述第一区为NMOS区，所述第二区为PMOS区；或者所述第一区为PMOS区，所述第二区为NMOS区。
可选的，采用外延生长方式在所述衬底上形成有第一牺牲层、位于所述第一牺牲层上的第一衬层、位移所述第一衬层上的第二牺牲层和位于所述第二牺牲层上的第二衬层。
可选的，采用外延生长方式在所述第二区的衬底上形成第三牺牲层、位于第三牺牲层上的所述第三衬层、位于第三衬层上的第四牺牲层和位于第四牺牲层上的第四衬层。
可选的，所述第一衬层的材料包括硅或锗或锗硅或砷化镓中的一种或者多种。
可选的，所述第二衬层的材料包括硅或锗或锗硅或砷化镓中的一种或者多种。
可选的，所述第三衬层的材料包括硅或锗或锗硅或砷化镓中的一种或者多种。
可选的，所述第四衬层的材料包括硅或锗或锗硅或砷化镓中的一种或者多种。
可选的，所述第一牺牲层的材料包括硅或锗硅或碳化硅或砷化镓或砷化铟镓中的一种或者多种。
可选的，所述第二牺牲层的材料包括硅或锗硅或碳化硅或砷化镓或砷化铟镓中的一种或者多种。
可选的，所述第三牺牲层的材料包括硅或锗硅或碳化硅或砷化镓或砷化铟镓中的一种或者多种。
可选的，所述第四牺牲层的材料包括硅或锗硅或碳化硅或砷化镓或砷化铟镓中的一种或者多种。
可选的，在形成所述第一区鳍部和所述第二区鳍部之后，去除所述第一区鳍部上的所述第一牺牲层之前还包括，在所述第一区的所述衬底上形成第一氧化层，同时在所述第二区的所述衬底上形成第二氧化层，所述第一氧化层的顶部与所述第一牺牲层的底部齐平；所述第二氧化层的顶部与所述第三牺牲层的底部齐平。
一种半导体器件，包括：衬底，所述衬底包括第一区和第二区；第一衬层，位于所述第一区的衬底上；第二衬层，位于所述第一衬层上；第一沟槽，位于所述第一区的衬底与所述第一衬层之间；第二沟槽，位于所述第一衬层与所述第二衬层之间；第三衬层，位于所述第二区的衬底上；第四衬层，位于所述第三衬层上；第三沟槽，位于所述第二区的衬底与所述第三衬层之间；第四沟槽，位于所述第三衬层与所述第四衬层之间。
与现有技术相比，本发明的技术方案具有以下优点：
由于所述第三牺牲层的厚度大于所述第一牺牲层的厚度和所述第四牺牲层的厚度大于所述第二牺牲层的厚度，所以去除所述第三牺牲层后形成的所述第三沟槽要比去除所述第一牺牲层后形成的所述第一沟槽要大；同理所以去除所述第四牺牲层后形成的所述第四沟槽要比去除所述第二牺牲层后形成的所述第二沟槽要大；这样在所述第一沟槽内、所述第二沟槽内、所述第三沟槽内、所述第四沟槽内填充材料层时；一方面便于在所述第一区和所述第二区上形成不同厚度的材料层；另一方面，当需要填充厚度较厚的材料层时，将较厚的材料层填充到沟槽较大的所述第三沟槽和所述第四沟槽，由于所述第三沟槽和所述第四沟槽能够提供足够大的空间，所述第三沟槽和所述第四沟槽内部气压较小，在填充材料层时由于内部气压对材料层的作用力小，保证材料层填充所述第三沟槽和所述第四沟槽的时候不会依附在所述第三沟槽和所述第四沟槽的边缘上而引起边缘的问题，同时不会在材料层的内部产生气孔保证填充的材料层的质量，从而便于提高半导体器件的性能。
附图说明
图1至图3是一种图形结构形成过程的结构示意图；
图4至图9是本发明第一实施例中半导体器件形成过程的结构示意图；
图10至图11是本发明第二实施例中半导体器件形成过程的结构示意图。
具体实施方式
目前半导体器件的性能稳定性差，具体参考图1至图3。
图1至图3是一种半导体器件形成过程的结构示意图。
参考图1，提供衬底1，所述衬底1，所述衬底包括第一区110和第二区120，所述衬底1上形成有第一牺牲层101、位于所述第一牺牲层101上的第一衬层102、位于所述第一衬层102上的第二牺牲层103以及位于所述第二牺牲层103上的第二衬层104。
参考图2，依次刻蚀所述第二衬层104、第二牺牲层103、第一衬层102以及第一牺牲层101，在所述第一区110上形成第一区鳍部111、在所述第二区120上形成第二区鳍部121。
参考图3，分别去除所述第一区鳍部111上的所述第一牺牲层101和所述第二牺牲层103，在所述第一区110的所述衬底1与所述第一衬层102之间形成第一沟槽112、在所述第一区110的所述第一衬层102与所述第二衬层104之间形成第二沟槽113；
分别去除所述第二区鳍部121上的所述第一牺牲层101和所述第二牺牲层103，在所述第二区120的所述衬底1与所述第一衬层102之间形成第三沟槽122、在所述第二区120的所述第一衬层102与所述第二衬层104之间形成第四沟槽123。
发明人发现，利用上述方法，形成的所述第一沟槽112、所述第二沟槽113、所述第三沟槽122和所述第四沟槽123的大小相同，向所述第一沟槽112、所述第二沟槽113、所述第三沟槽122和所述第四沟槽123填充材料层时，一方面不便于在所述第一区110和所述第二区120上形成不同厚度的材料层；另一方面，当需要在所述第一区110或者所述第二区120的沟槽内填充厚度较厚的材料层时，由于所述沟槽提供的空间较小，在材料层填充的时候，容易出现材料层只填充在沟槽的边缘上的现象，而引起桥接的问题从而降低了半导体器件的使用性能。
发明人研究发现，在第一区和第二区上形成不同厚度的牺牲层，利用牺牲层先占好空间，在后续去除牺牲层的时候，便能形成不同大小的沟槽，这样一方面利用不同大小的沟槽便于在第一区和第二区上形成不同厚度的材料层；另一方面，利用不同大小的沟槽，在填充材料层的时候，将需要形成较厚的材料层填充到较大的沟槽内，由于沟槽内的气压较小，材料层能够充分的填充到沟槽内而不会仅仅附着在沟槽的边缘上而引起桥接问题，降低半导体器件的使用性能。
为使本发明的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细地说明。
第一实施例
首先参考图4，提供衬底200，所述衬底200包括第一区210和第二区220。
本实施例中，所述衬底200的材料为单晶硅；其他实施例中，所述衬底200可以是多晶硅或非晶硅；所述衬底200也可以是硅、锗、锗硅、砷化镓等半导体材料。
本实施例中，所述第一区210为NMOS区，所述第二区220为PMOS区。
其他实施例中，所述第一区为PMOS区，所述第二区为NMOS区。
参考图5，在所述衬底200上依次形成第一牺牲层201、第一衬层202、第二牺牲层203和第二衬层204。
本实施例中，所述第一牺牲层201的材料为锗硅(SiGe)；其他实施例中，所述第一牺牲层201的材料还可以为硅或锗或砷化镓中的一种或者多种。
本实施例中，所述第一衬层202的材料为硅(Si)；其他实施例中，所述第一衬层202的材料还可为锗硅或碳化硅或砷化镓或砷化铟镓中的一种或者多种。
本实施例中，所述第二牺牲层203的材料为锗硅(SiGe)；其他实施例中，所述第二牺牲层203的材料还可以为硅或锗或砷化镓中的一种或者多种。
本实施例中，所述第二衬层204的材料为硅(Si)；其他实施例中，所述第二衬层204的材料还可为锗硅或碳化硅或砷化镓或砷化铟镓中的一种或者多种。
本实施例中，所述第一衬层202与所述第二衬层204的材料一样；其他实施例中，所述第一衬层202与所述第二衬层204的材料还可不一样。
本实施例中，所述第一牺牲层201与所述第二牺牲层203的材料一样；其他实施例中，所述第一牺牲层201与所述第二牺牲层203的材料还可不一样。
本实施例中，所述第一衬层202的厚度与所述第二衬层204的厚度相同；其他实施例中，所述第一衬层202的厚度与所述第二衬层204的厚度还可以不相同。
本实施例中，所述第一牺牲层201和所述第二牺牲层203的厚度相同；其他实施例中，所述第一牺牲层201和所述第二牺牲层203的厚度还可不相同。
本实施例中，采用外延生长的方式形成第一牺牲层201、第一衬层202、第二牺牲层203以及第二衬层204。
本实施例中，形成所述第一牺牲层201和所述第二牺牲层203的工艺参数包括：采用的气体包括氢气(H2)、氯化氢(HCl)气体、DCS气体、GeH4气体以及B2H6气体，其中所述氢气(H2)的气体流量为10～3000sccm；所述氯化氢(HCl)气体的气体流量为10～200sccm；所述DCS气体的气体流量为20～2000sccm；所述GeH4的气体流量为10～500sccm；所述B2H6气体的气体流量为5～600sccm；温度范围为600℃～850℃，压强范围为8～300毫托，时间为10min～1h。
本实施例中，形成所述第一衬层202和所述第二衬层204的工艺参数包括采用的气体包括氢气(H2)、氯化氢(HCl)气体、DCS气体、SiH4气体以及B2H6气体；其中，所述氢气(H2)的气体流量为10～3000sccm；所述氯化氢(HCl)气体的气体流量为10～250sccm；所述DCS气体的气体流量为20～2500sccm；所述SiH4气体的气体流量为10～700sccm；所述B2H6气体的气体流量为5～400sccm；压强范围8～～300毫托；温度为600℃～850℃之间。
本实施例中，采用外延生长的方式形成所述牺牲层以及所述衬层的原因是，外延生长方式可以获得电导率高的P型和N型材料，获得的牺牲层和衬层的完整性好，利于形成质量好的半导体器件。
其他实施例中，还可以采用离子掺杂工艺或者化学气相沉积的方法在所述衬底200上形成第一牺牲层201、位于所述第一牺牲层201上的第一衬层202、位于所述第一衬层202上的第二牺牲层203和位于所述第二牺牲层203上的第二衬层204。
参考图6，去除第二区220的第二衬层204、第二牺牲层203、第一衬层202、第一牺牲层201以及部分厚度的衬底200。
本实施例中，去除所述第二牺牲层203和所述第一牺牲层201工艺为湿法刻蚀工艺。所述湿法刻蚀溶液对硅和硅锗有很好的选择比，能够保证在去除锗硅的同时，硅的形貌不受影响。本实施例中所述湿法刻蚀的参数包括：刻蚀液为HCl气体的溶液，温度为25摄氏度～300摄氏度，所述HCl气体的溶液的体积百分比为20％～90％。
本实施例中，去除所述第二衬层204、所述第一衬层202以及部分厚度的所述衬底200工艺为湿法刻蚀工艺。所述湿法刻蚀的刻蚀液对硅和锗硅有很好的选择比，能够保证在去除硅的同时，锗硅的形貌不受影响。所述湿法刻蚀工艺的参数包括：刻蚀液为四甲基氢氧化铵溶液，温度为20摄氏度～80摄氏度，所述四甲基氢氧化铵溶液的体积百分比为10％～80％。
参考图7，在所述第二区220的衬底200上形成第三牺牲层205、位于所述第三牺牲层205上的第三衬层206、位于所述第三衬层206上的第四牺牲层207和位于所述第四牺牲层207上的第四衬层208。
本实施例中，所述第三牺牲层205的材料为锗硅(SiGe)；其他实施例中，所述第三牺牲层205的材料还可以为硅或锗或砷化镓中的一种或者多种。
本实施例中，所述第三衬层206的材料为硅(Si)；其他实施例中，所述第三衬层206的材料还可为锗硅或者碳化硅或者砷化镓或者砷化铟镓中的一种或者多种。
本实施例中，所述第四牺牲层207的材料为锗硅(SiGe)；其他实施例中，所述第四牺牲层207的材料还可以为硅或锗或砷化镓中的一种或者多种。
本实施例中，所述第四衬层208的材料为硅(Si)；其他实施例中，所述第四衬层208的材料还可为锗硅或者碳化硅或者砷化镓或者砷化铟镓中的一种或者多种。
本实施例中，所述第三牺牲层205和所述第四牺牲层207的材料相同；其他实施例中，所述第三牺牲层205和所述第四牺牲层207的材料还可以不同。
本实施例中，所述第三衬层206和所述第四衬层208的材料相同；其他实施例中，所述第三衬层206和所述第四衬层208的材料还可以不同。
本实施例中，采用外延生长方式在所述第二区220的衬底200上形成第三牺牲层205、位于第三牺牲层205上的第三衬层206、位于第三衬层206上的第四牺牲层207和位于第四牺牲层207上的第四衬层208。
其他实施例中，还可采用化学气相沉积或者原子层沉积或者离子掺杂等方式形成所述第三牺牲层205、所述第三衬层206、所述第四牺牲层207和所述第四衬层208。
本实施例中，采用与形成所述第一衬层202和所述第二衬层204相同的工艺参数形成所述第三衬层206和所述第四衬层208；其他实施例中，还可采用不同的工艺参数形成所述第三衬层206和所述第四衬层208。
本实施例中，形成所述第三牺牲层205和所述第四牺牲层207的工艺参数包括：采用的气体包括氢气(H2)、氯化氢(HCl)气体、DCS气体、GeH4气体以及B2H6气体，其中所述氢气(H2)的气体流量为10～3000sccm；所述氯化氢(HCl)气体的气体流量为10～200sccm；所述DCS气体的气体流量为20～2000sccm；所述GeH4的气体流量为10～500sccm；所述B2H6气体的气体流量为5～600sccm；温度范围为600℃～850℃，压强范围为8～300毫托，时间为10min～1h。
本实施例中，所述第三牺牲层205的厚度与所述第四牺牲层207的厚度相同；其他实施例中，所述第三牺牲层205的厚度与所述第四牺牲层207的厚度可以不相同。
本实施例中，所述第三衬层206的厚度与所述第四衬层208的厚度相同；其他实施例中，所述第三衬层206的厚度与所述第四衬层208的厚度还可以不相同。
本实施例中，所述第三牺牲层205的厚度大于所述第一牺牲层201的厚度；所述第四牺牲层207的厚度大于所述第二牺牲层203的厚度。这样设置的目的是在后续去除所述牺牲层形成沟槽时，在所述第二区220能够形成较大的沟槽。
本实施例中，所述第一衬层202的厚度和所述第三衬层206的厚度相同；其他实施例中，所述第一衬层202的厚度和所述第三衬层206的厚度还可不相同。
本实施例中，所述第二衬层204的顶部表面与所述第四衬层208的顶部表面齐平；其他实施例中，述第二衬层204的顶部表面与所述第四衬层208的顶部表面还可不齐平。
本实施例中，所述第二牺牲层203的顶部表面与所述第四牺牲层207的顶部表面齐平；其他实施例中，所述第二牺牲层203的顶部表面与所述第四牺牲层207的顶部表面还可以不齐平。
参考图8，刻蚀所述第一区210的所述第二衬层204、所述第二牺牲层203、所述第一衬层202、所述第一牺牲层201以及部分厚度的衬底200，形成第一区鳍部230；同时刻蚀所述第二区220的所述第四衬层208、所述第四牺牲层207、所述第三衬层206、所述第三牺牲层205以及部分厚度的衬底200，形成第二区鳍部240。
本实施例中，采用刻蚀工艺形成所述第一区鳍部230的工艺参数包括，采用CF4气体、氢气(H2)，其中所述CF4气体的流量为10～300sccm、所述氢气(H2)的气体流量为20～500sccm，反应时间为5～～500s；
本实施例中，形成所述第二区鳍部240的工艺参数包括采用的刻蚀气氛为、氧气(O2)、CH3F气体以及氦气(He)混合气氛，所述氧气(O2)的气体流量为5～～9005sccm、所述CH3F气体的气体流量为60～8000sccm、所述氦气(He)的气体流量为60～2000sccm，反应时间为50～10000s。
参考图9，形成第一沟槽231、第二沟槽232、第三沟槽241以及第四沟槽242。
去除所述第一区鳍部230上的所述第一牺牲层201，在所述第一区鳍部230上形成第一沟槽231；
同时去除所述第一区鳍部230上的所述第二牺牲层203，在所述第一区鳍部230上形成第二沟槽232；
同时去除所述第二区鳍部240上的所述第三牺牲层205，在所述第二区鳍部240上形成第三沟槽241；
同时去除所述第二区鳍部240上的所述第四牺牲层207，在所述第二区鳍部240上形成第四沟槽242。
本实施例中，由于所述第三牺牲层205的厚度大于所述第一牺牲层201的厚度；所述第四牺牲层207的厚度大于所述第二牺牲层203的厚度，所以形成的所述第三沟槽241、所述第四沟槽242要比所述第一沟槽231、所述第二沟槽232要大。利用较厚的所述第三牺牲层205和所述第四牺牲层207先占好较大空间位置，在去除所述第一牺牲层201、第二牺牲层203、所述第三牺牲层205和所述第四牺牲层207，才能保证形成第三沟槽241和第四沟槽242的尺寸要比形成的第一沟槽231和第二沟槽232的尺寸要大，那么在第三沟槽241和第四沟槽242内就容易形成较厚的材料层，在第一沟槽231和第二沟槽232内形成较薄的材料层，能够满足不同功能区对不同厚度材料层的需求；同时由于第三沟槽241和第四沟槽242的尺寸较大，在形成较厚的材料层时，便于材料层在沟槽内均匀的填充，不会由于沟槽尺寸较小，从而导致沟槽内具有较高的气压而导致材料层只能附着在沟槽的侧壁上而引起桥接的问题。
本实施例中，去除所述第一区鳍部230上的所述第一牺牲层201、所述第一区鳍部230上的所述第二牺牲层203、去除所述第二区鳍部240上的所述第三牺牲层205以及去除所述第二区鳍部240上的所述第四牺牲层207的工艺中采用水蒸气和氯化氢(HCl气体)的混合气体，两者的体积比为20～90％，温度25～300℃。
利用上述方法形成的一种半导体器件，包括：衬底200，所述衬底200包括第一区210和第二区220；第一衬层202，位于所述第一区210的衬底200上；第二衬层204，位于所述第一衬层202上；第一沟槽231，位于所述第一区210的衬底200与所述第一衬层202之间；第二沟槽232，位于所述第一衬层202与所述第二衬层204之间；第三衬层206，位于所述第二区220的衬底200上；第四衬层208，位于所述第三衬层206上；第三沟槽241，位于所述第二区220的衬底200与所述第三衬层206之间；第四沟槽242，位于所述第三衬层206与所述第四衬层208之间。
形成第一沟槽231、第二沟槽232、第三沟槽241以及第四沟槽242后，后续所述形成包围所述第一区鳍部230上所述第一衬层202的第一材料层；同时形成包围所述第一区鳍部230上所述第二衬层204的第二材料层；同时形成包围所述第二区鳍部240上所述第三衬层206的第三材料层；同时形成包围所述第二区鳍部240上所述第四衬层208的第四材料层。
第一材料层、第二材料层、第三材料层以及第四材料层的形成方法以及材料相同；以第三材料层的形成为例，其形成步骤包括，在所述第三沟槽241和所述第四沟槽242内形成包围所述第三衬层206的界面层(IL)；形成所述界面层(IL)之后，在所述界面层(IL)上形成高k金属层；形成高k金属层后，在所述形成高k金属层上形成功函层。
第二实施例
第二实施例中从提供衬底200到形成所述第一区鳍部230和所述第二区鳍部240的过程与第一实施例相同，参考图4至图8。
第二实施例与第一实施例的差别仅在于，在形成所述第一区鳍部230和所述第二区鳍部240之后，去除所述第一区鳍部上的所述第一牺牲层201之前还包括，在所述衬底上形成氧化层，具体参考图10。
第二实施例中，形成氧化层之后，去除所述第一牺牲层201、所述第二牺牲层203、所述第三牺牲层205以及所述第四牺牲层207的步骤与第一实施例中相同。
参考图10，形成第一区鳍部230和所述第二区鳍部240后，在所述第一区210的衬底200上形成第一氧化层250，同时在所述第二区220的衬底200上形成第二氧化层260。
本实施例中，在所述衬底200上形成第一氧化层250和第二氧化层260；其他实施例中，所述衬底200上还可不形成第一氧化层250和第二氧化层260。
本实施例中，所述第一氧化层250的顶部表面与所述第一牺牲层201的底部表面齐平。
本实施例中，所述第二氧化层260的顶部表面与所述第三牺牲层205的底部表面齐平。
本实施例中，所述第一氧化层250与所述第二氧化层260存在高度差，目的是保护好所述第一氧化层250与所述第二氧化层260所述包围和覆盖的衬底，防止在后续的工艺中对衬底表面产生损伤，从而影响半导体器件的性能。
本实施例中，所述第一氧化层250与所述第二氧化层260的材料相同，都采用氧化硅材料；其他实施例中，还可为氮氧化硅或者氮化硅或者碳氧化硅或者碳氮化硅或碳氮氧化硅。
本实施例中，所述第一氧化层250与所述第二氧化层260用于后的刻蚀过程中，作为刻蚀停止层，保护所述第一氧化层250与所述第二氧化层260所包围和覆盖的衬底表面的完整性，保证形成半导体器件的质量。
参考图11，形成所述第一氧化层250与所述第二氧化层260之后，再去除所述第一牺牲层201、所述第二牺牲层203、所述第三牺牲层205以及所述第四牺牲层207形成第一沟槽231、第二沟槽232、第三沟槽241以及第四沟槽242。
利用上述方法形成的一种半导体器件，包括：衬底200，所述衬底200包括第一区210和第二区220；第一氧化层250，位于所述第一区210的衬底200上；第一衬层202，位于所述第一氧化层250上；第二衬层204，位于所述第一衬层202上；第一沟槽231，位于所述第一区的所述衬底200与所述第一衬层202之间；第二沟槽232，位于所述第一衬层202与所述第二衬层204之间；第二氧化层260，位于所述第二区220的衬底200上；第三衬层206，位于所述第二氧化层260上；第四衬层208，位于所述第三衬层206上；第三沟槽241，位于所述第二区的所述衬底200与所述第三衬层206之间；第四沟槽242，位于所述第三衬层206与所述第四衬层208之间。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (14)

1.一种半导体器件的形成方法，其特征在于，包括：
提供衬底，所述衬底包括第一区和第二区，所述衬底上形成有第一牺牲层、位于所述第一牺牲层上的第一衬层、位于所述第一衬层上的第二牺牲层和位于所述第二牺牲层上的第二衬层；
依次去除所述第二区的所述第二衬层、所述第二牺牲层、所述第一衬层、所述第一牺牲层以及部分厚度的所述衬底；
在所述第二区的衬底上形成第三牺牲层、位于所述第三牺牲层上的第三衬层、位于所述第三衬层上的第四牺牲层和位于所述第四牺牲层上的第四衬层；
所述第三牺牲层的厚度大于所述第一牺牲层的厚度；
所述第四牺牲层的厚度大于所述第二牺牲层的厚度；
刻蚀所述第一区的所述第二衬层、所述第二牺牲层、所述第一衬层、所述第一牺牲层以及部分厚度的衬底，形成第一区鳍部；
同时刻蚀所述第二区的所述第四衬层、所述第四牺牲层、所述第三衬层、所述第三牺牲层以及部分厚度的衬底，形成第二区鳍部；
去除所述第一区鳍部上的所述第一牺牲层，在所述第一区鳍部上形成第一沟槽；
同时去除所述第一区鳍部上的所述第二牺牲层，在所述第一区鳍部上形成第二沟槽；
同时去除所述第二区鳍部上的所述第三牺牲层，在所述第二区鳍部上形成第三沟槽；
同时去除所述第二区鳍部上的所述第四牺牲层，在所述第二区鳍部上形成第四沟槽。
2.如权利要求1所述半导体器件的形成方法，其特征在于，所述第一区为NMOS区，所述第二区为PMOS区；或者所述第一区为PMOS区，所述第二区为NMOS区。
3.如权利要求1所述半导体器件的形成方法，其特征在于，采用外延生长方式在所述衬底上形成有第一牺牲层、所述第一衬层、所述第二牺牲层和所述第二衬层。
4.如权利要求1所述半导体器件的形成方法，其特征在于，采用外延生长方式在所述第二区的衬底上形成所述第三牺牲层、所述第三衬层、所述第四牺牲层和所述第四衬层。
5.如权利要求1所述半导体器件的形成方法，其特征在于，所述第一衬层的材料包括硅或锗或锗硅或砷化镓中的一种或者多种。
6.如权利要求1所述半导体器件的形成方法，其特征在于，所述第二衬层的材料包括硅或锗或锗硅或砷化镓中的一种或者多种。
7.如权利要求1所述半导体器件的形成方法，其特征在于，所述第三衬层的材料包括硅或锗或锗硅或砷化镓中的一种或者多种。
8.如权利要求1所述半导体器件的形成方法，其特征在于，所述第四衬层的材料包括硅或锗或锗硅或砷化镓中的一种或者多种。
9.如权利要求1所述半导体器件的形成方法，其特征在于，所述第一牺牲层的材料包括硅或锗硅或碳化硅或砷化镓或砷化铟镓中的一种或者多种。
10.如权利要求1所述半导体器件的形成方法，其特征在于，所述第二牺牲层的材料包括硅或锗硅或碳化硅或砷化镓或者砷化铟镓中的一种或者多种。
11.如权利要求1所述半导体器件的形成方法，其特征在于，所述第三牺牲层的材料包括硅或锗硅或碳化硅或砷化镓或砷化铟镓中的一种或者多种。
12.如权利要求1所述半导体器件的形成方法，其特征在于，所述第四牺牲层的材料包括硅或锗硅或碳化硅或砷化镓或砷化铟镓中的一种或者多种。
13.如权利要求1所述半导体器件的形成方法，其特征在于，在形成所述第一区鳍部和所述第二区鳍部之后，去除所述第一区鳍部上的所述第一牺牲层之前，还包括，在所述第一区的所述衬底上形成第一氧化层，同时在所述第二区的所述衬底上形成第二氧化层，所述第一氧化层的顶部与所述第一牺牲层的底部齐平；所述第二氧化层的顶部与所述第三牺牲层的底部齐平。
14.一种采用权利要求1至13任一项方法所形成的半导体器件，其特征在于，包括：
衬底，所述衬底包括第一区和第二区；
第一衬层，位于所述第一区的衬底上；
第二衬层，位于所述第一衬层上；
第一沟槽，位于所述第一区的衬底与所述第一衬层之间；
第二沟槽，位于所述第一衬层与所述第二衬层之间；
第三衬层，位于所述第二区的衬底上；
第四衬层，位于所述第三衬层上；
第三沟槽，位于所述第二区的衬底与所述第三衬层之间；
第四沟槽，位于所述第三衬层与所述第四衬层之间。
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