CN111816650A - SCR electrostatic protection structure and forming method thereof - Google Patents
SCR electrostatic protection structure and forming method thereof Download PDFInfo
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- CN111816650A CN111816650A CN201910295445.XA CN201910295445A CN111816650A CN 111816650 A CN111816650 A CN 111816650A CN 201910295445 A CN201910295445 A CN 201910295445A CN 111816650 A CN111816650 A CN 111816650A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
- H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
Abstract
An SCR electrostatic protection structure and a forming method thereof are disclosed, the structure comprises: an N-type well in the semiconductor substrate; a plurality of discrete first-to-Q-th stage main cells located in the N-type well; the kth stage main unit includes: an N-type doped region located at the top of the kth unit region of the N-type well; the first P-type doped region is positioned at the top part of the kth unit region of the N-type trap, is positioned at the side part of the N-type doped region and is separated from the N-type doped region; the second P-type doped region is positioned in the kth unit region of the N-type trap, positioned at the bottom of the first P-type doped region and adjacent to the first P-type doped region, and also extends to the bottom of the N-type doped region and adjacent to the N-type doped region; the N-type doped region in the first-level main unit is electrically connected with the first P-type doped region in the Q-th-level main unit, and the first P-type doped region in the i-1-th-level main unit is electrically connected with the N-type doped region in the i-th-level main unit. The performance of the structure is improved.
Description
Technical Field
The invention relates to the field of electrostatic protection, in particular to an SCR electrostatic protection structure and a forming method thereof.
Background
In the manufacture and application of integrated circuit chips, with the continuous improvement of super-large-scale integrated circuit process technology, the current CMOS integrated circuit manufacturing technology has entered the deep submicron stage, the size of MOS devices has been continuously reduced, the thickness of gate oxide layer is thinner and thinner, the voltage withstanding capability of MOS devices is significantly reduced, and the damage of Electrostatic Discharge (ESD) to integrated circuits has become more and more significant. Therefore, ESD protection of integrated circuits becomes particularly important.
In order to enhance the protection capability against static electricity, an electrostatic protection circuit is usually connected to an input/output interface (I/O pad) of the chip, and the electrostatic protection circuit provides a discharge path for electrostatic current for internal circuits in the chip to prevent the static electricity from breaking down the internal circuits of the chip.
However, the performance of the conventional electrostatic protection structure is poor.
Disclosure of Invention
The invention provides an SCR electrostatic protection structure and a forming method thereof, which aim to improve the performance of the SCR electrostatic protection structure.
In order to solve the above problems, the present invention provides an SCR electrostatic protection structure, including: a semiconductor substrate; the N-type well is positioned in the semiconductor substrate and comprises a plurality of first unit areas to Q unit areas which are separated, and Q is an integer more than or equal to 3; a plurality of discrete first-level main cells to Q-level main cells located in the N-type well, wherein the k-level main cells are located in a k-level cell region, and k is an integer greater than or equal to 1 and less than or equal to Q; the kth stage main unit includes: an N-type doped region located at the top of the kth unit region of the N-type well; the first P-type doped region is positioned at the top of the kth unit region of the N-type well, is positioned at the side part of the N-type doped region and is separated from the N-type doped region; the second P-type doped region is positioned in the kth unit region of the N-type trap, positioned at the bottom of the first P-type doped region and adjacent to the first P-type doped region, and also extends to the bottom of the N-type doped region and adjacent to the N-type doped region; the N-type doped region in the first-level main unit is electrically connected with the first P-type doped region in the Q-th-level main unit, the first P-type doped region in the i-1-level main unit is electrically connected with the N-type doped region in the i-th-level main unit, and i is an integer which is greater than or equal to 3 and less than or equal to Q; the first P-type doped region in the first-stage main unit is used for being connected with an anode potential, and the N-type doped region in the second-stage main unit is used for being connected with a cathode potential.
Optionally, the concentration of P-type ions in the second P-type doped region is less than the concentration of P-type ions in the first P-type doped region.
Optionally, the method further includes: and the silicide blocking layer is positioned on the surface of the semiconductor substrate between the N-type doped region and the first P-type doped region.
Optionally, the method further includes: and an isolation layer in the semiconductor substrate between the j-th cell region and the j + 1-th cell region, wherein j is an integer greater than or equal to 1 and less than or equal to Q-1.
Optionally, the bottom surface of the isolation layer is lower than the bottom surface of the second P-type doped region and higher than the bottom surface of the N-type well.
Optionally, the method further includes: and a first connection line on the semiconductor substrate, the first connection line electrically connecting the N-type doped region in the first-level main cell and the first P-type doped region in the Q-th-level main cell.
Optionally, the method further includes: and an i-2 th level connection line on the semiconductor substrate, the i-2 th level connection line electrically connecting the first P-type doped region in the i-1 th level main cell and the N-type doped region in the i-th level main cell.
Optionally, the semiconductor substrate has substrate trap ions therein, and the conductivity type of the substrate trap ions is P-type.
The invention also provides a forming method of the SCR electrostatic protection structure, which comprises the following steps: providing a semiconductor substrate; forming an N-type well in a semiconductor substrate, wherein the N-type well comprises a plurality of first unit areas to a Q unit area which are separated, and Q is an integer more than or equal to 3; forming a plurality of discrete first-level main cells to Q-level main cells in the N-type well, wherein the k-level main cells are positioned in a k-level cell area, and k is an integer greater than or equal to 1 and less than or equal to Q; the method of forming a kth level master cell includes: forming an N-type doped region on the top of the kth unit region of the N-type well; forming a first P-type doped region at the top of the kth unit region of the N-type well, wherein the first P-type doped region is positioned at the side part of the N-type doped region and is separated from the N-type doped region; forming a second P-type doped region in the kth unit region of the N-type well, wherein the second P-type doped region is positioned at the bottom of the first P-type doped region and is adjacent to the first P-type doped region, and the second P-type doped region also extends to the bottom of the N-type doped region and is adjacent to the N-type doped region; the N-type doped region in the first-level main unit is electrically connected with the first P-type doped region in the Q-th-level main unit, the first P-type doped region in the i-1-level main unit is electrically connected with the N-type doped region in the i-th-level main unit, and i is an integer which is greater than or equal to 3 and less than or equal to Q; the first P-type doped region in the first-stage main unit is used for being connected with an anode potential, and the N-type doped region in the second-stage main unit is used for being connected with a cathode potential.
Optionally, the concentration of P-type ions in the second P-type doped region is less than the concentration of P-type ions in the first P-type doped region.
Optionally, the method further includes: and forming a silicide blocking layer on the surface of the semiconductor substrate between the N-type doped region and the first P-type doped region.
Optionally, the method further includes: before forming the first-to Q-th-level main cells, an isolation layer in the semiconductor substrate between the j-th to j + 1-th cell regions, j being an integer of 1 or more and Q-1 or less.
Optionally, the bottom surface of the isolation layer is lower than the bottom surface of the second P-type doped region and higher than the bottom surface of the N-type well.
Optionally, the method further includes: and forming a first connecting wire on the semiconductor substrate, wherein the first connecting wire is electrically connected with the N-type doped region in the first-stage main unit and the first P-type doped region in the Q-th-stage main unit.
Optionally, the method further includes: and forming an i-2 th level connection line on the semiconductor substrate, wherein the i-2 th level connection line is electrically connected with the first P type doped region in the i-1 th level main unit and the N type doped region in the i-1 th level main unit.
Optionally, the semiconductor substrate has substrate trap ions therein, and the conductivity type of the substrate trap ions is P-type.
Compared with the prior art, the technical scheme of the invention has the following advantages:
in the SCR electrostatic protection structure provided by the technical solution of the present invention, the SCR electrostatic protection structure has a current leakage structure that is a PNPN structure, the current leakage structure includes a PNP tube and an NPN tube, a first P-type doped region in the first-stage main cell and a second P-type doped region at the bottom of the first P-type doped region in the first-stage main cell serve as an emitter of the PNP tube, an N-type well located at the bottom of the second P-type doped region in the first-stage main cell and the second P-type doped region in the second-stage main cell serve as a base of the PNP tube, a second P-type doped region located at the bottom of the N-type doped region in the second-stage main cell serve as a collector of the PNP tube, an N-type well located at the bottom of the second P-type doped region in the first-stage main cell and the second P-type doped region in the second-stage main cell serve as a collector of the NPN tube, a second P-type doped, the N-type doped region in the second-stage main unit is used as an emitter of the NPN tube. The current bleeding structure has a current bleeding path. The N-type doped region and the first P-type doped region in each stage of main unit are connected in series to form a diode series ring. The diode series ring has a diode conduction path. The diode conduction path is: the first P type doping area in the first-level main unit passes through the second P type doping area in the first-level main unit to the N type doping area in the first-level main unit, the N type doping area in the first-level main unit to the first P type doping area in the Q-th-level main unit, the first P type doping area in the Q-th-level main unit passes through the second P type doping area in the Q-th-level main unit to the N type doping area in the Q-th-level main unit, the N type doping area in the i-th-1-level main unit to the first P type doping area in the i-1-th-level main unit, and the first P type doping area in the i-1-th-level main unit passes through the second P type doping area in the i-1-level main unit to the N type doping area in the i-1-th-level main unit until the N type doping area in the second-level main unit.
Applying trigger voltage on the cathode and the anode, firstly conducting the diode series ring, and conducting the diode series ring, so that for the NPN tube of the current leakage structure, the N-type doped region in the second-stage main unit and the second P-type doped region in the second-stage main unit are forward biased, and the base of the NPN tube has current, that is, the second P-type doped region in the second-stage main unit has current, so that the NPN tube of the current leakage structure is conducted, so that electrons reach the N-type well at the bottom of the second P-type doped region in the second-stage main unit from the N-type doped region in the second-stage main unit through the second P-type doped region in the second-stage main unit, the potential of the N-type well at the bottom of the second P-type doped region in the second-stage main unit is reduced, that is the base potential of the PNP tube in the current leakage structure is reduced, the PNP tube is enabled to be conducted, so that the current leakage structure is conducted. The trigger voltage of the SCR electrostatic protection structure is reduced.
And secondly, the second P-type doped region is a part of the diode serial ring, and the second P-type doped region is arranged, so that the Darlington effect of the diode serial ring is effectively inhibited, and the electric leakage is reduced.
And thirdly, the first-stage main unit to the Q-th-stage main unit are all in the same N-type well, so that the first-stage main unit to the Q-th-stage main unit are compactly arranged, and the integration level of the SCR electrostatic protection structure is improved.
And thirdly, the current discharge structure in the SCR electrostatic protection structure is composed of a parasitic PNP tube and a parasitic NPN tube, and other SCR structures connected with the diode series ring are not arranged, so that the current discharge structure is prevented from being diversified in type, further, the SCR electrostatic protection structure is prevented from being triggered for many times during working, and the secondary resetting problem is avoided.
Drawings
Fig. 1 to fig. 3 are schematic structural diagrams illustrating a process of forming an SCR electrostatic protection structure according to an embodiment of the invention.
Detailed Description
As described in the background, the performance of the existing SCR electrostatic protection structures is poor.
There are two important parameters in the SCR electrostatic protection architecture, the holding voltage and the trigger voltage, respectively. For some SCR electrostatic protection structures for low-voltage device protection, the holding voltage of the SCR electrostatic protection structure can usually meet the requirement, but the trigger voltage is higher, so the trigger voltage of the SCR electrostatic protection structure needs to be reduced.
On this basis, the invention provides an SCR electrostatic protection structure, which includes: an N-type well in the semiconductor substrate, the N-type well including a plurality of discrete first to Q-th cell regions, Q being an integer greater than or equal to 3; a plurality of discrete first-to-Q-th-stage main cells located in the N-type well, the k-th-stage main cell being located in the k-th cell region; the kth stage main unit includes: an N-type doped region located at the top of the kth unit region of the N-type well; the first P-type doped region is positioned at the top of the kth unit region of the N-type well, is positioned at the side part of the N-type doped region and is separated from the N-type doped region; the second P-type doped region is positioned in the kth unit region of the N-type well, positioned at the bottom of the first P-type doped region and adjacent to the first P-type doped region, and also extends to the bottom of the N-type doped region and adjacent to the N-type doped region; the N-type doped region in the first-level main unit is electrically connected with the first P-type doped region in the Q-th-level main unit, the first P-type doped region in the i-1-level main unit is electrically connected with the N-type doped region in the i-th-level main unit, and i is an integer greater than or equal to 3 and less than or equal to Q. The performance of the SCR electrostatic protection structure is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 1 to fig. 3 are schematic structural diagrams illustrating a process of forming an SCR electrostatic protection structure according to an embodiment of the invention.
Referring to fig. 1, a semiconductor substrate 200 is provided.
The semiconductor substrate 200 has substrate trap ions therein, and the conductivity type of the substrate trap ions is P-type.
The material of the semiconductor substrate 200 includes single crystal silicon, single crystal germanium, or single crystal silicon germanium.
Referring to fig. 2, an N-type well 210 is formed in a semiconductor substrate 200.
The N-well 210 includes a plurality of discrete first to Q-th cell regions, Q being an integer greater than or equal to 3.
In this embodiment, taking Q as 3 as an example, the N-type well 210 includes several discrete first, second and third cell regions.
In this embodiment, the method further includes: an isolation layer 201 is formed in the semiconductor substrate, the isolation layer 201 serving to isolate adjacent main cells to be formed later.
The isolation layer 201 is located in the semiconductor substrate 200 between the j-th cell region to the j + 1-th cell region.
Wherein j is an integer of 1 or more and Q-1 or less.
The bottom surface of the isolation layer 201 is higher than the bottom surface of the N-well 210, and the bottom surface of the isolation layer 201 is lower than the bottom surface of the subsequent second P-type doped region.
Referring to fig. 3, a number of discrete first-to-Q-th-stage main cells are formed in the N-type well 210.
The kth-stage main cells are located in the kth cell region, and k is an integer of 1 or more and Q or less.
The method of forming a kth level master cell includes: forming an N-type doped region 220 on top in the kth cell region of the N-type well 210; forming a first P-type doped region 230 on the top of the kth cell region of the N-well 210, the first P-type doped region 230 being located at the side of the N-type doped region 220 and being separated from the N-type doped region 220; a second P-type doped region 240 is formed in the kth cell region of the N-well 210, the second P-type doped region 240 is located at the bottom of the first P-type doped region 230 and adjacent to the first P-type doped region 230, and the second P-type doped region 240 further extends to the bottom of the N-type doped region 220 and adjacent to the N-type doped region 220.
The N-type doped region 220 in the first-level main cell is electrically connected with the first P-type doped region 230 in the Q-th-level main cell, the first P-type doped region 230 in the i-1-level main cell is electrically connected with the N-type doped region 220 in the i-th-level main cell, and i is an integer greater than or equal to 3 and less than or equal to Q; the first P-type doped region 230 in the first-level main cell is used for connecting an anode potential, and the N-type doped region 220 in the second-level main cell is used for connecting a cathode potential.
The concentration of P-type ions in the second P-type doped region 240 is less than that of P-type ions in the first P-type doped region 230, which is favorable for forming a current leakage structure.
The concentration of the P-type ions in the second P-type doped region 240 is less than the concentration of the P-type ions in the first P-type doped region 230 and is greater than or equal to the concentration of the substrate well ions in the semiconductor substrate 200.
In one embodiment, the concentration of the P-type ions in the second P-type doped region 240 is 3/5-1/20 of the concentration of the P-type ions in the first P-type doped region 230.
The forming method of the SCR electrostatic protection structure further comprises the following steps: a silicide blocking layer 250 is formed on the surface of the semiconductor substrate 200 between the N-type doped region 220 and the first P-type doped region 230.
The role of the silicide block layer 250 includes: the formation of metal silicide material on the surface of the semiconductor substrate 200 between the N-type doped region 220 and the first P-type doped region 230 is avoided, and the short circuit between the N-type doped region 220 and the first P-type doped region 230 is avoided.
The material of the silicide blocking layer 250 is an insulating material.
It should be noted that the surface of the N-type doped region 220 and the surface of the first P-type doped region 230 both have a metal silicide layer.
The forming method of the SCR electrostatic protection structure further comprises the following steps: a first connection line electrically connecting the N-type doped region 220 in the first-level main cell and the first P-type doped region 230 in the Q-th-level main cell is formed on the semiconductor substrate 200.
One end of the first connection line is connected to the metal silicide layer on the surface of the N-type doped region 220 in the first-level main cell, and the other end of the first connection line is connected to the metal silicide layer on the surface of the first P-type doped region 230 in the Q-th-level main cell.
The forming method of the SCR electrostatic protection structure further comprises the following steps: an i-2 th level connection line is formed on the semiconductor substrate 200, and the i-2 th level connection line electrically connects the first P-type doped region 230 in the i-1 th level main cell and the N-type doped region 220 in the i-th level main cell.
One end of the i-2 th level connection line is connected to the metal silicide layer on the surface of the first P-type doped region 230 in the i-1 st level main cell, and the other end of the i-2 th level connection line is connected to the metal silicide layer on the surface of the N-type doped region 220 in the i-th level main cell.
The present invention also provides an SCR electrostatic protection structure formed by the above method, referring to fig. 3, including:
a semiconductor substrate 200;
an N-type well 210 located in the semiconductor substrate 200, the N-type well 210 including a plurality of discrete first to Q-th cell regions, Q being an integer greater than or equal to 3;
a plurality of discrete first-to-Q-th-stage main cells located in the N-well 210, a k-th-stage main cell located in a k-th cell region, k being an integer greater than or equal to 1 and less than or equal to Q;
the kth stage main unit includes: an N-type doped region 220 located at the top in the kth cell region of the N-type well 210; a first P-type doped region 230 located at the top of the kth cell region of the N-well 210, the first P-type doped region 230 being located at the side of the N-type doped region 220 and being separated from the N-type doped region 220; a second P-type doped region 240 in the kth cell region of the N-well 210, the second P-type doped region 240 being at the bottom of the first P-type doped region 230 and adjacent to the first P-type doped region 230, the second P-type doped region 240 further extending to the bottom of the N-type doped region 220 and adjacent to the N-type doped region 220;
the N-type doped region 220 in the first-level main cell is electrically connected with the first P-type doped region 230 in the Q-th-level main cell, the first P-type doped region 230 in the i-1-level main cell is electrically connected with the N-type doped region 220 in the i-th-level main cell, and i is an integer greater than or equal to 3 and less than or equal to Q; the first P-type doped region 230 in the first-level main cell is used for connecting an anode potential, and the N-type doped region 220 in the second-level main cell is used for connecting a cathode potential.
The concentration of P-type ions in the second P-type doped region 240 is less than that in the first P-type doped region 230.
The SCR electrostatic protection structure further comprises: and a silicide blocking layer 250 positioned on the surface of the semiconductor substrate 200 between the N-type doped region 220 and the first P-type doped region 230.
The SCR electrostatic protection structure further comprises: the isolation layer 201, j, which is an integer of 1 or more and Q-1 or less, in the semiconductor substrate 200 between the j-th cell region to the j + 1-th cell region.
The bottom surface of the isolation layer 201 is lower than the bottom surface of the second P-type doped region 240 and higher than the bottom surface of the N-well 210.
The SCR electrostatic protection structure further comprises: a first connection line on the semiconductor substrate 200, the first connection line electrically connecting the N-type doped region 220 in the first-level main cell and the first P-type doped region 230 in the Q-th-level main cell.
The SCR electrostatic protection structure further comprises: an i-2 th level connection line on the semiconductor substrate 200, the i-2 th level connection line electrically connecting the first P-type doped region 230 in the i-1 th level main cell and the N-type doped region 220 in the i-th level main cell.
The semiconductor substrate 200 has substrate trap ions therein, and the conductivity type of the substrate trap ions is P-type.
In the SCR electrostatic protection structure of this embodiment, the current leakage structure in the SCR electrostatic protection structure is a PNPN structure, and the current leakage structure includes a PNP transistor and an NPN transistor, where the first P-type doped region 230 in the first-stage main cell and the second P-type doped region 240 at the bottom of the first P-type doped region 230 in the first-stage main cell are used as emitters of the PNP transistor, the N-type well 210 at the bottom of the second P-type doped region 240 in the first-stage main cell and the second P-type doped region 240 in the second-stage main cell are used as bases of the PNP transistor, the second P-type doped region 240 at the bottom of the N-type doped region 220 in the second-stage main cell is used as a collector of the PNP transistor, the N-type doped region 240 at the bottom of the second P-type doped region 240 in the first-stage main cell and the second P-type doped region 240 in the second-stage main cell are used as a collector of the NPN transistor, the second P-type doped region 240 at the, the N-doped region 220 in the second level main cell serves as the emitter of the NPN transistor. The current bleeding structure has a current bleeding path L1. The N-type doped region and the first P-type doped region in each stage of main unit are connected in series to form a diode series ring. The diode series ring has a diode conduction path. The diode conduction path is: the first P-type doped region 230 in the first-level main cell passes through the second P-type doped region 240 in the first-level main cell to the N-type doped region 220 in the first-level main cell, the N-type doped region 220 in the first-level main cell to the first P-type doped region 230 in the Q-level main cell, the first P-type doped region 230 in the Q-level main cell passes through the second P-type doped region 240 in the Q-level main cell to the N-type doped region 220 in the Q-level main cell, the N-type doped region in the i-level main cell to the first P-type doped region 230 in the i-1-level main cell, the first P-type doped region 230 in the i-1-level main cell passes through the second P-type doped region 240 in the i-1-level main cell to the N-type doped region 220 in the i-1-level main cell, and to the N-type doped region 220 in the second-level main cell.
Applying a trigger voltage to the cathode and the anode, firstly, the diode serial ring is turned on, and because the diode serial ring is turned on, for the NPN transistor of the current drain structure, the N-type doped region 220 in the second-stage main cell and the second P-type doped region 240 in the second-stage main cell are forward biased, and there is a current in the base of the NPN transistor, i.e., there is a current in the second P-type doped region 240 in the second-stage main cell, so that the NPN transistor of the current drain structure is turned on, and thus electrons reach the N-type well 210 at the bottom of the second P-type doped region 240 in the second-stage main cell from the N-type doped region 220 in the second-stage main cell through the second P-type doped region 240 in the second-stage main cell, so that the potential of the N-type well 210 at the bottom of the second P-type doped region 240 in the second-stage main cell is reduced, and the potential of the N-type well 210 at the bottom of the second P-type doped region 240 in the second-, the PNP tube is enabled to be conducted, so that the current leakage structure is conducted. The trigger voltage of the SCR electrostatic protection structure is reduced.
Secondly, the second P-type doped region 240 is a part of the diode serial ring, and the second P-type doped region 240 is provided, so that the darlington effect of the diode serial ring is effectively inhibited, and the leakage is reduced.
Third, the first-stage main cells to the Q-th-stage main cells are all in the same N-type well 210, so that the first-stage main cells to the Q-th-stage main cells are compactly arranged, and the integration level of the SCR electrostatic protection structure is improved.
And thirdly, the current discharge structure in the SCR electrostatic protection structure is composed of a parasitic PNP tube and a parasitic NPN tube, and other SCR structures connected with the diode series ring are not arranged, so that the current discharge structure is prevented from being diversified in type, further, the SCR electrostatic protection structure is prevented from being triggered for many times during working, and the secondary resetting problem is avoided.
The SCR electrostatic protection structure of this embodiment can be used for protection of low-voltage devices, and the trigger voltage of the SCR electrostatic protection structure is low.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (16)
1. An SCR electrostatic protection structure, comprising:
a semiconductor substrate;
the N-type well is positioned in the semiconductor substrate and comprises a plurality of first unit areas to Q unit areas which are separated, and Q is an integer more than or equal to 3;
a plurality of discrete first-level main cells to Q-level main cells located in the N-type well, wherein the k-level main cells are located in a k-level cell region, and k is an integer greater than or equal to 1 and less than or equal to Q;
the kth stage main unit includes: an N-type doped region located at the top of the kth unit region of the N-type well; the first P-type doped region is positioned at the top of the kth unit region of the N-type well, is positioned at the side part of the N-type doped region and is separated from the N-type doped region; the second P-type doped region is positioned in the kth unit region of the N-type trap, positioned at the bottom of the first P-type doped region and adjacent to the first P-type doped region, and also extends to the bottom of the N-type doped region and adjacent to the N-type doped region;
the N-type doped region in the first-level main unit is electrically connected with the first P-type doped region in the Q-th-level main unit, the first P-type doped region in the i-1-level main unit is electrically connected with the N-type doped region in the i-th-level main unit, and i is an integer which is greater than or equal to 3 and less than or equal to Q; the first P-type doped region in the first-stage main unit is used for being connected with an anode potential, and the N-type doped region in the second-stage main unit is used for being connected with a cathode potential.
2. The SCR electrostatic protection structure of claim 1, wherein the concentration of P-type ions in the second P-type doped region is less than the concentration of P-type ions in the first P-type doped region.
3. The SCR electrostatic protection structure of claim 1, further comprising: and the silicide blocking layer is positioned on the surface of the semiconductor substrate between the N-type doped region and the first P-type doped region.
4. The SCR electrostatic protection structure of claim 1, further comprising: and an isolation layer in the semiconductor substrate between the j-th cell region and the j + 1-th cell region, wherein j is an integer greater than or equal to 1 and less than or equal to Q-1.
5. The SCR electrostatic protection structure of claim 4, wherein a bottom surface of the isolation layer is lower than a bottom surface of the second P-type doped region and higher than a bottom surface of the N-type well.
6. The SCR electrostatic protection structure of claim 1, further comprising: and a first connection line on the semiconductor substrate, the first connection line electrically connecting the N-type doped region in the first-level main cell and the first P-type doped region in the Q-th-level main cell.
7. The SCR electrostatic protection structure of claim 1, further comprising: and an i-2 th level connection line on the semiconductor substrate, the i-2 th level connection line electrically connecting the first P-type doped region in the i-1 th level main cell and the N-type doped region in the i-th level main cell.
8. The SCR electrostatic protection structure of claim 1, wherein said semiconductor substrate has substrate trap ions therein, said substrate trap ions being of a P-type conductivity type.
9. A method for forming an SCR electrostatic protection structure is characterized by comprising the following steps:
providing a semiconductor substrate;
forming an N-type well in a semiconductor substrate, wherein the N-type well comprises a plurality of first unit areas to a Q unit area which are separated, and Q is an integer more than or equal to 3;
forming a plurality of discrete first-level main cells to Q-level main cells in the N-type well, wherein the k-level main cells are positioned in a k-level cell area, and k is an integer greater than or equal to 1 and less than or equal to Q;
the method of forming a kth level master cell includes: forming an N-type doped region on the top of the kth unit region of the N-type well; forming a first P-type doped region at the top of the kth unit region of the N-type well, wherein the first P-type doped region is positioned at the side part of the N-type doped region and is separated from the N-type doped region; forming a second P-type doped region in the kth unit region of the N-type well, wherein the second P-type doped region is positioned at the bottom of the first P-type doped region and is adjacent to the first P-type doped region, and the second P-type doped region also extends to the bottom of the N-type doped region and is adjacent to the N-type doped region;
the N-type doped region in the first-level main unit is electrically connected with the first P-type doped region in the Q-th-level main unit, the first P-type doped region in the i-1-level main unit is electrically connected with the N-type doped region in the i-th-level main unit, and i is an integer which is greater than or equal to 3 and less than or equal to Q; the first P-type doped region in the first-stage main unit is used for being connected with an anode potential, and the N-type doped region in the second-stage main unit is used for being connected with a cathode potential.
10. The method as claimed in claim 9, wherein the concentration of P-type ions in the second P-type doped region is less than the concentration of P-type ions in the first P-type doped region.
11. The method for forming an SCR electrostatic protection structure of claim 9, further comprising: and forming a silicide blocking layer on the surface of the semiconductor substrate between the N-type doped region and the first P-type doped region.
12. The method for forming an SCR electrostatic protection structure of claim 9, further comprising: before forming the first-to Q-th-level main cells, an isolation layer in the semiconductor substrate between the j-th to j + 1-th cell regions, j being an integer of 1 or more and Q-1 or less.
13. The method as claimed in claim 12, wherein a bottom surface of the isolation layer is lower than a bottom surface of the second P-type doped region and higher than a bottom surface of the N-type well.
14. The method for forming an SCR electrostatic protection structure of claim 9, further comprising: and forming a first connecting wire on the semiconductor substrate, wherein the first connecting wire is electrically connected with the N-type doped region in the first-stage main unit and the first P-type doped region in the Q-th-stage main unit.
15. The method for forming an SCR electrostatic protection structure of claim 9, further comprising: and forming an i-2 th level connection line on the semiconductor substrate, wherein the i-2 th level connection line is electrically connected with the first P type doped region in the i-1 th level main unit and the N type doped region in the i-1 th level main unit.
16. The method as claimed in claim 9, wherein the semiconductor substrate has substrate trap ions therein, and the conductivity type of the substrate trap ions is P-type.
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