TW201322409A - Electrostatic discharge protection device - Google Patents

Electrostatic discharge protection device Download PDF

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TW201322409A
TW201322409A TW100143269A TW100143269A TW201322409A TW 201322409 A TW201322409 A TW 201322409A TW 100143269 A TW100143269 A TW 100143269A TW 100143269 A TW100143269 A TW 100143269A TW 201322409 A TW201322409 A TW 201322409A
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type
well region
region
type well
electrically connected
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TW100143269A
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TWI435432B (en
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Qi-An Xu
Chieh-Wei He
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Macronix Int Co Ltd
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Abstract

An ESD protection device including second P-type wells, first P+-type doped regions, first N+-type doped regions and a P-type substrate having a first P-type well, an N-type well and an N-type deep well is provided. The second P-type wells are disposed in the N-type deep well. The first P+-type doped regions and the first N+-type doped regions are respectively disposed in the first P-type well, the N-type well and the second P-type wells in alternation. The first P+-type doped region in the N-type well and the N-type deep well are electrically connected to the first connection terminal. The doped regions in the first P-type well and the P-type substrate are electrically connected to the second connection terminal. The second P-type wells and the first N+-type doped regions therein form a diode string connected in series between the first N+-type doped region of the N-type well and the second connection terminal.

Description

靜電放電保護元件Electrostatic discharge protection component

本發明是有關於一種保護元件,且特別是有關於一種靜電放電保護元件。This invention relates to a protective element and, more particularly, to an electrostatic discharge protection element.

靜電放電(electrostatic discharge,ESD)往往是造成積體電路發生靜電過度應力(electrostatic overstress)或是永久性損毀的主要原因,因此常見的作法是在核心電路(core circuit)與焊墊(pad)之間加入靜電放電保護元件,以防止靜電放電的損害。在諸多靜電放電保護元件中,二極體觸發矽控整流器(diode-triggered silicon controlled rectifier,DTSCR)因具有較低的觸發電壓以及快速導通的特性,故廣泛地應用在各類型的積體電路中。Electrostatic discharge (ESD) is often the main cause of electrostatic overstress or permanent damage in integrated circuits. Therefore, common methods are in core circuits and pads. An electrostatic discharge protection element is added between them to prevent damage from electrostatic discharge. Among many electrostatic discharge protection components, diode-triggered silicon controlled rectifier (DTSCR) is widely used in various types of integrated circuits because of its low trigger voltage and fast turn-on characteristics. .

圖1為習知之二極體觸發矽控整流器的剖面圖。參照圖1,二極體觸發矽控整流器100包括P型基底110以及配置在P型基底110內的P型井區120與N型井區131~134。此外,P+型摻雜區141~145與N+型摻雜區151~155交替地配置在P型井區120與N型井區131~134內。在電性連接上,由P+型摻雜區142~145與N型井區131~134所構成的多個二極體相互串接在焊墊101與接地配線GND1之間。再者,P型井區120內的P+型摻雜區141與N+型摻雜區151,以及P型基底110內的P+型摻雜區146,皆電性連接至接地配線GND1。1 is a cross-sectional view of a conventional diode triggered chirp rectifier. Referring to FIG. 1, the diode-triggered pilot rectifier 100 includes a P-type substrate 110 and a P-type well region 120 and N-type well regions 131-134 disposed in the P-type substrate 110. Further, the P+ doping regions 141 to 145 and the N+ doping regions 151 to 155 are alternately disposed in the P-type well region 120 and the N-type well region 131 to 134. In the electrical connection, a plurality of diodes composed of the P+ doping regions 142 to 145 and the N-type well regions 131 to 134 are connected in series between the pad 101 and the ground wiring GND1. Furthermore, the P+ doping region 141 and the N+ doping region 151 in the P-type well region 120 and the P+ doping region 146 in the P-type substrate 110 are electrically connected to the ground wiring GND1.

藉此,矽控整流器100的佈局結構將可等效成如圖2所示的電路圖。如圖2所示,二極體觸發矽控整流器100包括由PNP電晶體MP21與NPN電晶體MN2組合而成的矽控整流電路、連接成達靈頓組態(Darlington configuration)的PNP電晶體MP22~MP24以及電阻R2。在操作上,ESD事件可分類成多種模式,例如:PS模式與NS模式。其中,PS模式是於焊墊101輸入一正脈衝訊號且接地配線GND1接地,而NS模式則是於焊墊101輸入一負脈衝訊號且接地配線GND1接地。當來自焊墊101的靜電訊號為正脈衝訊號時,亦即PS模式的ESD事件發生時,PNP電晶體MP22~MP24將貢獻微小的電流,以觸發由PNP電晶體MP21與NPN電晶體MN2組合而成的矽控整流電路。藉此,來自焊墊101的正脈衝訊號將可透過矽控整流電路導引至接地配線GND1。Thereby, the layout structure of the controlled rectifier 100 can be equivalent to the circuit diagram shown in FIG. 2. As shown in FIG. 2, the diode-triggered rectifier rectifier 100 includes a voltage-controlled rectifier circuit composed of a PNP transistor MP21 and an NPN transistor MN2, and a PNP transistor MP22 connected to a Darlington configuration. ~MP24 and resistor R2. In operation, ESD events can be classified into multiple modes, such as PS mode and NS mode. The PS mode is that a positive pulse signal is input to the pad 101 and the ground wiring GND1 is grounded, and in the NS mode, a negative pulse signal is input to the pad 101 and the ground wiring GND1 is grounded. When the electrostatic signal from the pad 101 is a positive pulse signal, that is, the ESD event of the PS mode occurs, the PNP transistors MP22~MP24 will contribute a small current to trigger the combination of the PNP transistor MP21 and the NPN transistor MN2. A controlled rectifier circuit. Thereby, the positive pulse signal from the pad 101 can be guided to the ground wiring GND1 through the step-controlled rectifier circuit.

然而,當來自焊墊101的靜電訊號為負脈衝訊號時,亦即NS模式的ESD事件發生時,二極體觸發矽控整流器100將無法提供放電路徑。換言之,二極體觸發矽控整流器100並不具有NS模式的靜電放電保護功能,因此積體電路必需額外設置反向的二極體D2。此外,當核心電路102正常操作時,由N型井區131~134與P+型摻雜區142~145所形成的二極體串將偏壓在順向偏壓下。此時,二極體觸發矽控整流器100中等效的PNP電晶體MP22~MP24將產生縱向的漏電路徑,進而導致二極體觸發矽控整流器100產生龐大的漏電流。However, when the electrostatic signal from the pad 101 is a negative pulse signal, that is, an ESD event of the NS mode occurs, the diode-triggered rectifier rectifier 100 will not be able to provide a discharge path. In other words, the diode-triggered rectifier rectifier 100 does not have the electrostatic discharge protection function of the NS mode, so the integrated circuit must additionally provide the reverse diode D2. In addition, when the core circuit 102 is operating normally, the diode strings formed by the N-type well regions 131-134 and the P+-type doping regions 142-145 will be biased under forward bias. At this time, the equivalent PNP transistors MP22~MP24 in the diode-triggered rectifier rectifier 100 will generate a longitudinal leakage path, which in turn causes the diode to trigger the gated rectifier 100 to generate a large leakage current.

換言之,二極體觸發矽控整流器100將無法滿足高速傳輸元件所需之低漏電流的條件,進而無法應用在高速傳輸元件上。此外,二極體觸發矽控整流器100並不具有NS模式的靜電放電保護功能。In other words, the diode-triggered rectifier rectifier 100 will not be able to meet the low leakage current conditions required for high-speed transmission components, and thus cannot be applied to high-speed transmission components. In addition, the diode-triggered rectifier rectifier 100 does not have an electrostatic discharge protection function of the NS mode.

本發明提供一種靜電放電保護元件,利用N型深井區中的P型井區與N+型摻雜區來形成二極體串,以阻隔縱向漏電路徑的產生。藉此,本發明之靜電放電保護元件將可應用在高速傳輸元件上。The present invention provides an electrostatic discharge protection element that utilizes a P-type well region and an N+-type doped region in an N-type deep well region to form a diode string to block the generation of a longitudinal leakage path. Thereby, the electrostatic discharge protection element of the present invention can be applied to a high speed transmission element.

本發明提供一種靜電放電保護元件,利用N型深井區與P型基底來形成反向的二極體。藉此,本發明之靜電放電保護元件將具有PS模式與NS模式的靜電放電保護功能。The present invention provides an electrostatic discharge protection element that utilizes an N-type deep well region and a P-type substrate to form a reversed diode. Thereby, the electrostatic discharge protection element of the present invention will have an electrostatic discharge protection function of the PS mode and the NS mode.

本發明提出一種靜電放電保護元件,具有第一連接端與第二連接端,並包括P型基底、M個第二P型井區、多個第一P+型摻雜區以及多個第一N+型摻雜區,M為大於1的整數。P型基底具有第一P型井區、N型井區以及N型深井區。其中,N型深井區電性連接第一連接端,P型基底電性連接第二連接端。所述M個第二P型井區配置於N型深井區內。這些第一P+型摻雜區分別配置在第一P型井區、N型井區以及這些第二P型井區內。這些第一N+型摻雜區分別配置在第一P型井區、N型井區以及這些第二P型井區內,且這些第一N+型摻雜區與這些第一P+型摻雜區交替配置。The present invention provides an electrostatic discharge protection component having a first connection end and a second connection end, and includes a P-type substrate, M second P-type well regions, a plurality of first P+-type doped regions, and a plurality of first N+ Type doped region, M is an integer greater than one. The P-type substrate has a first P-type well region, an N-type well region, and an N-type deep well region. Wherein, the N-type deep well region is electrically connected to the first connection end, and the P-type substrate is electrically connected to the second connection end. The M second P-type well zones are disposed in the N-type deep well zone. The first P+ type doping regions are respectively disposed in the first P-type well region, the N-type well region, and the second P-type well regions. The first N+ doped regions are respectively disposed in the first P-type well region, the N-type well region, and the second P-type well regions, and the first N+-type doped regions and the first P+-type doped regions Alternate configuration.

在本發明之一實施例中,上述之位在第一P型井區內的第一P+型摻雜區與第一N+型摻雜區電性連接至第二連接端。位在N型井區內的第一P+型摻雜區與第一N+型摻雜區分別電性連接至第一連接端與第1個第二P型井區內的第一P+型摻雜區。第i個第二P型井區內的第一N+型摻雜區電性連接至第i+1個第二P型井區內的第一P+型摻雜區,且第M個第二P型井區內的第一N+型摻雜區電性連接至第二連接端,i為整數且1≦i≦(M-1)。In an embodiment of the invention, the first P+ doping region and the first N+ doping region in the first P-type well region are electrically connected to the second connection terminal. The first P+ doped region and the first N+ doped region located in the N-type well region are electrically connected to the first P+ type doping in the first connection end and the first second P-type well region, respectively. Area. The first N+ type doped region in the i-th second P-type well region is electrically connected to the first P+-type doped region in the i+1th second P-type well region, and the Mth second P The first N+ type doped region in the well region is electrically connected to the second connection end, i is an integer and 1≦i≦(M-1).

在本發明之一實施例中,上述之N型井區位在第一P型井區與N型深井區之間,且N型井區與第一P型井區相接觸,N型井區與N型深井區互不接觸。In an embodiment of the invention, the N-type well location is between the first P-type well area and the N-type deep well area, and the N-type well area is in contact with the first P-type well area, and the N-type well area is N-type deep well areas do not touch each other.

在本發明之一實施例中,上述M個第二P型井區互不接觸。In an embodiment of the invention, the M second P-type well regions are not in contact with each other.

在本發明之一實施例中,上述之靜電放電保護元件更包括第二N+型摻雜區。其中,第二N+型摻雜區配置在N型深井區內,並相鄰於第M個第二P型井區,且N型深井區透過第二N+型摻雜區電性連接第一連接端。In an embodiment of the invention, the electrostatic discharge protection device further includes a second N+ type doping region. Wherein, the second N+ doping region is disposed in the N-type deep well region and adjacent to the Mth second P-type well region, and the N-type deep well region is electrically connected to the first connection through the second N+-type doping region end.

在本發明之一實施例中,上述之靜電放電保護元件更包括第二P+型摻雜區。其中,第二P+型摻雜區配置於P型基底內,並相鄰於N型深井區,且P型基底透過第二P+型摻雜區電性連接第二連接端。In an embodiment of the invention, the electrostatic discharge protection device further includes a second P+ doped region. The second P+ type doped region is disposed in the P-type substrate and adjacent to the N-type deep well region, and the P-type substrate is electrically connected to the second connection end through the second P+-type doped region.

本發明提出一種靜電放電保護元件,具有第一連接端與第二連接端,並包括P型基底、第二P型井區、多個第一P+型摻雜區以及多個第一N+型摻雜區。P型基底具有第一P型井區、N型井區以及N型深井區,其中N型深井區電性連接第一連接端,P型基底電性連接第二連接端。第二P型井區配置於N型深井區內。這個第一P+型摻雜區分別配置在第一P型井區、N型井區以及第二P型井區內。這些第一N+型摻雜區分別配置在第一P型井區、N型井區以及第二P型井區內,且這些第一N+型摻雜區與這些第一P+型摻雜區交替配置。The present invention provides an electrostatic discharge protection element having a first connection end and a second connection end, and includes a P-type substrate, a second P-type well region, a plurality of first P+-type doped regions, and a plurality of first N+-type doping Miscellaneous area. The P-type substrate has a first P-type well region, an N-type well region and an N-type deep well region, wherein the N-type deep well region is electrically connected to the first connection end, and the P-type substrate is electrically connected to the second connection end. The second P-type well region is disposed in the N-type deep well region. The first P+ doped regions are respectively disposed in the first P-type well region, the N-type well region, and the second P-type well region. The first N+ doped regions are respectively disposed in the first P-type well region, the N-type well region, and the second P-type well region, and the first N+-type doped regions are alternated with the first P+-type doped regions. Configuration.

在本發明之一實施例中,上述之位在第一P型井區內的第一P+型摻雜區與第一N+型摻雜區電性連接至第二連接端。位在N型井區內的第一P+型摻雜區與第一N+型摻雜區分別電性連接至第一連接端與第二P型井區中的第一P+型摻雜區。位在第二P型井區內的第一N+型摻雜區電性連接至第二連接端。In an embodiment of the invention, the first P+ doping region and the first N+ doping region in the first P-type well region are electrically connected to the second connection terminal. The first P+ doped region and the first N+ doped region located in the N-type well region are electrically connected to the first P+-type doped region in the first connection end and the second P-type well region, respectively. The first N+-type doped region located in the second P-type well region is electrically connected to the second connection terminal.

基於上述,本發明是將N型深井區設置在P型基底內,並在N型深井區設置由P型井區與N+型摻雜區所構成的二極體串。此外,N型深井區電性連接至第一連接端連,且P型基底電性連接至第二連接端。藉此,當靜電放電事件發生時,靜電放電保護元件將可利用N型深井區內的二極體串來觸發其內部的矽控整流電路,或是導通其內部的反向二極體。此外,當核心電路正常操作時,N型深井區將藉由元件的第一連接端連接至焊墊,進而偏壓在反向電壓下。藉此,本發明之靜電放電保護元件將同時具有PS模式與NS模式的靜電放電保護功能,並可應用在高速傳輸元件上。Based on the above, the present invention provides an N-type deep well region in a P-type substrate, and a diode string composed of a P-type well region and an N+-type doped region in the N-type deep well region. In addition, the N-type deep well region is electrically connected to the first connection end, and the P-type substrate is electrically connected to the second connection end. Thereby, when an electrostatic discharge event occurs, the electrostatic discharge protection component can use the diode string in the N-type deep well region to trigger the internal controlled rectifier circuit or turn on the internal reverse diode. In addition, when the core circuit is operating normally, the N-type deep well region will be connected to the pad by the first connection of the component, thereby biasing at the reverse voltage. Thereby, the electrostatic discharge protection element of the present invention will have both an electrostatic discharge protection function of the PS mode and the NS mode, and can be applied to a high speed transmission element.

為讓本發明之上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。The above described features and advantages of the present invention will be more apparent from the following description.

圖3為依據本發明之ㄧ實施例之靜電放電保護元件的剖面圖,其中靜電放電保護元件300具有第一連接端TM31與第二連接端TM32,且為了說明方便起見同一個第二連接端TM32分別標示在不同處。參照圖3,靜電放電保護元件300包括P型基底310、P型井區320、N型井區330、N型深井區340、多個P型井區351~353、多個P+型摻雜區361~366以及多個N+型摻雜區371~376。3 is a cross-sectional view of an electrostatic discharge protection element according to an embodiment of the present invention, wherein the electrostatic discharge protection element 300 has a first connection end TM31 and a second connection end TM32, and the same second connection end is provided for convenience of description. TM32 is marked in different places. Referring to FIG. 3, the electrostatic discharge protection component 300 includes a P-type substrate 310, a P-type well region 320, an N-type well region 330, an N-type deep well region 340, a plurality of P-type well regions 351-353, and a plurality of P+-type doped regions. 361~366 and a plurality of N+ doped regions 371~376.

在配置上,P型井區320、N型井區330以及N型深井區340配置於P型基底310內。此外,N型井區330位在P型井區320與N型深井區340之間。N型井區330與P型井區320相接觸,且N型井區330與N型深井區340互不接觸。再者,P型井區351~353配置於N型深井區340內,且P型井區351~353互不接觸。In configuration, the P-type well region 320, the N-type well region 330, and the N-type deep well region 340 are disposed within the P-type substrate 310. In addition, the N-type well region 330 is located between the P-type well region 320 and the N-type deep well region 340. The N-type well region 330 is in contact with the P-type well region 320, and the N-type well region 330 and the N-type deep well region 340 are not in contact with each other. Furthermore, the P-type well regions 351-353 are disposed in the N-type deep well region 340, and the P-type well regions 351-353 are not in contact with each other.

另ㄧ方面,P型井區320、N型井區330以及配置於N型深井區340內的P型井區351~353各自包括一個P+型摻雜區與一個N+型摻雜區,例如:P型井區320內配置有P+型摻雜區361與N+型摻雜區371,N型井區330內配置有P+型摻雜區362與N+型摻雜區372。此外,位在P型井區320、N型井區330以及P型井區351~353中的P+型摻雜區361~365與N+型摻雜區371~375交替配置。In another aspect, the P-type well region 320, the N-type well region 330, and the P-type well regions 351-353 disposed in the N-type deep well region 340 each include a P+ doped region and an N+ doped region, for example: A P+ doping region 361 and an N+ doping region 371 are disposed in the P-type well region 320, and a P+ doping region 362 and an N+ doping region 372 are disposed in the N-type well region 330. In addition, the P+ doping regions 361 to 365 and the N+ doping regions 371 to 375 located in the P-type well region 320, the N-type well region 330, and the P-type well region 351-353 are alternately arranged.

在電性連接上,P型井區320內的P+型摻雜區361與N+型摻雜區371電性連接至第二連接端TM32。N型井區330內的P+型摻雜區362與N+型摻雜區372分別電性連接至第一連接端TM31與P型井區351內的P+型摻雜區363。針對P型井區351~353內的摻雜區來看,N+型摻雜區373電性連接至P+型摻雜區364,N+型摻雜區374電性連接至P+型摻雜區365,且N+型摻雜區375電性連接至第二連接端TM32。In the electrical connection, the P+ doping region 361 and the N+ doping region 371 in the P-type well region 320 are electrically connected to the second connection terminal TM32. The P+ doping region 362 and the N+ doping region 372 in the N-type well region 330 are electrically connected to the P+-type doping region 363 in the first connection terminal TM31 and the P-type well region 351, respectively. For the doped regions in the P-type well regions 351-353, the N+-type doping region 373 is electrically connected to the P+-type doping region 364, and the N+-type doping region 374 is electrically connected to the P+-type doping region 365. The N+ doping region 375 is electrically connected to the second connection terminal TM32.

此外,N+型摻雜區376配置在N型深井區340內,並相鄰於P型井區353。再者,N+型摻雜區376電性連接至第一連接端TM31。換言之,N型深井區340將可透過N+型摻雜區376電性連接至第一連接端TM31。另ㄧ方面,P+型摻雜區366配置於P型基底310內,並相鄰於N型深井區340。此外,P+型摻雜區366電性連接至第二連接端TM32。換言之,P型基底310可透過P+型摻雜區366電性連接至第二連接端TM32。In addition, the N+ doped region 376 is disposed within the N-type deep well region 340 and adjacent to the P-type well region 353. Furthermore, the N+ doping region 376 is electrically connected to the first connection terminal TM31. In other words, the N-type deep well region 340 is electrically connectable to the first connection terminal TM31 through the N+ type doping region 376. In another aspect, the P+ doped region 366 is disposed within the P-type substrate 310 and adjacent to the N-type deep well region 340. In addition, the P+ doping region 366 is electrically connected to the second connection terminal TM32. In other words, the P-type substrate 310 can be electrically connected to the second connection end TM32 through the P+ type doping region 366.

圖4為用以說明圖3之靜電放電保護元件的等效電路圖。請同時參照圖3與圖4,在實際應用上,靜電放電保護元件300的兩端TM31與TM32可分別連接至積體電路中的焊墊301與接地配線GND3,且靜電放電保護元件300用以避免靜電放電事件對核心電路302所造成的損害。就佈局結構來看,N+型摻雜區371、P型井區320以及N型井區330將形成橫向的NPN電晶體MN4,且P+型摻雜區362、N型井區330以及P型基底310將形成縱向的PNP電晶體MP41。藉此,NPN電晶體MN4與PNP電晶體MP41將可形成一矽控整流電路。此外,電阻R4則是P型井區320所貢獻的等效電阻。4 is an equivalent circuit diagram for explaining the electrostatic discharge protection element of FIG. 3. Referring to FIG. 3 and FIG. 4 simultaneously, in practical applications, both ends TM31 and TM32 of the electrostatic discharge protection component 300 can be respectively connected to the pad 301 and the grounding GND3 in the integrated circuit, and the electrostatic discharge protection component 300 is used. The damage caused by the electrostatic discharge event to the core circuit 302 is avoided. As far as the layout structure is concerned, the N+ doping region 371, the P-type well region 320, and the N-type well region 330 will form a lateral NPN transistor MN4, and the P+ doping region 362, the N-type well region 330, and the P-type substrate. 310 will form a longitudinal PNP transistor MP41. Thereby, the NPN transistor MN4 and the PNP transistor MP41 will form a voltage controlled rectifier circuit. In addition, resistor R4 is the equivalent resistance contributed by P-well region 320.

再者,P型井區351、N型深井區340以及P型基底310將形成縱向的PNP電晶體MP42。相似地,P型井區352、N型深井區340以及P型基底310將形成縱向的PNP電晶體MP43,且P型井區353、N型深井區340以及P型基底310將形成縱向的PNP電晶體MP44。另ㄧ方面,P型井區351與N+型摻雜區373將形成二極體D41,P型井區352與N+型摻雜區374將形成二極體D42,且P型井區353與N+型摻雜區375將形成二極體D43。亦即,N型深井區340內的P型井區351~353以及N+型摻雜區373~375將形成一二極體串,亦即由二極體D41~D43串接而成的二極體串。此外,N型深井區340與P型基底310將形成反向的二極體D44。Furthermore, the P-type well region 351, the N-type deep well region 340, and the P-type substrate 310 will form a longitudinal PNP transistor MP42. Similarly, the P-type well region 352, the N-type deep well region 340, and the P-type substrate 310 will form a longitudinal PNP transistor MP43, and the P-type well region 353, the N-type deep well region 340, and the P-type substrate 310 will form a longitudinal PNP. Transistor MP44. On the other hand, the P-type well region 351 and the N+-type doped region 373 will form a diode D41, and the P-type well region 352 and the N+-type doped region 374 will form a diode D42, and the P-type well region 353 and N+ The doped region 375 will form a diode D43. That is, the P-type well regions 351-353 and the N+-type doping regions 373-375 in the N-type deep well region 340 form a diode string, that is, a diode formed by connecting the diodes D41 to D43 in series. Body string. In addition, the N-type deep well region 340 and the P-type substrate 310 will form a reversed diode D44.

換言之,P型井區320、N型井區330以及摻雜區361~362與371~372主要是用以構成一矽控整流電路,而N型深井區340內的二極體串則是用以觸發所述的矽控整流電路。因此,靜電放電保護元件300係為一種二極體觸發矽控整流器(diode-triggered SCR)。In other words, the P-type well region 320, the N-type well region 330, and the doped regions 361-362 and 371-372 are mainly used to form a controlled rectifier circuit, and the diode strings in the N-type deep well region 340 are used. To trigger the controlled rectifier circuit. Therefore, the electrostatic discharge protection component 300 is a diode-triggered SCR.

在實際應用上,當來自焊墊301的靜電訊號為正脈衝訊號,亦即PS模式的ESD事件發生時,則此時二極體串將提供微小的電流,進而觸發由NPN電晶體MN4與PNP電晶體MP41所形成的矽控整流電路。藉此,來自焊墊301的正脈衝訊號將可透過矽控整流電路所提供的大電流路徑導引至接地配線GND3。此外,當來自焊墊301的靜電訊號為負脈衝訊號時,亦即NS模式的ESD事件發生時,則此時的二極體D44將導通,進而提供導通至接地配線GND3的路徑給負脈衝訊號。換言之,在實際應用上,靜電放電保護元件300無需額外設置一個反向的二極體,就同時具有PS模式與NS模式的靜電放電保護功能。In practical applications, when the electrostatic signal from the pad 301 is a positive pulse signal, that is, an ESD event in the PS mode occurs, then the diode string will provide a small current, which is triggered by the NPN transistor MN4 and PNP. A voltage controlled rectifier circuit formed by the transistor MP41. Thereby, the positive pulse signal from the pad 301 can be guided to the ground wiring GND3 through the large current path provided by the step-controlled rectifier circuit. In addition, when the electrostatic signal from the pad 301 is a negative pulse signal, that is, the ESD event of the NS mode occurs, the diode D44 at this time will be turned on, thereby providing a path to the ground wiring GND3 to the negative pulse signal. . In other words, in practical applications, the electrostatic discharge protection component 300 does not need to additionally provide a reverse diode, and has both an electrostatic discharge protection function of the PS mode and the NS mode.

再者,就靜電放電保護元件300的佈局結構來看,等效的PNP電晶體MP42~MP44不會形成達靈頓組態。此外,P型井區與N+型摻雜區所形成的二極體串是配置在N型深井區340內,且N型深井區340是電性連接至焊墊301。因此,當核心電路302正常操作時,N型深井區340將偏壓在反向電壓下,進而阻隔了縱向漏電路徑的產生。亦即,當核心電路302正常操作時,靜電放電保護元件300中的等效PNP電晶體MP42~MP44將不會產生漏電路徑。換言之,當核心電路302正常操作時,靜電放電保護元件300並不會產生龐大的漏電流。藉此,靜電放電保護元件300將可滿足高速傳輸元件所需之低漏電流的條件,進而可以應用在高速傳輸元件上。Furthermore, in terms of the layout structure of the electrostatic discharge protection component 300, the equivalent PNP transistors MP42~MP44 do not form a Darlington configuration. In addition, the diode strings formed by the P-type well region and the N+-type doped region are disposed in the N-type deep well region 340, and the N-type deep well region 340 is electrically connected to the bonding pad 301. Thus, when the core circuit 302 is operating normally, the N-type deep well region 340 will be biased at a reverse voltage, thereby blocking the generation of a longitudinal leakage path. That is, when the core circuit 302 operates normally, the equivalent PNP transistors MP42 to MP44 in the electrostatic discharge protection element 300 will not generate a leakage path. In other words, when the core circuit 302 operates normally, the electrostatic discharge protection element 300 does not generate a large leakage current. Thereby, the electrostatic discharge protection element 300 can satisfy the condition of low leakage current required for the high-speed transmission element, and can be applied to the high-speed transmission element.

值得一提的是,圖3實施例所列舉的二極體串是由3個二極體D41~D43串接而成,但其並非用以限定本發明,本領域具有通常知識者也可依設計所任意需更改二極體串的組成個數。舉例來說,N型深井區340內的二極體串可由M個二極體串接而成,M為大於1的整數。此時,N型深井區340內將設置M個P型井區。此外,在電性連接上,第1個P型井區內的P+型摻雜區電性連接至N型井區330內的N+型摻雜區372。第i個P型井區內的N+型摻雜區電性連接至第i+1個P型井區內的P+型摻雜區,且第M個P型井區內的N+型摻雜區電性連接至第二連接端TM32,i為整數且1≦i≦(M-1)。It should be noted that the diode strings exemplified in the embodiment of FIG. 3 are formed by connecting three diodes D41 to D43 in series, but it is not intended to limit the present invention, and those skilled in the art may also rely on The design needs to change the number of components of the diode string. For example, the diode strings in the N-type deep well region 340 may be formed by connecting M diodes in series, and M is an integer greater than 1. At this time, M P-type well regions will be disposed in the N-type deep well area 340. In addition, in the electrical connection, the P+ type doped region in the first P-type well region is electrically connected to the N+-type doped region 372 in the N-type well region 330. The N+ type doped region in the i-th P-type well region is electrically connected to the P+-type doped region in the i+1th P-type well region, and the N+-type doped region in the Mth P-type well region Electrically connected to the second connection terminal TM32, i is an integer and 1≦i≦(M-1).

除此之外,倘若應用在低壓操作下,N型深井區340內的二極體串也可由單一個二極體所構成。此時,N型深井區340內將配置單一個P型井區。此外,針對N型深井區340內的單一個P型井區來看,其內部的P+型摻雜區電性連接至N型井區330內的N+型摻雜區372,且其內部的N+型摻雜區則電性連接至第二連接端TM32。In addition, if applied under low voltage operation, the diode string in the N-type deep well region 340 can also be composed of a single diode. At this time, a single P-type well zone will be disposed in the N-type deep well zone 340. In addition, for a single P-type well region in the N-type deep well region 340, the internal P+-type doped region is electrically connected to the N+-type doped region 372 in the N-type well region 330, and its internal N+ The doped region is electrically connected to the second connection terminal TM32.

綜上所述,本發明是將N型深井區設置在P型基底內,並在N型深井區設置由P型井區與N+型摻雜區所構成的二極體串。藉此,當靜電放電事件發生時,靜電放電保護元件將可利用N型深井區內的二極體串來觸發其內部的矽控整流電路,或是導通其內部的反向二極體。此外,當核心電路正常操作時,N型深井區將藉由元件的第一連接端連接至焊墊,進而偏壓在反向電壓下。如此一來,將可阻隔縱向漏電路徑的產生,進而抑制靜電放電保護元件之漏電流的產生。換言之,本發明之靜電放電保護元件同時具有PS模式與NS模式的靜電放電保護功能,並可應用在高速傳輸元件上。In summary, the present invention provides an N-type deep well region in a P-type substrate, and a diode string composed of a P-type well region and an N+-type doped region in the N-type deep well region. Thereby, when an electrostatic discharge event occurs, the electrostatic discharge protection component can use the diode string in the N-type deep well region to trigger the internal controlled rectifier circuit or turn on the internal reverse diode. In addition, when the core circuit is operating normally, the N-type deep well region will be connected to the pad by the first connection of the component, thereby biasing at the reverse voltage. In this way, the generation of the longitudinal leakage path can be blocked, thereby suppressing the generation of leakage current of the electrostatic discharge protection element. In other words, the electrostatic discharge protection element of the present invention has both an electrostatic discharge protection function of the PS mode and the NS mode, and can be applied to a high speed transmission element.

雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作些許之更動與潤飾,故本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100...二極體觸發矽控整流器100. . . Diode triggered voltage controlled rectifier

110、310...P型基底110, 310. . . P-type substrate

120、320、351~353...P型井區120, 320, 351~353. . . P type well area

131~134、330...N型井區131~134, 330. . . N type well area

141~146、361~366...P+型摻雜區141~146, 361~366. . . P+ doped region

151~155、371~376...N+型摻雜區151~155, 371~376. . . N+ doped region

GND1、GND3...接地配線GND1, GND3. . . Ground wiring

101、301...焊墊101, 301. . . Solder pad

102、302...核心電路102, 302. . . Core circuit

MP21~MP24、MP41~MP44...PNP電晶體MP21~MP24, MP41~MP44. . . PNP transistor

MN2、MN4...NPN電晶體MN2, MN4. . . NPN transistor

R2、R4...電阻R2, R4. . . resistance

D2、D41~D44...二極體D2, D41~D44. . . Dipole

300...靜電放電保護元件300. . . Electrostatic discharge protection component

TM31...第一連接端TM31. . . First connection

TM32...第二連接端TM32. . . Second connection

340...N型深井區340. . . N type deep well area

圖1為習知之二極體觸發矽控整流器的剖面圖。1 is a cross-sectional view of a conventional diode triggered chirp rectifier.

圖2為用以說明習知之二極體觸發矽控整流器的等效電路圖。2 is an equivalent circuit diagram for explaining a conventional diode-triggered voltage-controlled rectifier.

圖3為依據本發明之ㄧ實施例之靜電放電保護元件的剖面圖。Figure 3 is a cross-sectional view of an electrostatic discharge protection device in accordance with an embodiment of the present invention.

圖4為用以說明圖3之靜電放電保護元件的等效電路圖。4 is an equivalent circuit diagram for explaining the electrostatic discharge protection element of FIG. 3.

300...靜電放電保護元件300. . . Electrostatic discharge protection component

310...P型基底310. . . P-type substrate

320、351~353...P型井區320, 351~353. . . P type well area

330...N型井區330. . . N type well area

340...N型深井區340. . . N type deep well area

361~366...P+型摻雜區361~366. . . P+ doped region

371~376...N+型摻雜區371~376. . . N+ doped region

301...焊墊301. . . Solder pad

TM31...第一連接端TM31. . . First connection

TM32...第二連接端TM32. . . Second connection

GND3...接地配線GND3. . . Ground wiring

Claims (11)

一種靜電放電保護元件,具有一第一連接端與一第二連接端,並包括:
  一P型基底,具有一第一P型井區、一N型井區以及一N型深井區,其中該N型深井區電性連接該第一連接端,該P型基底電性連接該第二連接端;
  M個第二P型井區,配置於該N型深井區內,其中M為大於1的整數;
  多個第一P+型摻雜區,分別配置在該第一P型井區、該N型井區以及該些第二P型井區內;以及
  多個第一N+型摻雜區,分別配置在該第一P型井區、該N型井區以及該些第二P型井區內,且該些第一N+型摻雜區與該些第一P+型摻雜區交替配置。
An ESD protection component has a first connection end and a second connection end, and includes:
a P-type substrate having a first P-type well region, an N-type well region, and an N-type deep well region, wherein the N-type deep well region is electrically connected to the first connection end, and the P-type substrate is electrically connected to the first Two connection ends;
M second P-type well regions, disposed in the N-type deep well region, wherein M is an integer greater than 1;
a plurality of first P+ doping regions respectively disposed in the first P-type well region, the N-type well region, and the second P-type well regions; and a plurality of first N+-type doping regions respectively configured In the first P-type well region, the N-type well region, and the second P-type well regions, and the first N+-type doped regions are alternately arranged with the first P+-type doped regions.
如申請專利範圍第1項所述之靜電放電保護元件,其中位在該第一P型井區內的該第一P+型摻雜區與該第一N+型摻雜區電性連接至該第二連接端,位在該N型井區內的該第一P+型摻雜區與該第一N+型摻雜區分別電性連接至該第一連接端與第1個第二P型井區內的該第一P+型摻雜區,第i個第二P型井區內的該第一N+型摻雜區電性連接至第i+1個第二P型井區內的該第一P+型摻雜區,且第M個第二P型井區內的該第一N+型摻雜區電性連接至該第二連接端,i為整數且1≦i≦(M-1)。The electrostatic discharge protection device of claim 1, wherein the first P+ doped region and the first N+ doped region in the first P-type well region are electrically connected to the first a second connection end, the first P+ type doped region and the first N+ type doped region located in the N-type well region are electrically connected to the first connection end and the first second P-type well region, respectively The first P+ doping region in the first P+ well region is electrically connected to the first region in the i+1th second P-type well region a P+-type doped region, and the first N+-type doped region in the Mth second P-type well region is electrically connected to the second connection terminal, where i is an integer and 1≦i≦(M-1). 如申請專利範圍第1項所述之靜電放電保護元件,其中該N型井區位在該第一P型井區與該N型深井區之間,且該N型井區與該第一P型井區相接觸,該N型井區與該N型深井區互不接觸。The electrostatic discharge protection device of claim 1, wherein the N-type well location is between the first P-type well region and the N-type deep well region, and the N-type well region and the first P-type When the well area is in contact, the N-type well area and the N-type deep well area do not contact each other. 如申請專利範圍第1項所述之靜電放電保護元件,其中該些第二P型井區互不相連。The electrostatic discharge protection component of claim 1, wherein the second P-type well regions are not connected to each other. 如申請專利範圍第1項所述之靜電放電保護元件,更包括:
  一第二N+型摻雜區,配置在該N型深井區內,並相鄰於第M個第二P型井區,其中該N型深井區透過該第二N+型摻雜區電性連接該第一連接端。
The electrostatic discharge protection component of claim 1, further comprising:
a second N+ type doping region is disposed in the N-type deep well region adjacent to the Mth second P-type well region, wherein the N-type deep well region is electrically connected through the second N+-type doping region The first connection end.
如申請專利範圍第1項所述之靜電放電保護元件,更包括:
  一第二P+型摻雜區,配置於該P型基底內,並相鄰於該N型深井區,其中該P型基底透過該第二P+型摻雜區電性連接該第二連接端。
The electrostatic discharge protection component of claim 1, further comprising:
A second P+-type doped region is disposed in the P-type substrate adjacent to the N-type deep well region, wherein the P-type substrate is electrically connected to the second connection terminal through the second P+-type doped region.
一種靜電放電保護元件,具有一第一連接端與一第二連接端,並包括:
  一P型基底,具有一第一P型井區、一N型井區以及一N型深井區,其中該N型深井區電性連接該第一連接端,該P型基底電性連接該第二連接端;
  一第二P型井區,配置於該N型深井區內;
  多個第一P+型摻雜區,分別配置在該第一P型井區、該N型井區以及該第二P型井區內;以及
  多個第一N+型摻雜區,分別配置在該第一P型井區、該N型井區以及該第二P型井區內,且該些第一N+型摻雜區與該些第一P+型摻雜區交替配置。
An ESD protection component has a first connection end and a second connection end, and includes:
a P-type substrate having a first P-type well region, an N-type well region, and an N-type deep well region, wherein the N-type deep well region is electrically connected to the first connection end, and the P-type substrate is electrically connected to the first Two connection ends;
a second P-type well region disposed in the N-type deep well region;
a plurality of first P+ doped regions respectively disposed in the first P-type well region, the N-type well region and the second P-type well region; and a plurality of first N+-type doped regions respectively disposed at The first P-type well region, the N-type well region and the second P-type well region, and the first N+-type doped regions are alternately arranged with the first P+-type doped regions.
如申請專利範圍第7項所述之靜電放電保護元件,其中位在該第一P型井區內的該第一P+型摻雜區與該第一N+型摻雜區電性連接至該第二連接端,位在該N型井區內的該第一P+型摻雜區與該第一N+型摻雜區分別電性連接至該第一連接端與該第二P型井區中的該第一P+型摻雜區,且位在該第二P型井區內的該第一N+型摻雜區電性連接至該第二連接端。The electrostatic discharge protection device of claim 7, wherein the first P+ doping region and the first N+ doping region in the first P-type well region are electrically connected to the first The first P+ type doped region and the first N+ doped region located in the N-type well region are electrically connected to the first connection end and the second P-type well region respectively The first P+-type doped region, and the first N+-type doped region located in the second P-type well region is electrically connected to the second connection terminal. 如申請專利範圍第7項所述之靜電放電保護元件,其中該N型井區位在該第一P型井區與該N型深井區之間,且該N型井區與該第一P型井區相接觸,該N型井區與該N型深井區互不接觸。The electrostatic discharge protection device of claim 7, wherein the N-type well location is between the first P-type well region and the N-type deep well region, and the N-type well region and the first P-type When the well area is in contact, the N-type well area and the N-type deep well area do not contact each other. 如申請專利範圍第7項所述之靜電放電保護元件,更包括:
  一第二N+型摻雜區,配置在該N型深井區內,並相鄰於該第二P型井區,其中該N型深井區透過該第二N+型摻雜區電性連接該第一連接端。
The electrostatic discharge protection component of claim 7, further comprising:
a second N+-type doping region disposed in the N-type deep well region adjacent to the second P-type well region, wherein the N-type deep well region is electrically connected to the second N+-type doped region A connection.
如申請專利範圍第7項所述之靜電放電保護元件,更包括:
  一第二P+型摻雜區,配置於該P型基底內,並相鄰於該N型深井區,其中該P型基底透過該第二P+型摻雜區電性連接該第二連接端。
The electrostatic discharge protection component of claim 7, further comprising:
A second P+-type doped region is disposed in the P-type substrate adjacent to the N-type deep well region, wherein the P-type substrate is electrically connected to the second connection terminal through the second P+-type doped region.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI661530B (en) * 2018-02-13 2019-06-01 力晶積成電子製造股份有限公司 Electrostatic discharge protection device
CN111816650A (en) * 2019-04-12 2020-10-23 中芯国际集成电路制造(上海)有限公司 SCR electrostatic protection structure and forming method thereof

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI661530B (en) * 2018-02-13 2019-06-01 力晶積成電子製造股份有限公司 Electrostatic discharge protection device
US10361187B1 (en) 2018-02-13 2019-07-23 Powerchip Semiconductor Manufacturing Corporation Electrostatic discharge protection device
CN111816650A (en) * 2019-04-12 2020-10-23 中芯国际集成电路制造(上海)有限公司 SCR electrostatic protection structure and forming method thereof
CN111816650B (en) * 2019-04-12 2023-05-26 中芯国际集成电路制造(上海)有限公司 SCR electrostatic protection structure and forming method thereof

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