CN111812373A - PCIe mainboard signal automatic testing device - Google Patents
PCIe mainboard signal automatic testing device Download PDFInfo
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- CN111812373A CN111812373A CN202010598435.6A CN202010598435A CN111812373A CN 111812373 A CN111812373 A CN 111812373A CN 202010598435 A CN202010598435 A CN 202010598435A CN 111812373 A CN111812373 A CN 111812373A
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Abstract
The application discloses PCIe mainboard signal automatic testing arrangement includes: the controller is used for acquiring a control instruction and outputting a control signal for keeping a preset time period according to the control instruction; the clock generator is used for receiving the control signal and outputting a clock signal of the preset time period according to the control signal; the CLB is used for receiving the clock signal and sending the clock signal to a mainboard to be tested so that the mainboard to be tested switches the code pattern and the speed of a PCIe signal according to the clock signal and generates corresponding test data; and the oscilloscope is used for receiving the test data fed back by the mainboard to be tested. This application utilizes controller and clock generator automatic generation clock signal at the PCIe test process of the whole mainboard that awaits measuring, makes the mainboard automatic switch-over PCIe signal's that awaits measuring code pattern and speed, and efficiency of software testing obtains obvious promotion, has saved a large amount of manpowers and time cost.
Description
Technical Field
The invention relates to the field of hardware testing, in particular to a PCIe mainboard signal automatic testing device.
Background
With the increasing performance of CPUs at home and abroad, the CPU (Central Processing Unit) has more and more abundant external interfaces, the signal rate also increases, the PCIe (Peripheral component interconnect Express) interface to the outside of the CPU, the highest rate of the PCIe signal currently in mass production and practical has reached PCIe4.0 (i.e. GT/s), and the number of PCIe4.0 interfaces is also more and more, and the NVMe interface (which is also a PCIe signal) replaces the conventional SATA (Serial Advanced technology attachment) interface, so the utilization rate and number of PCIe are increased, which brings great challenges to PCIe signal integrity test work, the test workload of signal integrity engineers is increased in multiples, and more manpower and material resources need to be invested.
According to the conventional PCIe testing method, a worker manually switches the PCIe signal rate and the code pattern through a rate Switch Toggle Mode Switch, an oscilloscope captures a PCIe signal waveform file, the waveform file is analyzed by using a sigtest provided by a PCIe association, the steps are repeated, and finally the worker arranges all wavelike files of the code pattern to be tested into a test report. Because these actions require manual handling, labor and time costs are too high.
Therefore, how to provide a solution to the above technical problems is a problem to be solved by those skilled in the art.
Disclosure of Invention
In view of the above, an object of the present invention is to provide an automatic PCIe motherboard signal testing apparatus with high testing efficiency. The specific scheme is as follows:
an automatic test device for PCIe mainboard signals comprises:
the controller is used for acquiring a control instruction and outputting a control signal for keeping a preset time period according to the control instruction;
the clock generator is used for receiving the control signal and outputting a clock signal of the preset time period according to the control signal;
the CLB is used for receiving the clock signal and sending the clock signal to a mainboard to be tested so that the mainboard to be tested switches the code pattern and the speed of a PCIe signal according to the clock signal and generates corresponding test data;
and the oscilloscope is used for receiving the test data fed back by the mainboard to be tested.
Preferably, the controller is further configured to:
and acquiring a waveform file corresponding to the test data through an oscilloscope, and analyzing a test result according to the waveform file to generate a control instruction corresponding to the next code pattern.
Preferably, the controller is further configured to:
and when the test results corresponding to all the code patterns in the code pattern table are obtained, sorting all the test results and generating a test report of the mainboard to be tested.
Preferably, the process of generating the control instruction corresponding to the next code pattern by the controller according to the waveform file analysis test result specifically includes:
and judging whether the test of the current code pattern is finished or not according to the waveform file, and if so, analyzing the test result according to the waveform file to generate a control instruction corresponding to the next code pattern.
Preferably, the clock signal is a clock signal of 100MHz, and the preset time period is 1 ms.
Preferably, the controller outputs the control signal to the clock generator through an I2C bus.
Preferably, the process of receiving the clock signal and sending the clock signal to the motherboard to be tested by the CLB specifically includes:
and receiving the clock signal through Rx Lane0 and sending the clock signal to the mainboard to be tested.
Preferably, the controller includes:
the control unit is used for receiving the test data and generating the control instruction;
and the protocol conversion unit is used for converting the control instruction into the control signal conforming to the I2C protocol.
The application discloses PCIe mainboard signal automatic testing arrangement includes: the controller is used for acquiring a control instruction and outputting a control signal for keeping a preset time period according to the control instruction; the clock generator is used for receiving the control signal and outputting a clock signal of the preset time period according to the control signal; the CLB is used for receiving the clock signal and sending the clock signal to a mainboard to be tested so that the mainboard to be tested switches the code pattern and the speed of a PCIe signal according to the clock signal and generates corresponding test data; and the oscilloscope is used for receiving the test data fed back by the mainboard to be tested. This application does not need the staff to press mechanical switch Toggle model switch at the PCIe test procedure of the whole mainboard that awaits measuring, utilizes controller and clock generator automatic generation clock signal, makes the mainboard automatic switch-over PCIe signal's that awaits measuring the code pattern and speed, and efficiency of software testing obtains obvious promotion, has saved a large amount of manpowers and time cost.
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In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a structural distribution diagram of an automatic PCIe motherboard signal testing device according to an embodiment of the present invention;
fig. 2 is a structural distribution diagram of an exemplary PCIe motherboard signal automatic test apparatus according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
According to the conventional PCIe testing method, a worker manually switches the PCIe signal rate and the code pattern through a Toggle Mode Switch, an oscilloscope captures a PCIe signal waveform file, a sigtest analysis waveform file provided by a PCIe association is used, the steps are repeated, and finally the worker arranges all wavelike files of the code pattern to be tested into a test report. Because these actions require manual handling, labor and time costs are too high. According to the method and the device, the controller and the clock generator are used for automatically generating the clock signal, so that the code pattern and the speed of the PCIe signal of the mainboard to be tested are automatically switched, the test efficiency is obviously improved, and a large amount of manpower and time cost are saved.
The embodiment of the invention discloses a PCIe mainboard signal automatic testing device, which is shown in figure 1 and comprises:
the controller 1 is used for acquiring a control instruction and outputting a control signal for keeping a preset time period according to the control instruction;
the clock generator 2 is used for receiving the control signal and outputting a clock signal of a preset time period according to the control signal;
the CLB 3 is used for receiving the clock signal and sending the clock signal to the mainboard X to be tested so that the mainboard X to be tested can switch the code pattern and the speed of the PCIe signal according to the clock signal and generate corresponding test data;
and the oscilloscope 4 is used for receiving the test data fed back by the mainboard X to be tested.
Before testing, all units in the automatic PCIe mainboard signal testing device need to be connected with a mainboard X to be tested, and then the controller 1 is used for leading the PCIe test of the mainboard X to be tested.
Specifically, the controller 1 obtains a control instruction and outputs a corresponding control signal according to the control instruction, the clock generator 2 receives the control signal and outputs a clock signal according to the control signal, the CLB 3 (compatibility Load Board) receives the clock signal and sends the clock signal to the mainboard X to be tested, and the mainboard X to be tested switches the code type and the rate of the PCIe signal according to the clock signal, generates corresponding test data, and returns the test data to the oscilloscope 4.
Further, the controller 1 is further configured to:
and acquiring a waveform file corresponding to the test data through the oscilloscope 4, and analyzing the test result according to the waveform file to generate a control instruction corresponding to the next code pattern.
It can be understood that, in order to improve the test accuracy, the process of generating the control instruction corresponding to the next code pattern by the controller 1 according to the waveform file analysis test result specifically includes:
and judging whether the test of the current code pattern is finished according to the waveform file, if so, analyzing the test result according to the waveform file to generate a control instruction corresponding to the next code pattern.
That is to say, in the testing process of all the code patterns, the control instruction of the controller 1 is generated after the last code pattern is tested and the testing result is determined, so that the integrity of each code pattern test is ensured, and the occurrence of error and leakage is avoided.
It can be understood that, the controller 1 in the whole PCIe motherboard signal automatic test apparatus starts to conduct PCIe test on the to-be-tested motherboard X from the first code pattern after receiving the initial control instruction, and automatically generates a control instruction of the next code pattern after each code pattern completes the test, and sequentially loops until PCIe tests of all code patterns are completed.
The PCIe signal is generally referred to as a PCIe4.0 signal, and the code pattern and the corresponding rate of the PCIe4.0 signal are provided in the following table, see table 1.
TABLE 1 PCIe4.0 signals code pattern and rate to be tested
| Default | 2.5GT/ |
12 | 8GT/s(Preset 10) |
| 1 | 5GT/s(-3.5dB)mode | 13 | 16GT/s(Preset 0) |
| 2 | 5GT/s(-6dB)mode | 14 | 16GT/s(Preset 1) |
| 3 | 8GT/s(Preset 0)mode | 15 | 16GT/s(Preset 2) |
| 4 | 8GT/s(Preset 1)mode | 16 | 16GT/s(Preset 3)mode |
| 5 | 8GT/s(Preset 2)mode | 17 | 16GT/s(Preset 4)mode |
| 6 | 8GT/s(Preset 3)mode | 18 | 16GT/s(Preset 5)mode |
| 7 | 8GT/s(Preset 4)mode | 19 | 16GT/s(Preset 6)mode |
| 8 | 8GT/s(Preset 5)mode | 20 | 16GT/s(Preset 7)mode |
| 9 | 8GT/s(Preset 6)mode | 21 | 16GT/s(Preset 8)mode |
| 10 | 8GT/s(Preset 7)mode | 22 | 16GT/s(Preset 9) |
| 11 | 8GT/s(Preset 8)mode | 13 | 16GT/s(Preset 10) |
| 12 | 8GT/s(Preset 9)mode |
Of course, besides the code pattern and the rate provided in table 1, if the mainboard X to be tested has the code pattern and the rate of other parameters, the adjustment and the feedback can be performed according to the corresponding parameter table.
Further, the controller 1 is further configured to:
and when the test results corresponding to all the code patterns in the code pattern table are obtained, sorting all the test results and generating a test report of the mainboard X to be tested.
It can be understood that the controller 1 uses the program software written inside to complete the above-described actions of judging whether the test result is complete, analyzing the test result according to the volatility file, generating the control instruction of the next code pattern, sorting all the test results to generate the test report, etc., so as to replace the repeated and tedious manual operation and manual data analysis, and effectively improve the working efficiency. The controller 1 may be implemented as a separate component or may be implemented as a chip in the oscilloscope 4.
The application discloses PCIe mainboard signal automatic testing arrangement includes: the controller is used for acquiring a control instruction and outputting a control signal for keeping a preset time period according to the control instruction; the clock generator is used for receiving the control signal and outputting a clock signal of a preset time period according to the control signal; the CLB is used for receiving the clock signal and sending the clock signal to the mainboard to be tested so that the mainboard to be tested switches the code pattern and the speed of the PCIe signal according to the clock signal and generates corresponding test data; and the oscilloscope is used for receiving the test data fed back by the mainboard to be tested. This application does not need the staff to press mechanical Switch Toggle Mode Switch at the PCIe test procedure of the whole mainboard that awaits measuring, utilizes controller and clock generator automatic generation clock signal, makes the mainboard automatic Switch-over PCIe signal's that awaits measuring the code pattern and speed, and efficiency of software testing obtains obvious promotion, has saved a large amount of manpowers and time cost.
The embodiment of the invention discloses a specific PCIe mainboard signal automatic testing device, and compared with the previous embodiment, the embodiment further explains and optimizes the technical scheme. Specifically, see fig. 2 for a description of:
the clock signal is specifically a 100MHz clock signal, and the preset time period is 1 ms.
In a specific implementation, the controller 1 outputs a control signal to the clock generator 2 via the I2C bus.
Thus, the controller 1 includes:
the control unit 11 is used for receiving the test data and generating a control instruction;
and the protocol conversion unit 12 is used for converting the control instruction into a control signal conforming to the I2C protocol.
It will be appreciated that the control commands are typically selected to correspond to the USB protocol, whereas the clock generator 2 corresponds to the I2C protocol, thus requiring the protocol conversion unit 12 to convert the control protocol to control signals conforming to the I2C protocol. Further, the protocol conversion unit 12 may be implemented by hardware such as a single chip.
Further, the process of receiving the clock signal and sending the clock signal to the motherboard X to be tested by the CLB 3 specifically includes:
the clock signal is received by Rx Lane0 and sent to the motherboard X to be tested.
It can be understood that Rx Lane0 is used as a physical signal interface between the remaining boards to be tested X of CLB 3 to implement signal transmission.
In addition, it can be seen in fig. 2 that another signal line connection is formed between the CLB 3 and the oscilloscope 4, so as to complete the transmission of the PCIe differential reference clock signal.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The PCIe motherboard signal automatic testing apparatus provided by the present invention is described in detail above, and a specific example is applied in this document to explain the principle and the implementation of the present invention, and the description of the above embodiment is only used to help understanding the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (8)
1. The utility model provides a PCIe mainboard signal automatic testing arrangement which characterized in that includes:
the controller is used for acquiring a control instruction and outputting a control signal for keeping a preset time period according to the control instruction;
the clock generator is used for receiving the control signal and outputting a clock signal of the preset time period according to the control signal;
the CLB is used for receiving the clock signal and sending the clock signal to a mainboard to be tested so that the mainboard to be tested switches the code pattern and the speed of a PCIe signal according to the clock signal and generates corresponding test data;
and the oscilloscope is used for receiving the test data fed back by the mainboard to be tested.
2. The PCIe motherboard signal automatic test apparatus of claim 1, wherein the controller is further configured to:
and acquiring a waveform file corresponding to the test data through an oscilloscope, and analyzing a test result according to the waveform file to generate a control instruction corresponding to the next code pattern.
3. The PCIe motherboard signal automatic test apparatus of claim 2, wherein the controller is further configured to:
and when the test results corresponding to all the code patterns in the code pattern table are obtained, sorting all the test results and generating a test report of the mainboard to be tested.
4. The PCIe motherboard signal automatic test apparatus according to claim 3, wherein the process of generating the control instruction corresponding to the next code pattern by the controller according to the waveform file analysis test result specifically includes:
and judging whether the test of the current code pattern is finished or not according to the waveform file, and if so, analyzing the test result according to the waveform file to generate a control instruction corresponding to the next code pattern.
5. The PCIe motherboard signal automatic test device according to any one of claims 1 to 4, wherein the clock signal is specifically a 100MHz clock signal, and the predetermined time period is 1 ms.
6. The PCIe motherboard signal automatic test device of claim 5, wherein the controller outputs the control signal to the clock generator through an I2C bus.
7. The PCIe motherboard signal automatic test apparatus according to claim 6, wherein the process of the CLB receiving the clock signal and sending it to the motherboard to be tested specifically comprises:
and receiving the clock signal through Rx Lane0 and sending the clock signal to the mainboard to be tested.
8. The PCIe motherboard signal automatic test apparatus of claim 7, wherein the controller comprises:
the control unit is used for receiving the test data and generating the control instruction;
and the protocol conversion unit is used for converting the control instruction into the control signal conforming to the I2C protocol.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113190387A (en) * | 2021-04-13 | 2021-07-30 | 山东英信计算机技术有限公司 | Compensation code type switching method and trigger equipment |
| CN113204452A (en) * | 2021-04-23 | 2021-08-03 | 山东英信计算机技术有限公司 | Method, system and medium for measuring high-speed signal |
| CN113295946A (en) * | 2021-05-11 | 2021-08-24 | 深圳市精泰达科技有限公司 | PCIe test fixture code pattern automatic switching method and device thereof |
| CN114116359A (en) * | 2021-12-03 | 2022-03-01 | 苏州浪潮智能科技有限公司 | PCIe chip signal testing device and method |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105045697A (en) * | 2015-06-24 | 2015-11-11 | 浪潮电子信息产业股份有限公司 | Test system and method for PCIE signal integrity |
| CN105699788A (en) * | 2016-04-27 | 2016-06-22 | 浪潮电子信息产业股份有限公司 | Power supply time sequence measurement method, oscilloscope and system thereof |
| CN105743737A (en) * | 2016-02-03 | 2016-07-06 | 浪潮(北京)电子信息产业有限公司 | Non-standard PCIe3.0 interface test method and system |
| CN107844393A (en) * | 2017-11-10 | 2018-03-27 | 郑州云海信息技术有限公司 | A kind of rate switching method of M.2 PCIe measurement jigs |
| CN108153630A (en) * | 2017-12-21 | 2018-06-12 | 曙光信息产业股份有限公司 | A kind of signal-testing apparatus |
| CN109828872A (en) * | 2018-12-28 | 2019-05-31 | 曙光信息产业(北京)有限公司 | Signal-testing apparatus and method |
| CN110515788A (en) * | 2019-09-29 | 2019-11-29 | 浪潮商用机器有限公司 | A kind of test device of data-interface |
-
2020
- 2020-06-28 CN CN202010598435.6A patent/CN111812373A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105045697A (en) * | 2015-06-24 | 2015-11-11 | 浪潮电子信息产业股份有限公司 | Test system and method for PCIE signal integrity |
| CN105743737A (en) * | 2016-02-03 | 2016-07-06 | 浪潮(北京)电子信息产业有限公司 | Non-standard PCIe3.0 interface test method and system |
| CN105699788A (en) * | 2016-04-27 | 2016-06-22 | 浪潮电子信息产业股份有限公司 | Power supply time sequence measurement method, oscilloscope and system thereof |
| CN107844393A (en) * | 2017-11-10 | 2018-03-27 | 郑州云海信息技术有限公司 | A kind of rate switching method of M.2 PCIe measurement jigs |
| CN108153630A (en) * | 2017-12-21 | 2018-06-12 | 曙光信息产业股份有限公司 | A kind of signal-testing apparatus |
| CN109828872A (en) * | 2018-12-28 | 2019-05-31 | 曙光信息产业(北京)有限公司 | Signal-testing apparatus and method |
| CN110515788A (en) * | 2019-09-29 | 2019-11-29 | 浪潮商用机器有限公司 | A kind of test device of data-interface |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113190387A (en) * | 2021-04-13 | 2021-07-30 | 山东英信计算机技术有限公司 | Compensation code type switching method and trigger equipment |
| CN113204452A (en) * | 2021-04-23 | 2021-08-03 | 山东英信计算机技术有限公司 | Method, system and medium for measuring high-speed signal |
| CN113204452B (en) * | 2021-04-23 | 2023-01-10 | 山东英信计算机技术有限公司 | Method, system and medium for measuring high-speed signal |
| CN113295946A (en) * | 2021-05-11 | 2021-08-24 | 深圳市精泰达科技有限公司 | PCIe test fixture code pattern automatic switching method and device thereof |
| CN114116359A (en) * | 2021-12-03 | 2022-03-01 | 苏州浪潮智能科技有限公司 | PCIe chip signal testing device and method |
| CN114116359B (en) * | 2021-12-03 | 2023-11-03 | 苏州浪潮智能科技有限公司 | PCIe chip signal testing device and method |
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