CN206378769U - A kind of test chart of multiplex roles - Google Patents

A kind of test chart of multiplex roles Download PDF

Info

Publication number
CN206378769U
CN206378769U CN201621327796.2U CN201621327796U CN206378769U CN 206378769 U CN206378769 U CN 206378769U CN 201621327796 U CN201621327796 U CN 201621327796U CN 206378769 U CN206378769 U CN 206378769U
Authority
CN
China
Prior art keywords
test
module
modules
test chart
ethernet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201621327796.2U
Other languages
Chinese (zh)
Inventor
孙骥
高策
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Faith Information Science & Technology Co Ltd
Original Assignee
Shanghai Faith Information Science & Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Faith Information Science & Technology Co Ltd filed Critical Shanghai Faith Information Science & Technology Co Ltd
Priority to CN201621327796.2U priority Critical patent/CN206378769U/en
Application granted granted Critical
Publication of CN206378769U publication Critical patent/CN206378769U/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Landscapes

  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

The utility model discloses a kind of test chart of multiplex roles, including FPGA module, MCU module, JTAG modules, USB module and ethernet test module, the FPGA module connects MCU module, two JTAG modules, two USB modules, ethernet test module, two DB9 modules, J3 interfaces and DB25 modules respectively.The utility model supports the test of multiple interfaces, and test operation can be operated by PC end main frames interface by network, it is convenient and swift, and it can be directed to due to various single function debugging board required for debugging, testing to board in engineering, the low caused waste of production cost and test board utilization rate caused, greatlys save cost and the versatility of test chart.

Description

A kind of test chart of multiplex roles
Technical field
The utility model is related to a kind of test chart, specifically a kind of test chart of multiplex roles.
Background technology
As Informatization Development is more and more rapider, the board of data processing used in everyday and data control is more and more, Integrated level and complexity more and more higher, the interface being accordingly related to are also more and more, then the adjustment method and equipment of board interface, Just turn into concerned point.Because the involved bus protocol of board debugging at this stage and complex interfaces are various, adjusted existing Try in equipment, it is single that the method for testing typically used has a function, workload is big, and efficiency is low, or cost it is high the shortcomings of, it is unfavorable In board testing efficiency and cost control.
The content of the invention
The purpose of this utility model is to provide a kind of test chart of multiplex roles, to solve what is proposed in above-mentioned background technology Problem.
To achieve the above object, the utility model provides following technical scheme:
A kind of test chart of multiplex roles, including FPGA module, MCU module, JTAG modules, USB module and ethernet test Module, the FPGA module connect respectively MCU module, two JTAG modules, two USB modules, ethernet test module, two DB9 modules, J3 interfaces and DB25 modules.
It is used as the utility model further scheme:The ethernet test module includes RJ45 modules and 8 row's pins.
Compared with prior art, the beneficial effects of the utility model are:The utility model supports the test of multiple interfaces, and Test operation can be operated by PC end main frames interface by network, convenient and swift, and can be directed to due to right in engineering Various single function debugging board required for board debugging, test, the production cost caused and test board utilization rate are low Caused waste, greatlys save cost and the versatility of test chart.
Brief description of the drawings
Fig. 1 is the structural representation of the test chart of multiplex roles.
Embodiment
Below in conjunction with the accompanying drawing in the utility model embodiment, the technical scheme in the utility model embodiment is carried out Clearly and completely describe.
Referring to Fig. 1, in the utility model embodiment, FPGA module is set by logic, make each debugging interface, pass through PC sends certain order, can connect, so as to realize multiplex roles, also serial ports is identical, enables commissioning staff from PC On, can be with the test chart of this multiplex roles come the signal data of the various interfaces of test board by certain operation.Ethernet is surveyed Die trial block, will coordinate oscillograph to carry out test ethernet signal quality, including eye pattern etc..
The utility model test chart debugging flow is as follows:First, determine that what the interfaces to be debugged of DUT are, it is determined that afterwards, Prepare corresponding software, other equipment etc., during such as test Ethernet, to coordinate software of giving out a contract for a project, ethernet line on PC and show Ripple device(Software comprising ethernet test);Secondly, the test chart power-on self-tests of multiplex roles it is complete it is out of question after, by DUT and tune The corresponding interface of examination card is connected;Finally, PC is connected by the serial ports of the test chart with multiplex roles, and commissioning staff passes through serial ports Send command data on the test chart of multiplex roles, get through the data link of serial ports and the interface to be tested on FPGA.So Corresponding test command or the packet of test etc. can be just sent by PC, corresponding interface is tested.
It is obvious to a person skilled in the art that the utility model is not limited to the details of above-mentioned one exemplary embodiment, and And in the case of without departing substantially from spirit or essential attributes of the present utility model, can realize that this practicality is new in other specific forms Type.Therefore, no matter from the point of view of which point, embodiment all should be regarded as exemplary, and is nonrestrictive, this practicality is new The scope of type limits by appended claims rather than described above, it is intended that the equivalency fallen in claim is contained All changes in justice and scope are included in the utility model.Any reference in claim should not be considered as limitation Involved claim.
Moreover, it will be appreciated that although the present specification is described in terms of embodiments, not each embodiment is only wrapped Containing an independent technical scheme, this narrating mode of specification is only that for clarity, those skilled in the art should Using specification as an entirety, the technical solutions in the various embodiments may also be suitably combined, forms those skilled in the art It may be appreciated other embodiment.

Claims (2)

1. a kind of test chart of multiplex roles, including FPGA module, MCU module, JTAG modules, USB module and ethernet test mould Block, it is characterised in that the FPGA module connects MCU module, two JTAG modules, two USB modules, ethernet tests respectively Module, two DB9 modules, J3 interfaces and DB25 modules.
2. the test chart of multiplex roles according to claim 1, it is characterised in that the ethernet test module includes RJ45 Module and 8 row's pins.
CN201621327796.2U 2016-12-06 2016-12-06 A kind of test chart of multiplex roles Active CN206378769U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201621327796.2U CN206378769U (en) 2016-12-06 2016-12-06 A kind of test chart of multiplex roles

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201621327796.2U CN206378769U (en) 2016-12-06 2016-12-06 A kind of test chart of multiplex roles

Publications (1)

Publication Number Publication Date
CN206378769U true CN206378769U (en) 2017-08-04

Family

ID=59405369

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201621327796.2U Active CN206378769U (en) 2016-12-06 2016-12-06 A kind of test chart of multiplex roles

Country Status (1)

Country Link
CN (1) CN206378769U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108874706A (en) * 2018-06-01 2018-11-23 国网安徽省电力有限公司阜阳供电公司 A kind of multifunctional printing conversion equipment

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108874706A (en) * 2018-06-01 2018-11-23 国网安徽省电力有限公司阜阳供电公司 A kind of multifunctional printing conversion equipment

Similar Documents

Publication Publication Date Title
CN105738854B (en) The analog memory test board system and test method of intelligent electric meter Embedded Application
CN201812014U (en) Automatic open-circuit and short-circuit testing system for integrated circuits
CN109799806A (en) Simulation test method and system for valve control device
CN105486999A (en) Boundary scanning digital circuit test system based on PXI bus and test method thereof
CN105357070A (en) FPGA-based ARINC818 bus analysis and test apparatus
CN104656632A (en) Integrated interface test system and detection method for aircraft semi-physical simulation tests
CN103376340B (en) A kind of keyset, multi-platform serial test system and method
CN103761185B (en) A kind of automatization test system and method
CN103678062A (en) Comprehensive test system and test method
CN108847869A (en) Portable multifunctional electric power analog channel test device and its test method
CN106681313A (en) Function testing method of dynamic stability control system and dynamic stability control system
CN112182837A (en) Multi-core SoC software and hardware collaborative verification platform special for relay protection based on FPGA
CN105320510B (en) A kind of method and device of automatic tracing data relationship
CN206378769U (en) A kind of test chart of multiplex roles
WO2016184170A1 (en) Smi interface device debugging apparatus and method, and storage medium
CN205540248U (en) Detection apparatus for vehicle control unit
CN205092934U (en) DP data line capability test appearance
CN112114899A (en) Chip debugging system and debugger
CN108255145A (en) A kind of test system and method for system of vehicle transmission control unit
CN204347152U (en) A kind of Multi-bus circuit board test diagnosis system
CN110988528A (en) Method, device and system for testing product signal integrity
CN105656718A (en) Stable automatic testing method for switch
CN207133813U (en) A kind of wireless emulator systems suitable for ARM chips
CN201114167Y (en) Dynamically reconfigurable multipath serial interface connector
CN207624231U (en) Mobile embedded teaching experiment system

Legal Events

Date Code Title Description
GR01 Patent grant
GR01 Patent grant