CN111799218A - Method for dividing wafer - Google Patents

Method for dividing wafer Download PDF

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Publication number
CN111799218A
CN111799218A CN202010194654.8A CN202010194654A CN111799218A CN 111799218 A CN111799218 A CN 111799218A CN 202010194654 A CN202010194654 A CN 202010194654A CN 111799218 A CN111799218 A CN 111799218A
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CN
China
Prior art keywords
wafer
front surface
dividing
polishing
chips
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202010194654.8A
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Chinese (zh)
Inventor
井上雄贵
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Disco Corp
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Disco Corp
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Filing date
Publication date
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Publication of CN111799218A publication Critical patent/CN111799218A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
    • H01L21/02065—Cleaning during device manufacture during, before or after processing of insulating layers the processing being a planarization of insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02076—Cleaning after the substrates have been singulated
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02082—Cleaning product to be cleaned
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H01L21/3043—Making grooves, e.g. cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Dicing (AREA)
  • Cleaning Or Drying Semiconductors (AREA)
  • Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)

Abstract

Provided is a wafer dividing method for satisfactorily removing machining chips from the front surface of a wafer. After the wafer (W) is divided in the dividing step to obtain the chips (C1), the front surfaces (2a) of the chips (C1) are polished in the polishing step. This enables the machining chips adhering to or welded to the front surface (2a) of the chip (C1) to be removed satisfactorily. Therefore, the yield of the chip (C1) can be improved. In the present embodiment, the front surface (2a) of the chip (C1) is subjected to CMP polishing using a slurry in the polishing step. Such CMP polishing is performed on the front surface (i.e., front surface (2a)) of the device (4) when the wafer (W) is manufactured. Therefore, the front surface (2a) of the chip (C1) can be prevented from being degraded in the polishing step.

Description

Method for dividing wafer
Technical Field
The present invention relates to a wafer dividing method.
Background
In a semiconductor wafer, devices are arranged in regions on the front surface of the wafer divided by predetermined dividing lines in a lattice shape. By dividing the wafer along the dividing lines, chips including devices can be obtained. Such wafer division is performed by cutting a cutting tool along a line to be divided or by ablating the wafer by irradiating a laser beam along the line to be divided.
When the wafer is divided as described above, the processing chips may adhere to the front surface of the wafer near the notch as the processing groove. Therefore, in the cutting process using the cutting tool, as described in patent documents 1 and 2, it is proposed to perform high-pressure cleaning during or after the cutting process. In the ablation process using a laser beam, as described in patent document 3, it is proposed to protect the front surface with a protective film.
Patent document 1: japanese laid-open patent publication No. 2010-046726
Patent document 2: japanese patent laid-open No. 2006-187834
Patent document 3: japanese patent laid-open publication No. 2006-140311
However, when the machining chips are welded to the front surface of the wafer by the machining heat or the like, the machining chips may remain on the front surface of the wafer even if cleaning is performed after the dividing process.
Disclosure of Invention
The invention aims to provide a wafer dividing method, which can well remove processing scraps from the front surface of a wafer after dividing processing.
A wafer dividing method (the dividing method) of the present invention is a wafer dividing method for dividing a wafer, in which devices are formed in respective regions of a front surface divided by planned dividing lines, along the planned dividing lines, the wafer dividing method including the steps of: a dividing step of dividing the wafer, which is bonded with a dicing tape on the back surface and held by a chuck table via the dicing tape, along the lines to be divided, thereby forming a plurality of chips including the device; a polishing step of polishing the front surfaces of the plurality of chips with a polishing pad to remove the machining chips after the dividing step; and a cleaning step of supplying cleaning water to the front side of the chip after the grinding step, thereby cleaning the chip.
In the dividing method, after the wafer is divided into chips in the dividing step, the front surfaces of the chips are polished in the polishing step. This enables the machining chips adhering to or welded to the front surface of the chip to be removed satisfactorily. Therefore, the yield in relation to chip manufacturing can be improved.
Drawings
Fig. 1 is a perspective view showing a wafer.
Fig. 2 is an explanatory diagram showing a workpiece group including wafers.
Fig. 3 is a sectional view showing the dividing process.
Fig. 4 is a sectional view showing a grinding process.
Fig. 5 is a sectional view showing a cleaning process.
Description of the reference symbols
WS: a workpiece group; f: an annular frame; t: scribing a tape; w: a wafer; 2 a: a front side; 2 b: a back side; 3: dividing the predetermined line; 4: a device; c1: a chip; 30: a cutting device; 40: a grinding device; 50: the cleaning device is rotated.
Detailed Description
In the method for dividing a wafer according to the present embodiment, a wafer W as shown in fig. 1 is used. As shown in fig. 1, the wafer W is a disk-shaped silicon substrate having a front surface 2a as a front surface and a back surface 2b as a back surface. On the front surface 2a of the wafer W, devices 4 are formed in respective regions defined by the plurality of lines to divide 3 in a lattice shape.
In addition, the devices 4 are formed on the front surface 2a of the wafer W. The front side 2a is thus also the front side of the device 4. The front surface 2a is also the front surface of the chip obtained by dividing the wafer W. Therefore, the expressions "front surface 2a of device 4" and "front surface 2a of chip" may be used hereinafter.
The wafer W together with the ring frame F and the dicing tape T form a workpiece group WS shown in fig. 2.
In forming the work set WS, first, the center of the ring frame F is aligned with the center of the wafer W in the opening of the ring frame F having an opening, and the front surface 2a of the wafer W is disposed facing downward. Next, the adhesive surface of the circular dicing tape T is stuck to the ring frame F and the back surface 2b of the wafer W, and the opening of the ring frame F is sealed to form a work group WS for supporting the wafer W on the ring frame F via the dicing tape T. In the work set WS, the front surface 2a of the wafer W is exposed.
Next, the operation of the present embodiment will be explained.
[ dividing Process ]
In this step, the wafer W in the tool group WS is divided along the lines to divide 3, thereby forming a plurality of chips including devices.
In this step, as shown in fig. 3, a workpiece group WS including a wafer W is set on a cutting apparatus 30 having a first chuck table 31 and a cutting section 33.
The first chuck table 31 has a first holding surface 32 made of a porous material or the like that can communicate with a suction source, not shown.
In the dividing step, as shown in fig. 3, the back surface 2b of the wafer W is sucked and held on the first holding surface 32 via the dicing tape T. The ring frame F is held by a not-shown clamp. Thereby, the wafer W is fixed to the first chuck table 31 with the front surface 2a exposed upward.
The cutting portion 33 of the cutting device 30 includes: a first main shaft 34 having a rotation axis in a horizontal direction; and a cutting tool 35 rotatable together with the first spindle 34.
In the cutting step, the first spindle 34 rotates in the direction of arrow B, and the cutting portion 33 moves downward. Further, the first chuck table 31 holding the wafer W moves in a direction perpendicular to the rotation axis of the first spindle 34 in the horizontal plane.
Thereby, the cutting tool 35 cuts the wafer W along the lines to divide 3 provided between the devices 4 on the front surface 2a of the wafer W.
As a result, the wafer W is divided into the plurality of chips C1, and the front surface 2a of the wafer W becomes the front surface 2a of the chip C1. In addition, the chips C1 each have one device 4 on the front side 2 a.
[ polishing Process ]
In this step, the front surface 2a of the plurality of chips C1 is polished by the polishing pad, thereby removing the machining chips from the front surface 2 a.
In this step, as shown in fig. 4, the wafer W divided into the plurality of chips C1 is removed from the cutting apparatus 30 and set on the polishing apparatus 40 while holding the work group WS integrated with the ring frame F and the dicing tape T.
The polishing apparatus 40 includes a second chuck table 41 and a polishing unit 43. The second chuck table 41 has a second holding surface 42 made of a porous material or the like that can communicate with a suction source, not shown.
In the polishing step, as shown in fig. 4, the back surface 2b of the wafer W is sucked and held on the second holding surface 42 via the dicing tape T, in the same manner as in the dividing step. The ring frame F is held by a not-shown clamp. Thereby, the wafer W is fixed to the second chuck table 41 with the front surface 2a exposed upward.
The polishing unit 43 of the polishing apparatus 40 includes a second spindle 44 and a polishing plate 45 rotatable together with the second spindle 44. A flat polishing pad 46 is disposed on the bottom surface of the polishing plate 45.
In the polishing step, the 2 nd chuck table 41 is rotated in the direction of arrow C, for example. Further, the polishing plate 45 of the polishing section 43 descends while rotating in the direction of arrow C. Then, the polishing pad 46 polishes the front surface 2a of the wafer W, i.e., the front surfaces 2a of the chips C1, while pressing them.
During polishing with the polishing pad 46, the slurry is supplied between the front surface 2a of the chip C1 and the polishing pad 46 through the slurry supply path 44a in the second spindle 44.
Therefore, a through hole penetrating the center of the polishing plate 45 and the polishing pad 46 is formed, and the slurry passing through the slurry supply path 44a is supplied between the front surface 2a of the chip C1 and the polishing pad 46 through the through hole.
In addition, in supplying the slurry, the slurry may not pass through the second main shaft 44. In the case where the area of the polishing pad 46 during polishing is smaller than the area of the wafer W, or in the case where the polishing pad 46 does not cover the entire front surface 2a of the wafer W, the exposed front surface 2a of the wafer W is not covered with the polishing pad 46, and thus the slurry can be supplied.
When the polishing pad 46 is brought into contact with the front surface 2a of the wafer W and protrudes from the front surface 2a of the wafer W, the slurry may be supplied to the polishing surface of the polishing pad 46.
The slurry supplied in the past may be retained on the dicing tape T between the outer periphery of the wafer W and the inner periphery of the ring frame, or the slurry retained on the polishing surface may be supplied.
By such polishing, the machining chips such as the chips and the chips attached or welded in the previous step are removed from the front surface 2a of the chip C1. The polishing removal amount is, for example, in the range of 3nm to 5 nm.
[ cleaning Process ]
In this step, the chip C1 is washed by supplying washing water to the front surface 2a side of the chip C1.
In this step, as shown in fig. 5, after the front surface 2a is polished, the wafer W including the plurality of chips C1 is removed from the polishing apparatus 40 and set on the spin cleaning apparatus 50 while maintaining the state of the work group WS integrated with the ring frame F and the dicing tape T.
The spin cleaning apparatus 50 includes a turntable 51 and a spin cleaning unit 53. The turntable 51 has a third holding surface 52 made of a porous material or the like that can communicate with a suction source not shown.
In the cleaning step, as shown in fig. 5, the back surface 2b of the wafer W is sucked and held on the third holding surface 52 via the dicing tape T, similarly to the polishing step and the like. The ring frame F is held by a not-shown clamp. Thereby, the wafer W is fixed to the turntable 51 with the front surface 2a exposed upward.
The rotary cleaning unit 53 of the rotary cleaning device 50 includes a cleaning nozzle 54 and a horizontal movement mechanism 55 for moving the cleaning nozzle 54 in the horizontal direction.
The horizontal movement mechanism 55 has a shaft 56 extending in the horizontal direction and a support member 57 supporting the washing nozzle 54. The support member 57 is movable in the horizontal direction along the shaft 56 in a state of supporting (holding) the washing nozzle 54. Further, a water supply source 58 and an air supply source 59 are connected to the cleaning nozzle 54.
In the cleaning step, the turntable 51 is rotated in the direction of arrow D, for example. Further, the cleaning nozzle 54 disposed above the wafer W is moved in the horizontal direction by the support member 57 as indicated by an arrow E.
At this time, two-fluid cleaning water, which is a mixture of water supplied from the water supply source 58 and air supplied from the air supply source 59, is ejected from the cleaning nozzle 54.
In this way, the two-fluid cleaning water is sprayed to the front surface 2a of substantially all of the chips C1 of the wafer W, and the chips C1 are cleaned.
In the cleaning step, the cleaning member may be brought into contact with the front surface of the wafer W to clean the wafer W. As the cleaning member, a brush or a soft sponge is used. By bringing the cleaning member into contact with the front surface of the wafer W, the time for removing the slurry adhering to the front surface 2a of the wafer W can be shortened. In addition, the chips C1 can be prevented from being separated from the dicing tape T and scattered during cleaning.
In addition, as the brush, a scrub brush may be used.
As described above, in the present embodiment, after the wafer W is divided in the dividing step to obtain the chips C1, the front surfaces 2a of the chips C1 are polished in the polishing step. This enables the machining chips adhering to or welded to the front surface 2a to be removed satisfactorily. Therefore, the yield in relation to the manufacture of the chip C1 can be improved.
In the present embodiment, in the polishing step, CMP (chemical mechanical polishing) polishing using a slurry is performed on the front surface 2a of the chip C1. Such CMP polishing is polishing performed on the front surface (i.e., the front surface 2a) of the device 4 when the wafer W is manufactured. Therefore, the front surface 2a can be suppressed from being deteriorated in the polishing step.

Claims (1)

1. A wafer dividing method for dividing a wafer having devices formed in regions of a front surface divided by dividing lines along the dividing lines,
the wafer dividing method includes the following steps:
a dividing step of dividing the wafer, which is bonded with a dicing tape on the back surface and held by a chuck table via the dicing tape, along the lines to be divided, thereby forming a plurality of chips including the device;
a polishing step of polishing the front surfaces of the plurality of chips with a polishing pad to remove the machining chips after the dividing step; and
a cleaning process of supplying cleaning water to the front side of the chip after the grinding process, thereby cleaning the chip.
CN202010194654.8A 2019-04-01 2020-03-19 Method for dividing wafer Pending CN111799218A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2019069838A JP7327974B2 (en) 2019-04-01 2019-04-01 Wafer division method
JP2019-069838 2019-04-01

Publications (1)

Publication Number Publication Date
CN111799218A true CN111799218A (en) 2020-10-20

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CN202010194654.8A Pending CN111799218A (en) 2019-04-01 2020-03-19 Method for dividing wafer

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JP (1) JP7327974B2 (en)
KR (1) KR20200116424A (en)
CN (1) CN111799218A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115206810A (en) * 2022-08-04 2022-10-18 马鞍山杰生半导体有限公司 Method for manufacturing light emitting device and light emitting device

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003059865A (en) 2001-08-20 2003-02-28 Towa Corp Cutting device and cutting method
JP2005039088A (en) 2003-07-16 2005-02-10 Sanyo Electric Co Ltd Cutting method, cutter and process for manufacturing semiconductor device
JP4571850B2 (en) 2004-11-12 2010-10-27 東京応化工業株式会社 Protective film agent for laser dicing and wafer processing method using the protective film agent
JP2006187834A (en) 2005-01-06 2006-07-20 Disco Abrasive Syst Ltd Cutting device
JP2006339373A (en) 2005-06-01 2006-12-14 Tokyo Seimitsu Co Ltd Groove forming method
JP5399662B2 (en) 2008-08-19 2014-01-29 株式会社ディスコ Cutting equipment
JP2015109348A (en) 2013-12-04 2015-06-11 株式会社ディスコ Processing method of wafer
JP2015126022A (en) 2013-12-25 2015-07-06 株式会社ディスコ Processing method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115206810A (en) * 2022-08-04 2022-10-18 马鞍山杰生半导体有限公司 Method for manufacturing light emitting device and light emitting device

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JP7327974B2 (en) 2023-08-16
KR20200116424A (en) 2020-10-12
JP2020170741A (en) 2020-10-15

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