CN111781986A - Current mirror, current copying method and electronic equipment - Google Patents
Current mirror, current copying method and electronic equipment Download PDFInfo
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- CN111781986A CN111781986A CN202010526587.5A CN202010526587A CN111781986A CN 111781986 A CN111781986 A CN 111781986A CN 202010526587 A CN202010526587 A CN 202010526587A CN 111781986 A CN111781986 A CN 111781986A
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- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
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Abstract
The invention discloses a current mirror, a current copying method and electronic equipment, wherein the current mirror comprises a first transistor, a source electrode is grounded, and a drain electrode is connected with a grid electrode and a current input end; a plurality of second transistors, wherein the drains are all connected to the current output end through the same connecting node, the sources are all grounded, the grids are all connected with the grid of the first transistor, and a selection switch is arranged between the drains and the connecting node; the control branch circuit is used for sequentially controlling the conduction of the equal but non-repeated selection switches at different moments so as to enable the current output end to output the average value of the currents at different moments on the connection node; the first transistor and the second transistor are first type transistors or second type transistors with equal threshold voltages, the width-length ratio of the second transistor and the width-length ratio of the first transistor are both approximately equal to a preset current ratio, and the first type and the second type are opposite. The invention can reduce the adverse effect of mismatching on the output current, so that the output current can accurately copy the input current according to the preset current ratio.
Description
Technical Field
The invention relates to the technical field of circuit design, in particular to a current mirror, a current copying method and electronic equipment.
Background
A current mirror is a commonly used current replica device and is widely used in integrated circuits. The current mirror receives an input current through a current input end thereof and outputs an output current through a current output end thereof, wherein the output current is a current obtained by copying the input current.
Fig. 1 shows a schematic circuit diagram of a current mirror in the prior art. Referring to fig. 1, the current mirror includes: a first transistor 100 and a second transistor 200, wherein the first transistor 100 and the second transistor 200 are both N-type MOSFETs with equal threshold voltages; the drain of the first transistor 100 is connected to the current input terminal and the gate of the first transistor 100, and the source of the first transistor 100 is grounded; the gate of the second transistor 200 is connected to the gate of the first transistor 100, the source of the second transistor 200 is grounded, and the drain of the second transistor 200 is connected to the current output terminal. The circuit realizes current replication based on the following principle: drain-source current I of transistor in saturation statedAnd gate source voltage VgsHas a relationship ofd＝β·(Vgs-Vth)2/2, wherein, β ═ μ CoxA/b, μ is electron or hole mobility, CoxThe gate oxide capacitance per unit area is shown, and a/b is the width-to-length ratio of the transistor, VthIs the threshold voltage.
For (a)2/b2)/(a1/b1) In the case of w, the circuit outputs a current IoutShould theoretically be the input current IinW times (hereinafter referred to as output current I)outIs a reference current IrefAnd is referenced to a current Iref＝w·Iin) Wherein a is2/b2Is the width-to-length ratio, a, of the second transistor 2001/b1Is the width to length ratio of the first transistor 100. However, considering the mismatching (Mis-Match) factor in the chip manufacturing process, the output current I of the conventional current mirror is equal to the output current I even though the common current mirror overcomes the channel modulation effect caused by the difference of drain-source voltagesoutWill also be referred to the reference current IrefDeviation of around + -10%, which is to be accurately reproduced when requiredThe current situation is often not negligible.
Disclosure of Invention
In order to solve the problems in the prior art, the present invention provides a current mirror, a current copying method and an electronic device, which can reduce the adverse effect of mismatching on an output current, so that the output current can accurately copy an input current according to a preset proportionality coefficient.
According to a first aspect of the present invention, there is provided a current mirror comprising: the source electrode of the first transistor is grounded, and the drain electrode of the first transistor is respectively connected with the grid electrode of the first transistor and the current input end;
a plurality of second transistors, gates of the second transistors being connected to a gate of the first transistor, sources of the second transistors being grounded, drains of the plurality of second transistors being connected to a current output terminal through a same connection node, and a selection switch being provided between the drain of each of the second transistors and the connection node;
the control branch circuit is used for sequentially controlling the conduction of the equal but non-repeated selection switches at different moments so that the current output end outputs the average value of the currents at different moments on the connection node;
the first transistor and the second transistor are both first type transistors with equal threshold voltages or second type transistors with equal threshold voltages, the width-to-length ratio of the second transistors and the width-to-length ratio of the first transistors are approximately equal to the preset current ratio of the current mirror, and the first type and the second type are opposite.
Optionally, the first type transistor is a P-type MOSFET, or the first type transistor is an N-type MOSFET.
Optionally, the width-to-length ratios of the plurality of second transistors are the same as each other.
Optionally, the width and length of the plurality of second transistors are different.
Optionally, the width-to-length ratios of the plurality of second transistors are different from each other and the difference is smaller than a predetermined value.
Optionally, the current mirror supplies power to a power device operating in a predetermined period, and the control branch includes:
a generator for generating a periodic strobe signal;
a gate connected to the generator and the plurality of selection switches for sequentially gating the plurality of selection switches in each gate period according to the gate signal,
wherein the gating period is less than the predetermined period.
Optionally, the output current of the current mirror is an average current of the gating period.
Optionally, the generator comprises any one of: a timer, a counter, and a random number generator.
According to a second aspect of the present invention, there is provided a current copying method comprising:
receiving an input current through a first transistor;
copying the input current through a plurality of second transistors to obtain a plurality of mirror currents;
sequentially controlling the current output branches of the second transistors to be conducted at the same quantity but not repeated at different moments so as to enable the current output ends to output average values of currents at different moments on the connecting nodes,
wherein the current output branches of the plurality of second transistors are connected to the current output terminal through the connection node.
According to a third aspect of the present invention, there is provided an electronic device comprising a powered device and the current mirror of the first aspect, wherein the powered device and the current output of the current mirror are connected to supply power to the powered device through the current mirror.
The invention has the beneficial effects that:
each second transistor and each first transistor are combined to form a sub-current mirror, and the deviation of the image current obtained by each sub-current mirror relative to the reference current (the ratio of the reference current to the input current is equal to the preset current ratio) has a positive value and a negative value, so that the average value of the currents at different moments on the connecting node is closer to the standard current (the ratio of the standard current to the reference current is equal to the number of simultaneously-gated switches) due to the offset effect of the positive deviation and the negative deviation, the adverse effect of mismatching on the output current is reduced, and the technical effect of enabling the output current to accurately copy the input current according to the preset proportionality coefficient is achieved.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings.
FIG. 1 is a schematic circuit diagram of a current mirror in the prior art;
FIG. 2 is a schematic diagram showing a circuit configuration of a current mirror according to the present invention;
FIG. 3 illustrates a simulation result corresponding to a current mirror circuit in the prior art;
FIG. 4 shows a simulation result corresponding to a current mirror in an embodiment of the invention;
FIG. 5 shows a schematic diagram of the control branch to the plurality of switches in the present invention;
fig. 6 shows a flow chart of a current copy method in the present invention.
Detailed Description
The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. Moreover, certain well-known elements may not be shown in the figures.
In the following description, numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of the devices are described in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.
Fig. 2 shows a schematic circuit diagram of the current mirror of the present invention. Referring to fig. 2, the current mirror includes:
a first transistor 100 (the first transistor 100 is also denoted as M0), a source of the first transistor 100 is grounded, and a drain of the first transistor 100 is connected to a gate of the first transistor 100 and a current input terminal, respectively;
n second transistors 200 (the ith second transistor 200 is denoted as M1_ i, i is 0, 1, …, n-1, where n is an integer greater than 1, and n is used as a definition unless otherwise specified in the following description), a gate of the second transistor 200 is connected to a gate of the first transistor 100, a source of the second transistor 200 is grounded, drains of the plurality of second transistors 200 are connected to the current output terminal through the same connection node Q, and a selection switch S is provided between the drain of each second transistor 200 and the connection node Q (a selection switch Si is provided between the drain of the second transistor M1_ i and the connection node Q);
the control branch circuit 300 is configured to sequentially control the conduction of the equal but non-repetitive selection switches S at different times, so that the current output end outputs an average value of currents at different times on the connection node Q;
the first transistor 100 and the second transistor 200 are both transistors of a first type having the same threshold voltage or transistors of a second type having the same threshold voltage, and the width-to-length ratio of the second transistors 200 and the width-to-length ratio of the first transistor 100 are substantially equal to a predetermined current ratio w of the current mirror (w is defined as w unless otherwise specified in the following description), where the first type is opposite to the second type.
The first type transistor may be a P-type MOSFET or an N-type MOSFET.
The specific control process of the control branch can be explained as follows: the control branch 300 is at a first time t1The first gating of the second transistor 200 is performed and m is gated1A second transistor 200 (also called the first group of output branches) at a second time t2A second gating of the second transistor 200 is performed and m is gated2A second transistor 200 (also called the second set of output branches), …, at time t (k is the amount of target current averaged over time and is used as such unless otherwise specified in the description below) at time tkThe kth gating of the second transistor 200 is performed and m is gatedkA second transistor 200 (also called kth group)Output branch) where m1＝m2＝…＝mk(ii) a At least two groups of output branches in the first group of output branches, the second group of output branches, … and the kth group of output branches are not completely the same; and (t)j+1-tj) Small enough that the current output as a whole delivers electrical energy to the consumer with a time average of k slightly fluctuating target currents, where j is 1, 2, …, k-1.
The time average value is a value obtained by averaging a plurality of target currents over time, and is specifically recorded as t0Is an initial time tfIs the f-th time, If' is the target current corresponding to the gating operation at the f-th time, the time average ī of the k target currents is:
it should be understood that, since the drains of the plurality of second transistors 200 that are simultaneously gated are connected in parallel to the connection node Q, if each gating is to simultaneously gate m (m is interpreted as meaning unless otherwise specified in the following description) second transistors 200, the target current is the mirroring current I on the m second transistors 200 that are simultaneously gatediAt each mirror current IiIs equal to the reference current IrefIn the case of (1), the target current I' is m.Iref. However, the mirror current IiRelative to IrefThere is a deviation of about + -10%, and therefore the target current I' is also equal to or greater than the standard current m.IrefOr less than the standard current m.IrefTherefore, when there are a plurality of target currents I ', the plurality of target currents I' can be averaged over time with respect to m · IrefIs offset so that the output current I of the current mirror is cancelledoutCloser to the standard current m.I than the single target current Iref。
FIG. 3 shows a formula IinWhen w is 1uA, n is 1, m is 1outThe 1000 Monte Carol simulation results correspond to the existing Monte Carol simulation resultsA simulation result of current mirror circuit in the art, wherein the horizontal axis represents IoutThe vertical axis represents IoutThe coordinate values on the horizontal axis and the vertical axis are all evenly distributed, and the vertical coordinate of each rectangular block is represented at IoutTaking the value of I within the range of the rectangular block bounded by the abscissaoutThe number of the cells. The following results are calculated according to the simulation result: i isoutThe sum and average value of (1 uA), the standard error sigma of 35.6nA, and 3sigma of 106.8nA, i.e. the current mirror 3-sigma distribution range is (1u-106.8nA, 1u +106.8nA), which is equivalent to (1-10%, 1+ 10%). 1uA in percentage.
FIG. 4 shows a formula IinWhen w is 1uA, n is 8, and m is 1, the pair IoutThe 1000 monte carol simulation results are a simulation result corresponding to the current mirror in the embodiment of the present invention, and the number n of the second transistors 200 is different between the circuit simulated in fig. 4 and the circuit simulated in fig. 3. Similarly, in FIG. 4, the horizontal axis represents IoutThe vertical axis represents IoutThe coordinate values on the horizontal axis and the vertical axis are all evenly distributed, and the vertical coordinate of each rectangular block is represented at IoutTaking the value of I within the range of the rectangular block bounded by the abscissaoutThe number of the cells. The following results are calculated according to the simulation result: i isoutThe sum and average of (a) is 1uA, and the standard error sigma is 4 nA.
In conjunction with fig. 3 and 4, it can be seen that: compared with the current mirror in the prior art, the current mirror provided by the embodiment of the invention enables the output current I to pass through the improvement of the circuit structureoutIs reduced to 1/8, i.e. the current output outputs the output current I with a greater probability with a smaller deviation from the standard currentout。
The current mirror provided by the embodiment of the invention reduces the output current I of the mismatching pairoutTo achieve the output current IoutAccurately copying the input current I according to a preset proportionality coefficient winThe technical effect of (1).
The width-to-length ratio of the plurality of second transistors 200 to the width-to-length ratio of the first transistor 100 is approximately equal to the preset current ratio w of the current mirror, and two schemes to be selected specifically may be as follows:
(1) the width-to-length ratios of the plurality of second transistors 200 are the same as each other
Specifically, the plurality of second transistors 200 may have the same width and the same length, and the plurality of second transistors 200 may have different widths and different lengths.
For the case where the plurality of second transistors 200 are equal in width and also equal in length, the following example can be adopted:
width a of the second transistor M1_ i2Are all of a first length a0(a2＝a0) Length b of the second transistor M1_ i2All are of the second length b0(b2＝b0) Wherein the first length a0And a second length b0Is a target ratio Sc0Target ratio Sc0Width to length ratio of Sc to first transistor1Is equal to a preset proportionality coefficient w. Thus, based on the drain-source current I of the transistor in saturationdAnd gate source voltage VgsIn that the plurality of second transistors 200 output positive offset mirror currents I that are equal in probability depending on mismatching in the chip manufacturing processiAnd negative offset mirror current IiIn order to improve the current reproduction accuracy by the time averaging process of a plurality of target currents.
(2) The width-to-length ratios of the plurality of second transistors 200 are different from each other and different by less than a predetermined value
Specifically, it may be a width a of the plurality of second transistors M1 — i2Not identical, and/or the length b of the plurality of second transistors M1_ i2Not exactly the same, wherein the width a of each second transistor M1_ i2And a first length a0Is less than a first threshold; length b of each second transistor M1_ i2And a second length b0Is smaller than a second threshold value, and finally the width-to-length ratios of the plurality of second transistors 200 are different from each other and have a difference smaller than a predetermined value but the width-to-length ratio of each second transistor 200 to the first transistor 100 is substantially equal to a preset current ratio w of the current mirror, wherein the first length a0And a second length b0Is a target ratio Sc0Target ratio Sc0Width to length ratio of Sc to first transistor1Is equal to a preset proportionality coefficient w.
It should be noted that the first threshold value can be determined according to the first length a0Also, the second threshold value may be determined according to the second length b0Is determined; further, the first threshold may define the width a of the second transistor M1 — i by a percentage2Relative to the first length a0A fine adjustment is made and the second threshold value may also define the length b of the second transistor M1_ i in terms of a percentage2Relative to the second length b0Fine tuning is performed.
For example, the first length a0Is 2um, the first threshold value needs to be a first length a03% of the first threshold value, the first threshold value is equal to 60 nm; and a second length b0Is 1.5um, the second threshold value needs to be the second length b03% of the first threshold value, the second threshold value is equal to 45 nm. Then, the width a of the plurality of second transistors M1 — i2And length b2Can be respectively set as: a is22um +20nm and b2＝1.5um-30nm、a22um-50nm and b21.5um to 30nm, etc.
Thus, the plurality of second transistors 200 output positive offset mirror currents IiAnd negative offset mirror current IiThe probability ratio of (a) is a modulation of the size of the second transistor M1 — i.e., a modulation of factors other than mismatch, where the mismatch causes the plurality of second transistors 200 to output positive offset mirror currents IiAnd negative offset mirror current IiIn case of unequal probabilities, the plurality of second transistors 200 can be enabled to output positive offset image currents I by modulating the sizes of the second transistors M1_ IiAnd negative offset mirror current IiAre equal, and then the current replication accuracy is improved as much as possible by the time averaging process of the plurality of target currents.
Referring to fig. 5, in another alternative embodiment, in which a current mirror supplies power to a powered device operating for a predetermined period, the control branch 300 includes:
a generator 310 for generating a periodic gating signal Con;
the gating unit 320 is connected to the timer 310 and the plurality of selection switches S, and is configured to gate the plurality of selection switches S in sequence every gating period according to the gating signal Con, wherein the gating period is less than a predetermined period.
Specifically, it can be understood that: generator 310, during a strobe cycle: in chronological order at a first time t1Generating a control command Con1At a second time t2Generating a control command Con2…, at time k tkGenerating a control command Conk(k is the amount of target current in one gating period), wherein, for the j (j ═ 1, 2, …, k) th time, the generator 310 generates the control command ConjThe gate 320 receives the control command ConjAnd according to the control command ConjTo generate the jth control signal group Xj＝{Pj1，Pj2，…，PjmIn which P isj1，Pj2，…，PjmAre all different and respectively correspond to an on signal P0Control switch S0Switch on, turn on signal P1Control switch S1On, …, turn on signal PnControl switch SnOn, and, the v-th control signal group XvAt least one of the included control signals is the jth control signal group XjExcluded (v ≠ j) is 1, 2, …, k and v ≠ j).
The generator 320 receives the control command Conj and generates a control command Con according to the control command ConjTo generate the jth control signal group Xj＝{Pj1，Pj2，…，PjmMay be implemented based on associated data stored in the gating device 320, the associated data being indicative of the control command ConjAnd control signal group XjData of the corresponding relationship between them.
The switch may adopt an N-type MOSFET as shown in fig. 5, and the specific connection manner is: the source is connected to the drain of the second transistor 200, the drain is connected to the connection node Q, and the gate is connected to the gate 320 to receive the control signal Con.
Further, as mentioned aboveThe predetermined number m being determined by the current demanded by the consumer to be driven by the current mirror, e.g. the input current IinWhen the required current of the electric device is 3uA, the preset number m is 3. Thus, the current mirror provided by the embodiment of the invention can be used for supplying electric energy to various electric equipment with different current requirements.
In the embodiment of the present invention, the control branch 300 achieves the purpose that a plurality of target currents are sequentially generated in time sequence within one gating period through the generator 310 and the gate 320, and the operation and the control are simple and orderly; in addition, the current mirror provides stable current for the electric equipment by taking the gating period as unit time, and if the gating period is shortened, the output current I of the current mirror can be further enabledoutThe current is always kept as the average current of all target currents in the gating period, so that the excellent characteristic that the power supply current is more stable is achieved.
Further, the generator 310 includes any one of the following:
(1) the timer is used for measuring time in a target time length unit and generating a control instruction at each measured moment, wherein the control instructions correspond to the sequencing of the control signal groups through the generation sequence to establish a one-to-one correspondence relationship, namely the control instructions have no content difference, for example, the control instructions can be all pulse signals, so that the generation of the control instructions is simpler.
For example, if the target time length unit is 0.002s, the control command Con is generated at 0.002s from the start time1Then, the control command Con is generated at a time 0.004s from the start time2…, the control command Con is finally generated at (k 0.002) s from the start timek。
And if the control commands are ordered into { Con ] in the generation order1、Con2、…、Cony、…、ConkThe ordering of the control signal groups is { X }1、X2、…、Xy、…、Xk}, the control command ConyAnd control signal group XyCorrespondingly, (y ═ 1, 2, …, k), that is, the gate 320 receives the control command ConyIn case of (2), a control signal is outputNumber group Xy。
(2) The counter is used for sequentially generating numbers with gradually increasing values as control instructions according to the time sequence, wherein the control instructions establish a one-to-one correspondence relationship by digitally representing the sequence numbers of the control signal groups, so that the generation of the control instructions can be realized by the conventional counter, and the gating device 320 does not need to store more complicated associated data.
It should be noted that, the numbers with the numerical values gradually increasing one by one are sequentially generated in time series, for example, the counter sequentially generates the numbers 1, 2, …, y, …, k in time series, and each of these numbers represents a control command; ordering of control signal groups as { X1、X2、…、Xy、…、XkThe gating unit 320 outputs the control signal group X when receiving the control command represented by the number yy。
(3) The random number generator is used for sequentially generating random numbers or random number groups as control instructions according to a time sequence, wherein the control instructions establish a one-to-one correspondence relationship by representing the arrangement numbers of the control signal groups through the random numbers, or establish a one-to-one correspondence relationship by representing the arrangement numbers of the output branches through the numbers in the random number groups, so that the generation of the control instructions can be realized by the conventional random number generating circuit, the gating device 320 does not need to store more complex associated data, the randomness of gating of the output branches is increased, and the positive deviation mirror current I is favorably output with equal probabilityiAnd negative offset mirror current Ii。
The control commands are arranged in a one-to-one correspondence by randomly numerically representing the control signal groups, e.g., the control signal groups are arranged in an order of { X }1、X2、…、Xy、…、XkAnd if the random number generation circuit sequentially generates the following random numbers in time sequence as a control instruction: 4, 1, …, the gate 320 outputs the control signal groups X in time sequence4，X1，…。
The control command is in one-to-one correspondence relationship by representing the rank number of the control signal group by a random number, for example, a preset number m is 2, and the random number generation circuit sequentially generates the following random number groups in time sequence as the control command: {4, 7}, {2, 1}, …, the gate 320 controls the fourth output branch and the seventh output branch to be conducted first and then controls the second output branch and the first output branch to be conducted, …, in time sequence.
An embodiment of the present invention further provides a current replication method, and referring to fig. 6, the current replication method includes:
step S101, receiving input current through a first transistor;
step S102, copying input current through a plurality of second transistors to obtain a plurality of mirror currents;
and step S103, sequentially controlling the current output branches of the equal-quantity but non-repetitive second transistors to be conducted at different moments so that the current output ends output the average values of the currents at different moments on the connection nodes, wherein the current output branches of the plurality of second transistors are connected to the current output ends through the connection nodes.
Specifically, the current method may be implemented by using any one of the current mirrors described above, and details about the specific implementation of the current replication method may refer to the description about the current mirror described above, and are not described herein again.
According to the current copying method provided by the embodiment of the invention, each second transistor and each first transistor are combined to form a sub-current mirror, and the deviation of the image current obtained by each sub-current mirror relative to the reference current (the ratio of the reference current to the input current is equal to the preset current ratio) has a positive value and a negative value, so that the average value of the currents at different moments on the connection node is closer to the standard current (the ratio of the standard current to the reference current is equal to the number of simultaneously-gated switches) due to the offset of the positive deviation and the negative deviation, the adverse effect of mismatching on the output current is reduced, and the technical effect of enabling the output current to copy the input current more accurately according to the preset proportionality coefficient is achieved.
Corresponding to the current mirror, the embodiment of the invention also provides electronic equipment, which comprises electric equipment and any one of the current mirrors, wherein the electric equipment is connected with the current output end of the current mirror so as to provide electric energy for the electric equipment through the current mirror, so that the electric equipment can obtain more accurate electric energy to perform high-performance work.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
In accordance with the present invention, as set forth above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and their full scope and equivalents.
Claims (10)
1. A current mirror, comprising:
the source electrode of the first transistor is grounded, and the drain electrode of the first transistor is respectively connected with the grid electrode of the first transistor and the current input end;
a plurality of second transistors, gates of the second transistors being connected to a gate of the first transistor, sources of the second transistors being grounded, drains of the plurality of second transistors being connected to a current output terminal through a same connection node, and a selection switch being provided between the drain of each of the second transistors and the connection node;
the control branch circuit is used for sequentially controlling the conduction of the equal but non-repeated selection switches at different moments so that the current output end outputs the average value of the currents at different moments on the connection node;
the first transistor and the second transistor are both first type transistors with equal threshold voltages or second type transistors with equal threshold voltages, the width-to-length ratio of the second transistors and the width-to-length ratio of the first transistors are approximately equal to the preset current ratio of the current mirror, and the first type and the second type are opposite.
2. The current mirror of claim 1, wherein the first type transistor is a P-type MOSFET or the first type transistor is an N-type MOSFET.
3. The current mirror of claim 1, wherein the width-to-length ratios of the plurality of second transistors are the same as each other.
4. The current mirror of claim 3, wherein the second transistors are each different in width and length.
5. The current mirror of claim 1, wherein the width-to-length ratios of the second transistors are different from each other by less than a predetermined value.
6. The current mirror of claim 1, which supplies power to a powered device operating for a predetermined period, wherein the control branch comprises:
a generator for generating a periodic strobe signal;
a gate connected to the generator and the plurality of selection switches for sequentially gating the plurality of selection switches in each gate period according to the gate signal,
wherein the gating period is less than the predetermined period.
7. The current mirror of claim 6, an output current of the current mirror being an average current of the gating period.
8. The current mirror of claim 6, wherein the generator comprises any one of: a timer, a counter, and a random number generator.
9. A current copy method, comprising:
receiving an input current through a first transistor;
copying the input current through a plurality of second transistors to obtain a plurality of mirror currents;
sequentially controlling the current output branches of the second transistors to be conducted at the same quantity but not repeated at different moments so as to enable the current output ends to output average values of currents at different moments on the connecting nodes,
wherein the current output branches of the plurality of second transistors are connected to the current output terminal through the connection node.
10. An electronic device comprising a powered device and a current mirror as claimed in any of claims 1 to 8, wherein the powered device is connected to a current output of the current mirror for supplying power to the powered device through the current mirror.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010526587.5A CN111781986A (en) | 2020-06-09 | 2020-06-09 | Current mirror, current copying method and electronic equipment |
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| CN202010526587.5A CN111781986A (en) | 2020-06-09 | 2020-06-09 | Current mirror, current copying method and electronic equipment |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6172495B1 (en) * | 2000-02-03 | 2001-01-09 | Lsi Logic Corporation | Circuit and method for accurately mirroring currents in application specific integrated circuits |
| CN1436351A (en) * | 2000-06-09 | 2003-08-13 | 三因迪斯克公司 | Multiple output current mirror with improved accuracy |
| CN102455732A (en) * | 2010-11-03 | 2012-05-16 | 华润矽威科技（上海）有限公司 | Circuit capable of improving matching degree of multi-path large current |
| CN109213263A (en) * | 2018-09-04 | 2019-01-15 | 合肥宽芯电子技术有限公司 | A kind of current source for improving mismatch and influencing |
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2020
- 2020-06-09 CN CN202010526587.5A patent/CN111781986A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6172495B1 (en) * | 2000-02-03 | 2001-01-09 | Lsi Logic Corporation | Circuit and method for accurately mirroring currents in application specific integrated circuits |
| CN1436351A (en) * | 2000-06-09 | 2003-08-13 | 三因迪斯克公司 | Multiple output current mirror with improved accuracy |
| CN102455732A (en) * | 2010-11-03 | 2012-05-16 | 华润矽威科技（上海）有限公司 | Circuit capable of improving matching degree of multi-path large current |
| CN109213263A (en) * | 2018-09-04 | 2019-01-15 | 合肥宽芯电子技术有限公司 | A kind of current source for improving mismatch and influencing |
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Application publication date: 20201016 |