CN111755406A - 减少无应力释放器件焊点应力的结构、制作方法及应用 - Google Patents

减少无应力释放器件焊点应力的结构、制作方法及应用 Download PDF

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CN111755406A
CN111755406A CN202010599513.4A CN202010599513A CN111755406A CN 111755406 A CN111755406 A CN 111755406A CN 202010599513 A CN202010599513 A CN 202010599513A CN 111755406 A CN111755406 A CN 111755406A
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栗凡
潘恒太
刘军
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Xian Microelectronics Technology Institute
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Abstract

一种减少无应力释放器件焊点应力的结构、制作方法及应用,结构包括软导线,软导线的一端与印制板对应的焊盘焊点焊接,软导线回弯成型之后另一端与无应力释放器件的引线进行焊接;所述回弯成型之后的软导线外部包覆硅橡胶,软导线与无应力释放器件的引线焊点露出在硅橡胶之外。该结构能够应用于无应力释放封装器件。本发明能够有效避免焊点后期热应力对焊点的损伤,连接后器件引线焊点实现目视可检测,并且与器件原有焊点能够兼容,在焊盘和器件引线长度无法更改的情况下,减少无应力释放器件的焊点应力。

Description

减少无应力释放器件焊点应力的结构、制作方法及应用
技术领域
本发明涉及电子元器件焊点结构,具体涉及一种减少无应力释放器件焊点应力的结构、制作方法及应用,提高电子元器件的安全可靠性。
背景技术
按照QJ 3171《航天电子电气产品元器件成形技术要求》标准第4.4条要求,QFP、SOP封装器件装焊前需要对其引线进行成形处理,成形处理后增加器件的应力释放弯,满足后期器件组装至印制板后的各种环境试验要求。现在普遍的做法是:按照要求由操作人员对器件进行倒置成形,使其引线形成一种倒置悬臂梁结构。如图1所示。
而现有国产QFP、SOP封装器件底部外引出的引线较短,无法满足标准中规定的倒置成形,如图2所示,若按照图2的方式直接焊接,后期试验中由于引线焊点应力得不到释放会导致焊点出现问题,为了避免底部出引线QFP、SOP封装器件后期引线焊点应力都得到释放,必须对其引线焊点采取应力释放措施。
发明内容
本发明的目的在于针对上述现有技术中器件由于引线较短而采用直接焊接导致应力得不到释放的问题,提供一种减少无应力释放器件焊点应力的结构、制作方法及应用,有效避免焊点后期热应力对焊点的损伤,连接后器件引线焊点实现目视可检测,并且与器件原有焊点能够兼容,在焊盘和器件引线长度无法更改的情况下,减少无应力释放器件的焊点应力。
为了实现上述目的,本发明有如下的技术方案:
一种减少无应力释放器件焊点应力的结构,包括软导线,软导线的一端与印制板对应的焊盘焊点焊接,软导线回弯成型之后另一端与无应力释放器件的引线进行焊接;所述回弯成型之后的软导线外部包覆硅橡胶,软导线与无应力释放器件的引线焊点露出在硅橡胶之外。
作为一种优选方案,在焊接完毕的软导线以及印制板上涂刷三防漆固化,三防漆选用TS01-3聚氨酯清漆。
作为一种优选方案,所述硅橡胶的灌注高度与软导线回弯部位的高度齐平,硅橡胶的型号选用GD414。
作为一种优选方案,所述软导线的尺寸、长度根据引线焊点以及焊盘焊点的间距满足连接需要来调整。
本发明同时提供一种减少无应力释放器件焊点应力的结构的制作方法,包括以下步骤:
-将软导线的一端与印制板对应的焊盘焊点焊接,采用三防漆对焊接之后的软导线与印制板进行加固刷涂;
-软导线回弯成型;
-将与印制板焊接之后的软导线另一端与无应力释放器件的引线进行焊接,采用三防漆对焊接之后的软导线进行喷涂防护;
-注入硅橡胶,硅橡胶的灌注高度与软导线回弯部位的高度齐平,使硅橡胶将软导线完全包覆,露出软导线与无应力释放器件的引线焊点。
作为一种优选方案,所述的三防漆采用TS01-3聚氨酯清漆,硅橡胶的型号选用GD414。
作为一种优选方案,所述的硅橡胶采用注射器从软导线的外侧上方注入。
一种无应力释放封装器件,采用所述减少无应力释放器件焊点应力的结构,其耐温区间为-55℃-125℃,循环次数在500次以上。
相较于现有技术,本发明具有如下的有益效果:针对非标成形无应力释放的元器件,例如:国产底部出腿QFP封装、SOP封装器件等,本发明的结构能够保证在高温差、热应力大环境中元器件焊点的正常连接,不会因各种材料热膨胀系数不一致产生的热应力而导致的无法应力释放导致焊点断裂问题。通过调整不同软导线的尺寸、长度来适用于不同尺寸大小的元器件引线焊点、印制件焊盘间距的连接,对于不同尺寸的元器件、印制板焊盘有很好的普适性。本发明实现非标无应力释放元器件不可检焊点的双重备份,不仅可以解决国产底部出引线的QFP、SOP封装器件的焊点不可检问题,而且有效避免了后期应力对焊点的损伤。且此种连接方法成形后器件引线焊点实现目视可检测,本发明与元器件原有引线和配套印制板焊盘兼容,还能够根据软导线长度实现不同尺寸引线和焊盘的实施,具有良好的普适性。
附图说明
图1倒置悬臂梁结构引线示意图;
图2国产QFP、SOP封装器件底部外引线示意图;
图3本发明减少无应力释放器件焊点应力的结构示意图;
附图中:1-无应力释放器件;2-软导线;3-焊盘焊点;4-引线焊点;5-引线;6-印制板;7-硅橡胶。
具体实施方式
下面结合附图及实施例对本发明做进一步的详细说明。
本发明不同于传统的PCB连线方式,而是兼容原器件引线长度和PCB焊盘的自连线方式。参见图3,一种减少无应力释放器件焊点应力的结构,包括软导线2,软导线2的一端与印制板6对应的焊盘焊点3焊接,软导线2回弯成型之后另一端与无应力释放器件1的引线5进行焊接;在焊接完毕的软导线2以及印制板6上涂刷三防漆固化,实施例中的三防漆选用TS01-3聚氨酯清漆。回弯成型之后的软导线2外部包覆硅橡胶7,软导线2与无应力释放器件1的引线焊点4露出在硅橡胶7之外。硅橡胶7的灌注高度与软导线2回弯部位的高度齐平,实施例中的硅橡胶7的型号选用GD414。本发明的结构中所用到的不同软导线2的尺寸、长度根据引线焊点4以及焊盘焊点3的间距满足连接需要来调整。
一种减少无应力释放器件焊点应力的结构的制作方法,包括以下步骤:
-将软导线2的一端与印制板6对应的焊盘焊点3焊接,采用三防漆对焊接之后的软导线2与印制板6进行加固刷涂;三防漆采用TS01-3聚氨酯清漆;
-软导线2回弯成型;
-将与印制板6焊接之后的软导线2另一端与无应力释放器件1的引线5进行焊接,采用三防漆对焊接之后的软导线2进行喷涂防护;三防漆采用TS01-3聚氨酯清漆;
-采用注射器从软导线2的外侧上方注入硅橡胶7,硅橡胶7选用GD414型号,所述硅橡胶7的灌注高度与软导线2回弯部位的高度齐平,使硅橡胶7将软导线2完全包覆,露出软导线2与无应力释放器件1的引线焊点4。
一种无应力释放封装器件,其引线连接部分采用本发明减少无应力释放器件焊点应力的结构,其耐温区间为-55℃-125℃,循环次数在500次以上。
现国产陶封QFP、SOP封装器件的引出线需进行成形后上机焊接,但国产陶封QFP、SOP封装器件底部外引出的引线较短,无法满足标准中规定的应力释放成形,无应力释放的焊点在后期热应力作用下导致开裂。为减少热应力对无应力释放器件焊点的影响,本发明通过设计一种结构及工艺方法,在无法成形的情况下,在原有焊点上采用软导线二次连接、加固的方式,吸收组装后的热应力,解决了无应力释放元器件焊点在热应力条件下开裂问题。
本发明的作用是在兼容原元器件引线和组装PCB焊盘的条件下,采用软导线后无应力释放器件焊点的电性能、抗热力学性能和抗机械性能均有大幅提高,增强了器件使用的可靠性和型号的可靠性,解决了型号生产中出现的问题,目前已成功应用于多个计算机产品中。
值得注意的是,对于不同尺寸的元器件引线、印制件焊盘进行连接时,通过选用不同连接软导线的尺寸可以实现,该连接结构及工艺方法可以实现不同尺寸的元器件连接工作,有较强的普适性。使用此结构及工艺方法实施的元器件,引线焊点环境适应的程度大大提高,尤其对适应更大温度范围环境下耐热应力适应性有明显的提高。经过测试,由原来的温度区间-40℃-60℃增加到-55℃-125℃,循环次数由原来的100次增加到500次以上。大大增强了整机的使用寿命和质量,降低了元器件和整机的报废率,节约了生产成本。
以上所述的仅仅是本发明的较佳实施例,并不用以对本发明进行任何限制,本领域技术人员应当理解的是,在不脱离本发明精神和原则的前提下,该技术方案还可以进行若干简单的修改和替换,这些修改和替换也均属于权利要求书所涵盖的保护范围之内。

Claims (8)

1.一种减少无应力释放器件焊点应力的结构,其特征在于:包括软导线(2),软导线(2)的一端与印制板(6)对应的焊盘焊点(3)焊接,软导线(2)回弯成型之后另一端与无应力释放器件(1)的引线(5)进行焊接;所述回弯成型之后的软导线(2)外部包覆硅橡胶(7),软导线(2)与无应力释放器件(1)的引线焊点(4)露出在硅橡胶(7)之外。
2.根据权利要求1所述减少无应力释放器件焊点应力的结构,其特征在于:在焊接完毕的软导线(2)以及印制板(6)上涂刷三防漆固化,三防漆选用TS01-3聚氨酯清漆。
3.根据权利要求1所述减少无应力释放器件焊点应力的结构,其特征在于:硅橡胶(7)的灌注高度与软导线(2)回弯部位的高度齐平,硅橡胶(7)的型号选用GD414。
4.根据权利要求1所述减少无应力释放器件焊点应力的结构,其特征在于:软导线(2)的尺寸、长度根据引线焊点(4)以及焊盘焊点(3)的间距满足连接需要来调整。
5.一种减少无应力释放器件焊点应力的结构的制作方法,包括以下步骤:
-将软导线(2)的一端与印制板(6)对应的焊盘焊点(3)焊接,采用三防漆对焊接之后的软导线(2)与印制板(6)进行加固刷涂;
-软导线(2)回弯成型;
-将与印制板(6)焊接之后的软导线(2)另一端与无应力释放器件(1)的引线(5)进行焊接,采用三防漆对焊接之后的软导线(2)进行喷涂防护;
-注入硅橡胶(7),硅橡胶(7)的灌注高度与软导线(2)回弯部位的高度齐平,使硅橡胶(7)将软导线(2)完全包覆,露出软导线(2)与无应力释放器件(1)的引线焊点(4)。
6.根据权利要求5所述减少无应力释放器件焊点应力的结构的制作方法,其特征在于:所述的三防漆采用TS01-3聚氨酯清漆,硅橡胶(7)的型号选用GD414。
7.根据权利要求5所述减少无应力释放器件焊点应力的结构的制作方法,其特征在于:所述的硅橡胶(7)采用注射器从软导线(2)的外侧上方注入。
8.一种无应力释放封装器件,其特征在于,采用如权利要求1-4中任意一项所述的减少无应力释放器件焊点应力的结构,耐温区间为-55℃-125℃,循环次数在500次以上。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113571309A (zh) * 2021-07-23 2021-10-29 西安微电机研究所 一种航天领域用较大体积电感安装结构及工艺
CN114885495A (zh) * 2022-04-28 2022-08-09 西安微电子技术研究所 一种转接印制板焊接结构及焊接工艺

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10200024A (ja) * 1996-10-01 1998-07-31 Internatl Rectifier Corp 表面実装用パッケージとその製造方法
US20030209785A1 (en) * 2002-05-10 2003-11-13 Choi Seung-Yong Semiconductor package having solder joint of improved reliability
CN101221930A (zh) * 2007-01-10 2008-07-16 日月光半导体制造股份有限公司 芯片封装结构及其封装方法
JP2009152228A (ja) * 2007-12-18 2009-07-09 Pearl Lighting Co Ltd 反射型発光ダイオード
US20100193923A1 (en) * 2009-01-30 2010-08-05 Renesas Technology Corp. Semiconductor Device and Manufacturing Method Therefor
CN102117753A (zh) * 2010-01-05 2011-07-06 飞思卡尔半导体公司 封装半导体器件的方法
CN205092235U (zh) * 2014-12-10 2016-03-16 意法半导体有限公司 集成电路ic器件
CN107221524A (zh) * 2017-06-26 2017-09-29 西安微电子技术研究所 一种针对底部引出器件非倒置成形的工艺方法
CN107919338A (zh) * 2017-12-20 2018-04-17 苏州市悠文电子有限公司 Pcb板led晶片插件组件

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10200024A (ja) * 1996-10-01 1998-07-31 Internatl Rectifier Corp 表面実装用パッケージとその製造方法
US20030209785A1 (en) * 2002-05-10 2003-11-13 Choi Seung-Yong Semiconductor package having solder joint of improved reliability
CN101221930A (zh) * 2007-01-10 2008-07-16 日月光半导体制造股份有限公司 芯片封装结构及其封装方法
JP2009152228A (ja) * 2007-12-18 2009-07-09 Pearl Lighting Co Ltd 反射型発光ダイオード
US20100193923A1 (en) * 2009-01-30 2010-08-05 Renesas Technology Corp. Semiconductor Device and Manufacturing Method Therefor
CN102117753A (zh) * 2010-01-05 2011-07-06 飞思卡尔半导体公司 封装半导体器件的方法
CN205092235U (zh) * 2014-12-10 2016-03-16 意法半导体有限公司 集成电路ic器件
CN107221524A (zh) * 2017-06-26 2017-09-29 西安微电子技术研究所 一种针对底部引出器件非倒置成形的工艺方法
CN107919338A (zh) * 2017-12-20 2018-04-17 苏州市悠文电子有限公司 Pcb板led晶片插件组件

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
武晔卿: "《嵌入式系统可靠性设计技术及案例解析》", 31 July 2012, 北京航空航天大学出版社 *
王文祥: "《微波工程技术》", 30 April 2009, 国防工业出版社 *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113571309A (zh) * 2021-07-23 2021-10-29 西安微电机研究所 一种航天领域用较大体积电感安装结构及工艺
CN113571309B (zh) * 2021-07-23 2022-08-05 西安微电机研究所有限公司 一种航天领域用较大体积电感安装结构及工艺
CN114885495A (zh) * 2022-04-28 2022-08-09 西安微电子技术研究所 一种转接印制板焊接结构及焊接工艺
CN114885495B (zh) * 2022-04-28 2023-06-06 西安微电子技术研究所 一种转接印制板焊接结构及焊接工艺

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