CN111739862A - Semiconductor packaging structure and manufacturing method thereof - Google Patents
Semiconductor packaging structure and manufacturing method thereof Download PDFInfo
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- CN111739862A CN111739862A CN202010780581.0A CN202010780581A CN111739862A CN 111739862 A CN111739862 A CN 111739862A CN 202010780581 A CN202010780581 A CN 202010780581A CN 111739862 A CN111739862 A CN 111739862A
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/54—Providing fillings in containers, e.g. gas fillings
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- H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
- H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
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Abstract
The embodiment of the application provides a semiconductor packaging structure and a manufacturing method of the semiconductor packaging structure, and relates to the technical field of semiconductors, wherein the semiconductor packaging structure comprises a substrate, a first supporting chip, a first stacked chip and filling glue, the substrate comprises conductive glue, and the first stacked chip comprises a first vertical routing; the first supporting chip is arranged on one side of the substrate; the first stacked chip is arranged on one side, far away from the substrate, of the first supporting chip in a shifting and stacking mode, wherein one side, where the first vertical routing is located, is in contact with the first supporting chip; the first vertical routing is connected with the substrate through conductive adhesive; the filling adhesive is arranged between the first stacked chip and the substrate, wraps the first vertical routing, can ensure the stability of routing by arranging the first vertical routing and the filling adhesive, can keep the structural strength of the semiconductor packaging structure, and can obtain a stable semiconductor packaging structure.
Description
Technical Field
The application relates to the technical field of semiconductors, in particular to a semiconductor packaging structure and a manufacturing method of the semiconductor packaging structure.
Background
With the development of semiconductor technology, electronic products tend to be miniaturized, and the performance and memory requirements of the electronic products are higher and higher, in the prior art, a semiconductor package structure adopts a Stack-Die (Stack-Die) technology or a flow over wire (fow) stacking technology to meet the increasing requirements. However, in the semiconductor package manufactured by the prior art, as the number of stacked chips is higher, the wire bonding length is longer, and it is difficult to precisely wire the chip, which may cause unstable wire bonding. Furthermore, as the height of the chip stack increases, the inclination of the chip stack increases, and the bottom structure of the chip becomes unstable, which may cause the stacked chip structure to collapse, resulting in product damage, and thus making the conventional semiconductor package structure with stacked multi-layer chips unstable.
Based on this, it is necessary for those skilled in the art to provide a stable implementation scheme of a semiconductor package structure with stacked multi-layer chips.
Disclosure of Invention
The application provides a semiconductor packaging structure and a manufacturing method of the semiconductor packaging structure.
The embodiment of the application can be realized as follows:
in a first aspect, an embodiment of the present application provides a semiconductor package structure, including a substrate, a first supporting chip, a first stacked chip, and a filling adhesive, where the substrate includes a conductive adhesive, and the first stacked chip includes a first vertical wire bond;
the first supporting chip is arranged on one side of the substrate;
the first stacked chip is arranged on one side, far away from the substrate, of the first supporting chip in an offset stacking mode, wherein one side, where the first vertical routing is located, is in contact with the first supporting chip;
the first vertical routing is connected with the substrate through the conductive adhesive;
the filling adhesive is arranged between the first stacked chip and the substrate, and wraps the first vertical routing.
In an alternative embodiment, the first stacked chip further comprises pins;
one end of the pin is connected with the chip body of the first stacked chip, and the other end of the pin is connected with the first vertical routing.
In an alternative embodiment, the semiconductor package structure further includes a second stacked die, the second stacked die including a second vertical wire bond;
the second stacked chip is arranged on one side of the first stacked chip far away from the first supporting chip in an offset stacking mode, and one side where the second vertical routing is located is in contact with the first stacked chip;
the second vertical routing is connected with the substrate through the conductive adhesive;
the filling adhesive is arranged between the second stacked chip and the substrate, and wraps the second vertical routing.
In an alternative embodiment, the offset directions of the first stacked chip and the second stacked chip are the same.
In an optional embodiment, the semiconductor package structure further includes a control chip, a second supporting chip, and a third stacked chip, where the third stacked chip includes a third vertical wire bonding;
the control chip is arranged on one side of the substrate, and the second supporting chip is arranged on the substrate on one side of the control chip far away from the first supporting chip;
the third stacked chip is arranged on one side, far away from the substrate, of the second supporting chip in an offset stacking mode, wherein one side, where the third vertical routing is located, is in contact with the second supporting chip;
the third vertical routing is connected with the substrate through the conductive adhesive;
the filling adhesive is arranged between the third stacked chip and the substrate, and wraps the third vertical routing.
In a second aspect, an embodiment of the present application provides a method for fabricating a semiconductor package structure, for fabricating and forming the semiconductor package structure described in any one of the foregoing embodiments, the method includes:
providing a substrate, and arranging a first supporting chip on one side of the substrate;
arranging conductive adhesive on the substrate on one side of the first supporting chip;
arranging a first stacked chip on one side of the first supporting chip far away from the substrate, wherein the offset direction of the first stacked chip is the direction in which the first supporting chip points to the conductive adhesive, and one side where a first vertical routing is located is in contact with the first supporting chip;
connecting the first vertical routing with the conductive adhesive and solidifying the conductive adhesive so as to enable the first stacked chip to be communicated with the substrate through the first vertical routing;
filling glue into a gap between the first stacked chip and the substrate, and curing the filling glue to fix the first vertical routing.
In an alternative embodiment, the method further comprises:
arranging conductive adhesive on one side, away from the first supporting chip, of the conductive adhesive connected with the substrate through the first vertical routing;
arranging a second stacked chip on one side of the first stacked chip far away from the first supporting chip, wherein the offset direction of the second stacked chip is the direction in which the first supporting chip points to the conductive adhesive, and one side where a second vertical routing is located is in contact with the first stacked chip;
connecting the second vertical routing with the conductive adhesive and solidifying the conductive adhesive so as to enable the second stacked chip to be communicated with the substrate through the second vertical routing;
filling glue into a gap between the second stacked chip and the substrate and solidifying the filling glue so as to fix the second vertical routing.
The beneficial effects of the embodiment of the application include, for example: by adopting the semiconductor packaging structure and the manufacturing method thereof, the semiconductor packaging structure comprises a substrate, a first supporting chip, a first stacked chip and filling glue, wherein the substrate comprises conductive glue, and the first stacked chip comprises a first vertical routing; the first supporting chip is arranged on one side of the substrate; the first stacked chip is arranged on one side, far away from the substrate, of the first supporting chip in an offset stacking mode, wherein one side, where the first vertical routing is located, is in contact with the first supporting chip; the first vertical routing is connected with the substrate through the conductive adhesive; the filling adhesive is arranged between the first stacked chip and the substrate, wraps the first vertical routing, can ensure the stability of routing by arranging the first vertical routing and the filling adhesive, can keep the structural strength of the semiconductor packaging structure, and can obtain a stable semiconductor packaging structure.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained from the drawings without inventive effort.
Fig. 1 is a schematic structural diagram of a semiconductor package structure according to an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of a first stacked chip according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of another semiconductor package structure according to an embodiment of the present disclosure;
fig. 4 is a schematic structural diagram of another semiconductor package structure according to an embodiment of the present disclosure;
fig. 5 is a flowchart illustrating a method for manufacturing a semiconductor package structure according to an embodiment of the present disclosure.
Icon: 1-a semiconductor package structure; 10-a substrate; 101-conductive adhesive; 11-a first supporting chip; 12-a first stacked chip; 121-first vertical routing; 122-pin; 13-filling glue; 14-a second stacked chip; 141-second vertical routing; 15-a control chip; 16-a second supporting chip; 17-a third stacked chip; 171-third vertical bonding.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
In the description of the present application, it should be noted that if the terms "upper", "lower", "inside", "outside", etc. are used for indicating the orientation or positional relationship based on the orientation or positional relationship shown in the drawings or the orientation or positional relationship which the present invention product is usually put into use, it is only for convenience of describing the present application and simplifying the description, but it is not intended to indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation and be operated, and thus, should not be construed as limiting the present application.
Furthermore, the appearances of the terms "first," "second," and the like, if any, are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.
It should be noted that the features of the embodiments of the present application may be combined with each other without conflict.
In order to solve the aforementioned problems of unstable wire bonding caused by too long wire bonding of the upper chip in the multi-layer chip stacking structure in the prior art and the problem of easy collapse of the multi-layer chip stacking structure with a large number of layers, please refer to fig. 1, fig. 1 is a semiconductor package structure 1 provided in the embodiment of the present application, the semiconductor package structure 1 includes a substrate 10, a first supporting chip 11, a first stacked chip 12 and a filling adhesive 13, the substrate 10 includes a conductive adhesive 101, and the first stacked chip 12 includes a first vertical wire bonding 121.
The first supporting chip 11 is disposed at one side of the substrate 10.
The first stacked chip 12 is disposed on the first supporting chip 11 at a side away from the substrate 10, wherein the first vertical wire 121 is in contact with the first supporting chip 11 at the side.
The first vertical wire 121 is connected to the substrate 10 through the conductive adhesive 101.
The filling adhesive 13 is disposed between the first stacked chip 12 and the substrate 10, and the filling adhesive 13 wraps the first vertical wire 121.
The position of the conductive adhesive 101 on the substrate 10 is a bonding finger (i.e. gold finger) on the substrate 10, so that the first vertical wire 121 can be connected to the circuit of the substrate 10 through the conductive adhesive 101, and the bonding between the first vertical wire 121 and the substrate 10 is completed after the conductive adhesive 101 is cured. The filling adhesive 13 can be a non-conductive adhesive 101, the distance from the chip to the substrate 10 can be shortened by the arrangement of the first vertical routing 121 (the straight line between two points is shortest), the first vertical routing 121 can be wrapped by the arrangement of the filling adhesive 13, the first vertical routing 121 can be fixed and protected, the problem that the first vertical routing 121 is broken or bridged in the packaging process is prevented, furthermore, the filling adhesive 13 is arranged between the first stacked chip 12 and the substrate 10, and can play a supporting role for the first stacked chip 12 after curing, so that a multi-layer chip stacked structure formed by the first supporting chip 11 and the first stacked chip 12 has strong structural characteristics, and the problem that the chip is collapsed in the subsequent use is avoided.
On this basis, please refer to fig. 2, fig. 2 is a schematic structural diagram of a first stacked chip 12 according to an embodiment of the present disclosure.
The first stacked chip 12 further includes pins 122.
One end of the pin 122 is connected to the chip body of the first stacked chip 12, and the other end is connected to the first vertical wire 121.
In this embodiment of the present application, the first stacked chip 12 may be obtained by vertically wiring a pin (i.e., pad) of the normal chip by using a wire bonding principle, so as to replace the function of implementing a flip chip. The length of the first vertical wire 121 can refer to the distance from the side of the first supporting chip 11 away from the substrate 10 to the substrate 10, i.e. the distance from the side of the first supporting chip 11 away from the substrate 10 to the substrate 10 is the same as the length of the first vertical wire 121.
Based on the foregoing, the semiconductor package 1 further includes a second stacked chip 14, and the second stacked chip 14 includes a second vertical wire bond 141, as shown in fig. 3.
The second stacked chip 14 is disposed on the first stacked chip 12 at a side away from the first supporting chip 11, and the second vertical wire 141 is in contact with the first stacked chip 12.
The second vertical wire 141 is connected to the substrate 10 through the conductive adhesive 101.
The filling adhesive 13 is disposed between the second stacked chip 14 and the substrate 10, and the filling adhesive 13 wraps the second vertical bonding wire 141.
The second stacked chip 14 may be disposed on the first stacked chip 12 in an offset stacking manner, and the second stacked chip 14 may be an extension of a multi-layer chip stacked structure formed by the first supporting chip 11 and the first stacked chip 12, that is, it is understood that the disposing manner of the second stacked chip 14 on the first stacked chip 12 may be the same as the disposing manner of the first stacked chip 12 on the first supporting chip 11, and it should be understood that the bonding finger for connecting the second vertical bonding 141 with the substrate 10 through the conductive adhesive 101 may be the same as or different from the bonding finger for connecting the first vertical bonding 121 with the substrate 10 through the conductive adhesive 101, which is not limited herein. It should be understood that the multilayer chip stack structure formed by the first supporting chip 11, the first stacked chip 12 and the second stacked chip 14 may also extend continuously, the number of extending layers is not limited herein, and the offset directions of the first stacked chip 12 and the second stacked chip 14 may be consistent or not, and are not limited herein.
Through the above description, can obtain a stable in structure's multilayer chip stacked structure, when encapsulating, each perpendicular routing is protected by 13 parcel of filling adhesive, the condition such as fracture can not appear, and the multilayer flip chip that the slope set up has the support in 13 solidification back bottoms of filling adhesive, also can not appear in the use because of the unstable condition of collapsing that appears of multilayer chip stacked structure bottom sprag.
In order to more clearly describe the foregoing structure, referring to fig. 4, the semiconductor package structure 1 further includes a control chip 15, a second supporting chip 16, and a third stacked chip 17, where the third stacked chip 17 includes a third vertical wire 171;
the control chip 15 is disposed on one side of the substrate 10, and the second supporting chip 16 is disposed on the substrate 10 on a side of the control chip 15 away from the first supporting chip 11.
The third stacked chip 17 is disposed on the second supporting chip 16 at a side away from the substrate 10, wherein the third vertical wires 171 are in contact with the second supporting chip 16 at the side.
The third vertical wire 171 is connected to the substrate 10 through the conductive adhesive 101.
The filling adhesive 13 is disposed between the third stacked chip 17 and the substrate 10, and the filling adhesive 13 wraps the third vertical wire 171.
In the embodiment of the present application, in addition to the multilayer chip stack made up of the first support chip 11 and the first stacked chip 12 and the extension thereof provided on the substrate 10, the multilayer chip stack made up of the second support chip 16 and the third stacked chip 17 and the extension thereof may be provided. The first supporting chip 11, the first stacked chip 12, the second supporting chip 16 and the third stacked chip 17 may be memory chips, and the control chip 15 and the memory chip are connected by a circuit on the substrate 10 to implement a memory function of the semiconductor package structure 1.
The embodiment of the present application provides a method for manufacturing a semiconductor package structure, which is used to manufacture and form the semiconductor package structure 1, as shown in fig. 5, the method for manufacturing a semiconductor package structure is implemented through steps 201 to 205.
In step 202, a conductive adhesive 101 is disposed on the substrate 10 on one side of the first supporting chip 11.
In step 203, the first stacked chip 12 is disposed on a side of the first supporting chip 11 away from the substrate 10.
The offset direction of the first stacked chip 12 is the direction in which the first supporting chip 11 points to the conductive adhesive 101, and one side of the first vertical wire 121 is in contact with the first supporting chip 11.
In step 205, the filling adhesive 13 is filled into the gap between the first stacked chip 12 and the substrate 10 and the filling adhesive 13 is cured to fix the first vertical wire 121.
In the embodiment of the present application, after the first supporting chip 11 is disposed on the substrate 10, the conductive paste 101 may be disposed on the substrate 10 by dispensing on one side of the substrate 10 of the first supporting chip 11 by using a dispenser. The first vertical wire 121 of the first stacked chip 12 may be disposed on the first stacked chip 12 by using a vertical wire principle in advance, after the conductive adhesive 101 is disposed by dispensing, the first stacked chip 12 may be disposed on the first supporting chip 11 in a manner of offset stacking, so that the first vertical wire 121 contacts with the conductive adhesive 101, and after the conductive adhesive 101 is cured, the first vertical wire 121 is soldered to the substrate 10, thereby achieving communication between the first stacked chip 12 and the circuit of the substrate 10. The structure of the vertical wire bonding is not always maintained, the filling of the filling adhesive 13 can be performed after the welding is completed, the solidified filling adhesive 13 can ensure the stability of the first vertical wire bonding 121 during the packaging, and the first stacked chip 12 is supported to maintain the structural strength of the multilayer chip stacked structure, so that the collapse is prevented. Based on this, the semiconductor package structure 1 having the stable structure can be obtained.
In addition, the embodiments of the present application provide another detailed implementation of a method for manufacturing a semiconductor package structure.
The conductive adhesive 101 is disposed on a side of the conductive adhesive 101, which is connected to the substrate 10 by the first vertical wire 121 and is away from the first supporting chip 11.
The second stacked chip 14 is disposed on a side of the first stacked chip 12 away from the first supporting chip 11, wherein the second stacked chip 14 is offset in a direction in which the first supporting chip 11 points to the conductive adhesive 101, and a side of the second vertical wire 141 contacts the first stacked chip 12.
The second vertical wire 141 is connected to the conductive adhesive 101 and the conductive adhesive 101 is cured, so that the second stacked chip 14 is connected to the substrate 10 through the second vertical wire 141.
The filling adhesive 13 is filled into the gap between the second stacked chip 14 and the substrate 10 and the filling adhesive 13 is cured to fix the second vertical wire 141.
Through the steps, it can be understood that in the embodiment of the present application, the multilayer chip stacking structure may be extended through the steps, so as to obtain the multilayer chip stacking structure meeting the number of layers required by a user.
In order to more clearly describe the process of the aforementioned method for fabricating the semiconductor package structure, a more detailed flow of steps is provided below.
(1) wafer dicing: and cutting the whole wafer into single wafers along the cutting path by using laser/diamond, and attaching the FOW film to the back surface of the chip.
(2) Mounting the first support chip 11: the first support chip 11 is attached to the surface of the substrate 10 using a FOW film.
(3) Baking: the FOW film is cured by baking to fix the first supporting chip 11 on the surface of the substrate 10.
(4) Routing: the first supporting chip 11 is connected to the substrate 10 by a wire bonding method using copper/alloy/gold wires.
(5) Dispensing: and (4) utilizing a glue dispensing machine to dispense the conductive glue 101 on the routing finger.
(6) Mounting the first stacked chip 12: the first stacked chip 12 is attached to the first supporting chip 11, the first vertical wire 121 (vertical wire) at the bottom of the first stacked chip 12 is used to combine the first vertical wire 121 with the conductive adhesive 101, and the conductive adhesive 101 is cured by baking to complete the bonding of the first vertical wire 121 and the substrate 10.
(7) Dispensing: fill the height of the first vertical routing 121 arc at the bottom of the first stacked chip through the filling adhesive 13, achieve the purpose of protecting the bottom line arc, strengthen the intensity of the vertical line of the bottom area of the first stacked chip 12 through baking and solidifying the filling adhesive 13, realize upwards stacking, and utilize the filling adhesive 13 to strengthen the intensity of the multilayer chip stacked structure.
(8) Plastic packaging: and protecting the stacked chips by using a plastic packaging material.
(9) Printing: the required characters are engraved on the surface of the plastic package body by laser.
(10) Cutting: and cutting the plastic-sealed product into single pieces by using a cutting knife.
(11) package: and (4) putting the cut single products into a tray disc (material disc), and packaging and delivering the products out of the warehouse.
Through the above steps, the semiconductor package 1 can be obtained.
In summary, the embodiment of the present application provides a semiconductor package structure and a method for manufacturing the semiconductor package structure, where the semiconductor package structure includes a substrate, a first supporting chip, a first stacked chip and a filling adhesive, the substrate includes a conductive adhesive, and the first stacked chip includes a first vertical wire bonding; the first supporting chip is arranged on one side of the substrate; the first stacked chip is arranged on one side, far away from the substrate, of the first supporting chip in an offset stacking mode, wherein one side, where the first vertical routing is located, is in contact with the first supporting chip; the first vertical routing is connected with the substrate through the conductive adhesive; the filling adhesive is arranged between the first stacked chip and the substrate, wraps the first vertical routing, can ensure the stability of routing by arranging the first vertical routing and the filling adhesive, can keep the structural strength of the semiconductor packaging structure, and can obtain a stable semiconductor packaging structure.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present application should be covered within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (7)
1. A semiconductor packaging structure is characterized by comprising a substrate, a first supporting chip, a first stacked chip and filling glue, wherein the substrate comprises conductive glue, and the first stacked chip comprises a first vertical routing;
the first supporting chip is arranged on one side of the substrate;
the first stacked chip is arranged on one side, far away from the substrate, of the first supporting chip in an offset stacking mode, wherein one side, where the first vertical routing is located, is in contact with the first supporting chip;
the first vertical routing is connected with the substrate through the conductive adhesive;
the filling adhesive is arranged between the first stacked chip and the substrate, and wraps the first vertical routing.
2. The semiconductor package structure of claim 1, wherein the first stacked chip further comprises a pin;
one end of the pin is connected with the chip body of the first stacked chip, and the other end of the pin is connected with the first vertical routing.
3. The semiconductor package structure of claim 1, further comprising a second stacked die, the second stacked die comprising a second vertical wire bond;
the second stacked chip is arranged on one side of the first stacked chip far away from the first supporting chip in an offset stacking mode, and one side where the second vertical routing is located is in contact with the first stacked chip;
the second vertical routing is connected with the substrate through the conductive adhesive;
the filling adhesive is arranged between the second stacked chip and the substrate, and wraps the second vertical routing.
4. The semiconductor package structure of claim 3, wherein the first stacked die and the second stacked die have a uniform offset direction.
5. The semiconductor package structure of claim 1, further comprising a control chip, a second supporting chip, and a third stacked chip, wherein the third stacked chip comprises a third vertical wire bond;
the control chip is arranged on one side of the substrate, and the second supporting chip is arranged on the substrate on one side of the control chip far away from the first supporting chip;
the third stacked chip is arranged on one side, far away from the substrate, of the second supporting chip in an offset stacking mode, wherein one side, where the third vertical routing is located, is in contact with the second supporting chip;
the third vertical routing is connected with the substrate through the conductive adhesive;
the filling adhesive is arranged between the third stacked chip and the substrate, and wraps the third vertical routing.
6. A method for fabricating a semiconductor package structure, the method being used for fabricating and forming the semiconductor package structure of any one of claims 1-5, the method comprising:
providing a substrate, and arranging a first supporting chip on one side of the substrate;
arranging conductive adhesive on the substrate on one side of the first supporting chip;
arranging a first stacked chip on one side of the first supporting chip far away from the substrate, wherein the offset direction of the first stacked chip is the direction in which the first supporting chip points to the conductive adhesive, and one side where a first vertical routing is located is in contact with the first supporting chip;
connecting the first vertical routing with the conductive adhesive and solidifying the conductive adhesive so as to enable the first stacked chip to be communicated with the substrate through the first vertical routing;
filling glue into a gap between the first stacked chip and the substrate, and curing the filling glue to fix the first vertical routing.
7. The method of claim 6, further comprising:
arranging conductive adhesive on one side, away from the first supporting chip, of the conductive adhesive connected with the substrate through the first vertical routing;
arranging a second stacked chip on one side of the first stacked chip far away from the first supporting chip, wherein the offset direction of the second stacked chip is the direction in which the first supporting chip points to the conductive adhesive, and one side where a second vertical routing is located is in contact with the first stacked chip;
connecting the second vertical routing with the conductive adhesive and solidifying the conductive adhesive so as to enable the second stacked chip to be communicated with the substrate through the second vertical routing;
filling glue into a gap between the second stacked chip and the substrate and solidifying the filling glue so as to fix the second vertical routing.
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| CN2020104068475 | 2020-05-14 | ||
| CN202010406847.5A CN111554649A (en) | 2020-05-14 | 2020-05-14 | Semiconductor packaging structure and manufacturing method thereof |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006310649A (en) * | 2005-04-28 | 2006-11-09 | Sharp Corp | Semiconductor device package and its manufacturing method |
| US20140021605A1 (en) * | 2012-05-30 | 2014-01-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package on Package Devices and Methods of Packaging Semiconductor Dies |
| CN104795386A (en) * | 2014-01-16 | 2015-07-22 | 三星电子株式会社 | Semiconductor package including stepwise stacked chips |
| TW201943039A (en) * | 2018-03-27 | 2019-11-01 | 力成科技股份有限公司 | Semiconductor package and manufacturing method thereof |
| CN108369942B (en) * | 2015-12-30 | 2019-12-03 | 英帆萨斯公司 | Microelectronics Packaging |
-
2020
- 2020-05-14 CN CN202010406847.5A patent/CN111554649A/en active Pending
- 2020-08-06 CN CN202010780581.0A patent/CN111739862A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006310649A (en) * | 2005-04-28 | 2006-11-09 | Sharp Corp | Semiconductor device package and its manufacturing method |
| US20140021605A1 (en) * | 2012-05-30 | 2014-01-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package on Package Devices and Methods of Packaging Semiconductor Dies |
| CN104795386A (en) * | 2014-01-16 | 2015-07-22 | 三星电子株式会社 | Semiconductor package including stepwise stacked chips |
| CN108369942B (en) * | 2015-12-30 | 2019-12-03 | 英帆萨斯公司 | Microelectronics Packaging |
| TW201943039A (en) * | 2018-03-27 | 2019-11-01 | 力成科技股份有限公司 | Semiconductor package and manufacturing method thereof |
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