CN111726189B - Dual-core system clock synchronization method and device based on timestamp marking circuit - Google Patents
Dual-core system clock synchronization method and device based on timestamp marking circuit Download PDFInfo
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- CN111726189B CN111726189B CN202010556809.8A CN202010556809A CN111726189B CN 111726189 B CN111726189 B CN 111726189B CN 202010556809 A CN202010556809 A CN 202010556809A CN 111726189 B CN111726189 B CN 111726189B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0658—Clock or time synchronisation among packet nodes
- H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
- H04J3/0667—Bidirectional timestamps, e.g. NTP or PTP for compensation of clock drift and for compensation of propagation delays
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0658—Clock or time synchronisation among packet nodes
- H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
- H04J3/067—Details of the timestamp structure
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention discloses a dual-core system clock synchronization method and a dual-core system clock synchronization device based on a timestamp marking circuit, wherein the method comprises the following steps: the circuit based on the timestamp mark comprises a local clock unit, a frequency compensation register, a synchronous message/delay request detection circuit, a synchronous message/delay request time latch, a first base address data register, a second base address data register and a time event state register, wherein firstly, a CPU writes a frequency compensation value into the frequency compensation register through a bus interface and starts the local clock unit as a local clock reference; writing the address of the second base address data register into the first base address data register, and writing the address of the first base address data register into the second base address data register; the invention has the advantages that: the hardware circuit obtains the time stamp at the bottom layer, and the slave clock can quickly calculate and adjust the deviation with the master clock according to the receiving and sending time stamp to complete the synchronization of the master clock and the slave clock.
Description
Technical Field
The invention relates to the field of clock synchronization of an AIRT-ROS real-time system and a non-real-time system, in particular to a dual-core system clock synchronization method and device based on a timestamp marking circuit.
Background
At present, most clock synchronization algorithms are applied in clock synchronization under ethernet environment, for example, chinese patent publication No. CN103067112A, which discloses a clock synchronization method, apparatus and network device, and the apparatus includes: at least one hardware chip, a CPU and a logic control chip; the hardware chip is used for receiving a first PTP event message sent by the opposite terminal device, recording a first time stamp, subtracting the first time stamp from a correction value in a CF domain of the first PTP event message, and then sending the first time stamp to the CPU; the CPU is used for sending the first PTP event message to the logic control chip; the logic control chip is used for recording a PTP timestamp of the first PTP event message reaching the logic control chip, calculating a first time deviation between a first PTP system time of the logic control chip and a second PTP system time of the opposite terminal device according to the first PTP event message and the PTP timestamp, and performing clock synchronization with the opposite terminal device according to the first time deviation. The invention can improve the precision of clock synchronization, reduce the influence on the system efficiency and reduce the realization cost on hardware. However, the invention synchronizes clocks in a network, and is clock synchronization among a plurality of computers.
The network delay in the ethernet environment is one of the main factors to be considered by the clock synchronization algorithm, since the delay of ethernet may reach 50ms, the accuracy of clock synchronization is greatly affected, and the delay may generate large jitter due to different loads in the network. Therefore, the clock synchronization algorithm in the ethernet is not suitable for the clock synchronization of the dual-core dual system.
Disclosure of Invention
The technical problem to be solved by the present invention is how to provide a clock synchronization method and apparatus suitable for dual-core dual system.
The invention solves the technical problems through the following technical means: a dual-core system clock synchronization method based on a timestamp marking circuit is applied to an AIRT-ROS real-time system and a non-real-time system, the timestamp marking circuit comprises a local clock unit, a frequency compensation register, a synchronous message/delay request detection circuit, a synchronous message/delay request time latch, a first base address data register, a second base address data register and a time event state register, firstly, a CPU writes a frequency compensation value into the frequency compensation register through a bus interface, and starts the local clock unit to be used as a local clock reference; writing the address of the second base address data register into the first base address data register, and writing the address of the first base address data register into the second base address data register; the synchronous message/delay request detection circuit captures the message of the synchronous message/delay request message by detecting the write operation of the CPU to the first base address data register or the second base address data register to enable the latching function of the synchronous message/delay request time latch, the time event state register records the current time count value as the receiving and sending timestamp of the time message to generate time event interrupt, the CPU reads each timestamp of the time event state register and sets the time compensation value of the synchronous message or the delay request, thereby completing clock synchronization.
The invention provides a clock synchronization method suitable for a dual-core system by designing a timestamp marking circuit and carrying out clock synchronization based on the timestamp marking circuit, wherein a time event state register records the current time counting value as a receiving and sending timestamp of a time message, a hardware circuit acquires the timestamp at the bottom layer, errors caused by waiting CPU clock beats and scheduling at an operating system layer are reduced, and a slave clock can quickly calculate and adjust the deviation with a master clock according to the receiving and sending timestamp.
Furthermore, the first base address data register and the second base address data register are both array type ring buffers.
Furthermore, the AIRT-ROS real-time system and the non-real-time system include a real-time system and a non-real-time system, a master clock is set in the real-time system, a slave clock is set in the non-real-time system, the synchronization packet/delay request detection circuit captures a message of the synchronization packet/delay request packet by detecting a write operation of the master clock to the first base address data register to enable a latch function of the synchronization packet/delay request time latch, the time event status register generates a current time count value as a transmission/reception timestamp of the time packet and transmits the time stamp to the slave clock, the slave clock receives the message and extracts the timestamp therefrom, and the slave clock calculates a time deviation between the master clock and the slave clock according to the timestamp and adjusts and compensates the time deviation, thereby completing clock synchronization of the dual core system.
Still further, the master clock places a timestamp into the tail end of the first base address data register, and the slave clock removes data from the head end of the first base address data register, and when the tail end of the first base address data register is reached, the master clock wraps around to the head end of the first base address data register.
Furthermore, the message types required by the master clock and the slave clock in the clock synchronization process comprise a synchronization type, a following type, a delay request type and a delay reply type, the master clock periodically sends a synchronization type message, the time event state register generates a current time count value as a sending timestamp of a time message and sends a sending time t1 to the slave clock, and the slave clock receives the synchronization type message and records a time t2 when the synchronization type message is received; the slave clock sends a delay request type message to the master clock and records a sending time t3, at the moment, t3 is a pre-estimated value, the slave clock sends an actual timestamp for sending the delay request to the master clock, the master clock receives the following of the delay request, the time event state register generates a following time count value and returns a sending time t4 to the master clock, and after the process, the time deviation of the master clock and the slave clock is
The slave clock compensates for the time offset.
Furthermore, the AIRT-ROS real-time system and the non-real-time system include a real-time system and a non-real-time system, a master clock is set in the real-time system, a slave clock is set in the non-real-time system, the synchronization packet/delay request detection circuit captures a message of the synchronization packet/delay request packet by detecting a write operation from the slave clock to the second base address data register to enable a latch function of the synchronization packet/delay request time latch, the time event status register generates a current time count value as a transmission/reception timestamp of the time packet and transmits the time stamp to the master clock, the master clock receives the message and extracts the timestamp therefrom, and the master clock calculates a time deviation between the master clock and the slave clock according to the timestamp and adjusts and compensates the time deviation, thereby completing clock synchronization of the dual core system.
Still further, the slave clock places a message containing a timestamp into the tail end of the second base address data register, the master clock removes data from the head of the second base address data register, and the slave clock wraps around to the head of the second base address data register when the tail of the second base address data register is reached.
The invention also provides a dual-core system clock synchronization device based on a timestamp marking circuit, which is applied to an AIRT-ROS real-time system and a non-real-time system, wherein the timestamp marking circuit comprises a local clock unit, a frequency compensation register, a synchronous message/delay request detection circuit, a synchronous message/delay request time latch, a first base address data register, a second base address data register and a time event state register; writing the address of the second base address data register into the first base address data register, and writing the address of the first base address data register into the second base address data register; the synchronous message/delay request detection circuit captures the message of the synchronous message/delay request message by detecting the write operation of the CPU to the first base address data register or the second base address data register to enable the latching function of the synchronous message/delay request time latch, the time event state register records the current time count value as the receiving and sending timestamp of the time message to generate time event interrupt, the CPU reads each timestamp of the time event state register and sets the time compensation value of the synchronous message or the delay request, thereby completing clock synchronization.
Further, the first base address data register and the second base address data register are both array type ring buffers.
Furthermore, the AIRT-ROS real-time system and the non-real-time system include a real-time system and a non-real-time system, a master clock is set in the real-time system, a slave clock is set in the non-real-time system, the sync message/delay request detection circuit captures the message of the sync message/delay request message by detecting the write operation of the master clock to the first base address data register to enable the latch function of the sync message/delay request time latch, the time event status register generates the current time count value as the transmit-receive timestamp of the time message and transmits the time stamp to the slave clock, the slave clock receives the message and extracts the timestamp from the message, the slave clock calculates the time deviation between the master clock and the slave clock according to the timestamp and adjusts and compensates the time deviation, thereby completing the clock synchronization of the dual core system.
Still further, the master clock places a timestamp into the tail end of the first base address data register, and the slave clock removes data from the head end of the first base address data register, and when the tail end of the first base address data register is reached, the master clock wraps around to the head end of the first base address data register.
Furthermore, the message types required by the master clock and the slave clock in the clock synchronization process comprise a synchronization type, a following type, a delay request type and a delay reply type, the master clock periodically sends a synchronization type message, the time event state register generates a current time count value as a sending timestamp of a time message and sends a sending time t1 to the slave clock, and the slave clock receives the synchronization type message and records a time t2 when the synchronization type message is received; the slave clock sends a delay request type message to the master clock and records a sending time t3, at the moment, t3 is an estimated value, the slave clock sends an actual timestamp for sending the delay request to the master clock, the master clock receives the following of the delay request, the time event state register generates a following time count value and returns a sending time t4 to the master clock, and after the processes, the time deviation between the master clock and the slave clock is obtained
The slave clock compensates for the time offset.
Furthermore, the AIRT-ROS real-time system and the non-real-time system include a real-time system and a non-real-time system, a master clock is set in the real-time system, a slave clock is set in the non-real-time system, the sync message/delay request detection circuit captures the message of the sync message/delay request message by detecting the write operation from the slave clock to the second base address data register to enable the latch function of the sync message/delay request time latch, the time event status register generates the current time count value as the transmit-receive timestamp of the time message and transmits the time stamp to the master clock, the message is received and the timestamp is extracted from the master clock, the master clock calculates the time deviation between the master clock and the slave clock according to the timestamp and adjusts and compensates the time deviation, thereby completing the clock synchronization of the dual core system.
Still further, the slave clock places a message containing a timestamp into the tail end of the second base address data register, the master clock removes data from the head of the second base address data register, and the slave clock wraps around to the head of the second base address data register when the tail of the second base address data register is reached.
The invention has the advantages that:
(1) The invention provides a clock synchronization method suitable for a dual-core system by designing a timestamp marking circuit and carrying out clock synchronization based on the timestamp marking circuit, wherein a time event state register records the current time counting value as a receiving and sending timestamp of a time message, a hardware circuit acquires the timestamp at the bottom layer, errors caused by waiting CPU clock beats and scheduling at an operating system layer are reduced, and a slave clock can quickly calculate and adjust the deviation with a master clock according to the receiving and sending timestamp.
(2) The invention sets a master clock in the real-time system, sets a slave clock in the non-real-time system, the messages sent by the master clock and the slave clock are written to respective base address data registers, the master clock and the slave clock respectively read the time stamp in the message sent by the opposite terminal from the base address data register of the opposite terminal, the slave clock adjusts the self clock based on the time stamp of the master clock, completes the synchronization of the master clock and the slave clock, and solves the clock synchronization problem of the dual-core dual-system.
Drawings
FIG. 1 is a schematic diagram of a dual core system clock synchronization method based on a timestamp marking circuit according to an embodiment of the present invention;
fig. 2 is a block diagram of a design implementation of obtaining a timestamp from the interior of a physical layer in the dual core system clock synchronization method based on a timestamp marking circuit according to the embodiment of the present invention;
fig. 3 is a schematic circuit diagram of a clock processing portion in the dual core system clock synchronization method based on the timestamp marking circuit according to the embodiment of the present invention;
fig. 4 is a schematic diagram of master-slave clock synchronization in the dual-core system clock synchronization method based on the timestamp marking circuit according to the embodiment of the present invention;
fig. 5 is a schematic diagram of a clock synchronization state machine in the dual-core system clock synchronization method based on the timestamp marking circuit according to the embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the embodiments of the present invention, and it is obvious that the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example 1
As shown in fig. 1, which is a schematic diagram of a dual-core system clock synchronization method based on a timestamp marking circuit disclosed in embodiment 1 of the present invention, fig. 2 is a block diagram of a design implementation for obtaining a timestamp inside a physical layer, and in fig. 1, ring buffer represents a Ring buffer area, embodiment 1 of the present invention provides a dual-core system clock synchronization method based on a timestamp marking circuit, and the method process is described in detail below:
the clock synchronization method is applied to an AIRT-ROS real-time system and a non-real-time system, the circuit based on the timestamp mark comprises a local clock unit, a frequency compensation register, a synchronous message/delay request detection circuit, a synchronous message/delay request time latch, a first base address data register, a second base address data register and a time event state register, firstly, a CPU writes a frequency compensation value into the frequency compensation register through a bus interface, and starts the local clock unit to be used as a local clock reference; writing the address of the second base address data register into the first base address data register, and writing the address of the first base address data register into the second base address data register; the synchronous message/delay request detection circuit captures the message of the synchronous message/delay request message by detecting the write operation of the CPU to the first base address data register or the second base address data register to enable the latching function of the synchronous message/delay request time latch, the time event state register records the current time count value as the receiving and sending timestamp of the time message to generate time event interrupt, the CPU reads each timestamp of the time event state register and sets the time compensation value of the synchronous message or the delay request, thereby completing clock synchronization.
Several flag bits generated by the timestamp are: SOF _ TIMESTIMAGING _ TX _ SOFTWARE is generated in the device driver, representing the SOFTWARE timestamp of the packet, and the alias ts [0] is set. And a HARDWARE timestamp SOF _ TIMESTAMPING _ TX _ HARDWARE generated by the network card sets an alias th [0]. The timestamp SOF _ TIMESTAMPING _ RX _ softwave at which the received packet arrives at the kernel stack sets alias rs [0]. And the network card generates a HARDWARE timestamp SOF _ TIMESTAMTIMPING _ RX _ HARDWARE for receiving the packet, and sets an alias rh [0]. ts [0], rs [0] represents the sending/receiving time stamp generated by the software, the sending/receiving hardware time stamp is represented by th [0], rh [0], and ths [0] and rhs [0] respectively store the mapping from the sending/receiving hardware time stamp to the software time stamp. The maximum line rate of the SerDes (Serializer-Deserializer) of the FPGA can reach 12.5Gb/s, and can meet the rate requirement of 10.3125Gb/s of 10G Base-R Ethernet, so the FPGA is selected as a PHY (physical layer) transceiver. Fig. 2 is a block diagram of a design implementation for obtaining timestamps inside the PHY, including FIFO, clock processing, PCS (Physical Coding sub) and transceiver. Wherein FIFO completes the conversion from system side clock domain nclk to sending side clock domain and receiving side clock domain, refclk is external reference clock, ths [0]/rhs [0] saves the mapping from hardware time stamp to software time stamp; the software time stamp records the sending/receiving time by ts [0]/rs [0] respectively; the hardware time stamp records the transmission/reception time by th 0/rh 0, respectively. To avoid the jitter effect of the FIFO on the timestamp, the timestamp processing is placed inside the PHY between the FIFO and the PCS, making use of the fixed delays of the PCS and the transceiver. Thereby achieving the purpose of eliminating the delay jitter of the transmission path.
Two clocks Svs _ clk and Ref _ clk which are external inputs and are homologous to the system, sys _ clk is 156.25MHz and is used as an operating clock connected to the system side, ref _ clk is 161.1328125MHz and is a reference clock of an FPGA internal clock management unit, the two clocks generate a tx _ clock (161.1328125 MHz) and a high-speed serial clock in the transmission direction, and parallel data processing units (including a time stamp circuit) in the transmission direction all operate in the tx _ clock domain. The Clock Data Recovery (CDR) in the receiving direction generates a parallel line clock rx _ clock (161.1328125 MHz) and a high-speed serial clock, and the parallel data processing units (including the time stamp circuits) in the receiving direction all work in the rx _ clock domain. The receiving clock locks the sending clock frequency of the far end through the CDR, so that the influence of the frequency deviation between the sending end and the receiving end on the time stamp is avoided.
After a data message from a system is converted into a clock domain of a transmission line through a TX FIFO, the data message is analyzed and a new timestamp is marked, then 64B/66B coding is carried out on a 64-bit data stream according to the standard requirement of 10G Base-R PCS of IEEE 802.3 according to a 64B/66B coding table to form a 66-bit code stream, and then scrambling is carried out on a high 64-bit payload in the code stream. Because the high-speed transceiver can not process the 66bit code stream directly, the code stream after scrambling also needs to be sent into the gearbox to complete the conversion from 66bit to 64bit, and an enabling signal of the transmission line clock is generated, namely, after every 32 continuous clock beats, one clock beat is paused to adapt to the code stream rate of the transmission line, and finally, the serialization of the data stream is completed through the transceiver.
Firstly, deserializing of a data stream is completed through a transceiver, then code stream conversion from 64bit to 66bit is completed, namely, after every 32 continuous clock beats, one clock beat is paused, so that the code stream rate of a receiving line can be ensured to be adaptive. And then completing the synchronous processing of the 66-bit code stream block, carrying out descrambling, and carrying out 64B/66B decoding on the descrambled 66-bit code stream so as to obtain a 64-bit data stream. And analyzing the message, marking a timestamp, finally completing the conversion from the receiving line clock to the system clock domain through FIFO, and sending the converted message to the system to complete the data processing of a higher layer.
The clock processing part circuit comprises a four-Channel phase-locked loop (QPLL, quad PLL) based on LC and a Channel phase-locked loop (CPLL, channel PLLs) based on four rings as shown in figure 3. The present invention takes into account the different line speeds: when the line speed exceeds 6.5Gb/s, QPLL is used. The linear speed is between 0.6 Gb/s and 6.5Gb/s, and QPLL/CPLL is selected. QPLL is LC tank and CPLL is Ring, preferably QPLL. The clock processing module maintains a local timestamp counter comprising a 32bit second count and a 30bit nanosecond count. The upper 16 bits of the 48bit second count required in the timestamp message are given by the operating system. When the operating system sends a timestamp message, the upper 16 bits of the timestamp are set by the operating system, and the lower 32 bits are set to 0. When the time stamp message is sent to the PHY, the message analysis hardware detects the clock of the time stamp message, when the message is sent out, the local time stamp is written into the time stamp message, and relevant CRC and CHKSUM values are modified. In the message receiving direction, there is also message parsing hardware. After the timestamp message is analyzed, the accurate timestamp of the received message can be inserted into the message or reported through a control interface.
Continuing with fig. 1, the AIRT-ROS includes a real-time system and a non-real-time system, a master clock is set in the real-time system, a slave clock is set in the non-real-time system, a physical layer of the AIRT-ROS is close to based on a timestamp marking circuit, the synchronization message/delay request detection circuit captures a message of the synchronization message/delay request message by detecting a write operation of the master clock to a first base address data register to enable a latch function of the synchronization message/delay request time latch, a time event status register generates a current time count value as a transceiving timestamp of the time message and transmits the timestamp to the slave clock, the slave clock receives the message and extracts the timestamp therefrom, and the slave clock calculates a time deviation between the master clock and the slave clock according to the timestamp and adjusts and compensates the time deviation, thereby completing clock synchronization of the dual core system. The first base address data register and the second base address data register are both array type annular buffer areas, and the process of receiving messages by the slave clock and extracting the time stamps from the master clock is as follows: the master clock will place a timestamp into the end of the first base address data register while the slave clock removes data from the head of the first base address data register, the master clock wrapping around to the head of the first base address data register when the end of the first base address data register is reached.
The synchronous message/delay request detection circuit captures the message of the synchronous message/delay request message by detecting the write operation from the slave clock to the second base address data register to enable the latching function of the synchronous message/delay request time latch, the time event state register generates the current time count value as the receiving and sending time stamp of the time message and sends the time stamp to the master clock, the master clock receives the message and extracts the time stamp from the message, and the master clock calculates the time deviation between the master clock and the slave clock according to the time stamp and adjusts and compensates the time deviation, thereby completing the clock synchronization of the dual-core dual-system. The process of the master clock receiving the message and extracting the timestamp from the slave clock is: the slave clock places a message containing a timestamp into the tail end of the second base address data register, the master clock removes data from the head of the second base address data register, and the slave clock wraps around to the head of the second base address data register when the tail end of the second base address data register is reached.
It should be noted that the first base address data register and the second base address data register are both array type Ring buffers, i.e., ring buffers. The key for synchronizing the clocks of the AIRT-ROS real-time system and the non-real-time system is to rapidly read the message sent by the master clock and the slave clock based on a Ring buffer structure developed on a memory. Ring buffer is a circular buffer, first, ring buffer is an array, faster than a linked list, and has an easily predictable access pattern. The memory addresses of the elements in the Ring buffer are stored contiguously. Friendly to CPU cache, as long as one element in Ring buffer is loaded to a cache line, other adjacent elements can be loaded to the same cache line. The non-real-time operating system pre-allocates memory for Ring buffer so that the array object always exists. Without the need to spend a significant amount of time for waste recovery. In addition, unlike the linked list, a one-to-one node object needs to be created for each object added to the link list, and when a node is deleted, a corresponding memory cleaning operation needs to be performed. The non-real-time operating system applies for two Ring buffers, wherein one Ring buffer is used for a master clock to put in a message, and a slave clock acquires the message: the master clock puts the message into the tail of the Ring buffer and the slave clock removes the data from the other end of the Ring buffer, and when the Tail of the Ring buffer is reached, the master clock wraps back to the head of the Ring buffer. Another is for the slave clock to put in the message, the master clock obtains the message: the slave clock puts the message into the tail of the Ring buffer and the master clock removes the data from the other end of the Ring buffer, wrapping from the slave clock back to the head of the Ring buffer when the Tail of the Ring buffer is reached.
The message types required by the master clock and the slave clock in the clock synchronization process include a synchronization type (Sync), a following type (PDelay _ Resp _ Follow _ Up, which is a following message that substantially pre-determines a Delay response, and is referred to as following for short), a Delay request type (PDelay _ Resp, which is a response that substantially pre-determines a Delay request, and is referred to as Delay request for short), and a Delay reply type (Delay _ Resp), and further include a notification (notification) and Management messages (Management messages), where the messages include two types, i.e., a general message and an event message. The following type and the delayed reply type belong to a common message, the common message does not carry out time stamp processing, and the following type and the delayed reply type can carry accurate sending or receiving time value information of the event message. The synchronization type and the delay request type belong to event messages, the event messages are time-sensitive messages and need to be stamped with accurate time stamps, wherein the synchronization type is periodically sent from a master clock (generally once every two seconds) and contains clock attributes required by a master clock algorithm, and the synchronization type time stamps are sent by subsequent following types. Sync: the synchronous message is sent to the slave equipment by the master equipment, and the message can contain a Sync sending time tag; PDelay _ Req is an estimated time tag for requesting the opposite end to reply the message, and the time tag is embedded in the request message PDelay _ Req; the Announce broadcasts the state and characteristic information of the sending node and the advanced main clock; requesting the opposite end to return a time tag which is replied when the opposite end predicts the receiving of the PDelay _ Req message, wherein the time tag is embedded in a response message PDelay _ Resp; PDelay _ Resp _ Follow _ Up, namely predicting the timestamp of the Follow message of delayed reply; management-transmitting information for managing a clock device and a command. Delay Req: requesting the opposite end to return a time tag when the Delay Req message is received, wherein the time tag is embedded in a response message Delay Resp; follow Up: a send time for transmitting the Sync message; delay Resp: in response to Delay req, the band sends a time stamp. The header of the message is defined, including version, scope, message type, identifier, sequence number, control word, etc., and the header message definition is shown in table 1. Defining a synchronization type and a delay request type, including a timestamp, a deviation from a world standard time, a communication protocol, a master clock port, a master clock grade, a master clock to be selected and the like, wherein synchronization and delay request messages are defined as shown in table 2. The following type carries the timestamp of the Syn packet, as shown in table 3.
Table 1 header message definition
TABLE 2 synchronization and delay requests
TABLE 3 delayed response
As shown in fig. 4, the clock synchronization process is further refined according to the definition of the message type: the master clock periodically sends the synchronous type message, the time event state register generates the current time count value as the sending time stamp of the time message and sends the sending time t1 to the slave clock, the slave clock receives the synchronous type message and records the time t2 of receiving the synchronous type message; the slave clock sends a delay request type message to the master clock and records a sending time t3, at the moment, t3 is a pre-estimated value, the slave clock sends an actual timestamp for sending the delay request to the master clock, the master clock receives the following of the delay request, the time event state register generates a following time count value and returns a sending time t4 to the master clock, and after the process, the time deviation of the master clock and the slave clock is
The slave clock compensates for the time offset. Sync, PDelay _ Req, PDelay _ Resp _ Follow _ Up record four timestamps t1, t2, t3, t4, respectively. Due to the difference of the internal scheduling mechanism of the master-slave clock, the difference of the message sending/receiving delay can cause the difference between the master clock and the slave clock to be determined, namely, the difference of the delay from the master clock to the slave clock and the delay from the slave clock to the master clock. When a non-real-time operating system completes an executing task, its time stamp acquisition is delayed, which in some cases can be quite long, even on the order of milliseconds. Therefore, the master and slave clocks need to be synchronized by calculating the offset time a plurality of times.
As shown in fig. 5, the main states of the clock synchronization of the present invention include: initializing, (preparing) a master clock, a slave clock, an uncalibrated state and a monitoring state, wherein the master clock and the slave clock start from any state, bootstrap to be the master clock or the slave clock according to the type of the current operating system (if the master clock of the real-time operating system and the non-real-time operating system is the slave clock), and enter the initialization state; when an error is encountered, or the master clock actively initiates a disable instruction, the state enters a disable state (non-working state). Sending out an enabling instruction from the de-enabling state, wherein the enabling instruction indicates that the master clock and the slave clock need to return to the initial state again; if the real-time system is restarted, the main clock firstly enters an initialization state, then is bootstrapped to be the main clock, enters a prepared main clock state, then is distributed with a ring buffer to enter the prepared main clock state, and is prepared to send and receive messages; master clock state: the master clock starts sending sync, followUp messages and prepares to accept the DelayReq (delay request) of the slave clock. A state decision event refers to: sync, followUp, delayReq, delayResp, response to a deferred request. The slave clock is not calibrated, and the listening state indicates that the clock of the slave clock is not synchronized with the master clock and needs to be continuously synchronized. Successful synchronization of the slave clock indicates that the master and slave clocks are already synchronized.
Through the technical scheme, the master clock is arranged in the real-time system, the slave clock is arranged in the non-real-time system, messages sent by the master clock and the slave clock are written to respective memories, the master clock and the slave clock respectively read the timestamp in the message sent by the opposite terminal from the memory of the opposite terminal, the slave clock adjusts the self clock based on the timestamp of the master clock, the master clock and the slave clock are synchronized, and the dual-core dual-system clock synchronization problem is solved.
Example 2
Corresponding to embodiment 1 of the present invention, embodiment 2 of the present invention further provides a dual-core system clock synchronization apparatus based on a timestamp marking circuit, which is applied to an AIRT-ROS real-time system and a non-real-time system, wherein the timestamp marking circuit includes a local clock unit, a frequency compensation register, a synchronization packet/and delay request detection circuit, a synchronization packet/delay request time latch, a first base address data register, a second base address data register, and a time event status register, and first, a CPU writes a frequency compensation value into the frequency compensation register through a bus interface, and starts the local clock unit as a local clock reference; writing the address of the second base address data register into the first base address data register, and writing the address of the first base address data register into the second base address data register; the synchronous message/delay request detection circuit captures the message of the synchronous message/delay request message by detecting the write operation of the CPU to the first base address data register or the second base address data register to enable the latching function of the synchronous message/delay request time latch, the time event state register records the current time count value as the receiving and sending timestamp of the time message to generate time event interrupt, the CPU reads each timestamp of the time event state register and sets the time compensation value of the synchronous message or the delay request, thereby completing clock synchronization.
Specifically, the first base address data register and the second base address data register are both array type ring buffers.
Specifically, the AIRT-ROS real-time system and the non-real-time system include a real-time system and a non-real-time system, a master clock is set in the real-time system, a slave clock is set in the non-real-time system, the synchronization packet/delay request detection circuit captures a message of a synchronization packet/delay request packet by detecting a write operation of the master clock to a first base address data register to enable a latch function of a synchronization packet/delay request time latch, a time event status register generates a current time count value as a transmission/reception timestamp of a time packet and transmits the time stamp to the slave clock, the slave clock receives the message and extracts the timestamp from the slave clock, and the slave clock calculates a time deviation between the master clock and the slave clock according to the timestamp and adjusts and compensates the time deviation, thereby completing clock synchronization of the dual core system.
Specifically, the master clock places a timestamp into the tail end of the first base address data register, and the slave clock removes data from the head of the first base address data register, and when the tail end of the first base address data register is reached, the master clock wraps around to the head of the first base address data register.
Specifically, the message types required by the master clock and the slave clock in the clock synchronization process include a synchronization type, a following type, a delay request type and a delay reply type, the master clock periodically sends a synchronization type message, the time event state register generates a current time count value as a sending timestamp of a time message and sends a sending time t1 to the slave clock, and the slave clock receives the synchronization type message and records a time t2 when the synchronization type message is received; when the slave clock gives the masterThe clock sends a delay request type message and records a sending time t3, at the moment, t3 is a predicted value, the slave clock sends an actual timestamp for sending the delay request to the master clock, the master clock receives the following of the delay request, the time event state register generates a following time count value and returns a sending time t4 to the master clock, and after the processes, the time deviation between the master clock and the slave clock is obtained as
The slave clock compensates for the time offset.
Specifically, the AIRT-ROS real-time system and the non-real-time system include a real-time system and a non-real-time system, a master clock is set in the real-time system, a slave clock is set in the non-real-time system, the sync message/delay request detection circuit captures a message of a sync message/delay request message by detecting a write operation from the slave clock to the second base address data register to enable a latch function of the sync message/delay request time latch, the time event status register generates a current time count value as a transmit-receive timestamp of the time message and transmits the timestamp to the master clock, the message is received at the master clock and a timestamp is extracted therefrom, and the master clock calculates a time deviation between the master clock and the slave clock according to the timestamp and adjusts and compensates the time deviation, thereby completing clock synchronization of the dual core system.
Specifically, the slave clock puts a message containing a timestamp into the tail end of the second base address data register, the master clock removes data from the head of the second base address data register, and when the tail end of the second base address data register is reached, the slave clock wraps around to the head of the second base address data register.
The above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (8)
1. The dual-core system clock synchronization method based on the timestamp marking circuit is characterized by being applied to an AIRT-ROS real-time system and a non-real-time system, wherein the timestamp marking circuit comprises a local clock unit, a frequency compensation register, a synchronous message/delay request detection circuit, a synchronous message/delay request time latch, a first base address data register, a second base address data register and a time event state register; writing the address of the second base address data register into the first base address data register, and writing the address of the first base address data register into the second base address data register; the synchronous message/delay request detection circuit captures the message of the synchronous message/delay request message by detecting the write operation of the CPU to the first base address data register or the second base address data register to enable the latching function of the synchronous message/delay request time latch, the time event state register records the current time count value as the receiving and sending time stamp of the time message to generate time event interrupt, the CPU reads each time stamp of the time event state register and sets the time compensation value of the synchronous message or the delay request, thereby completing clock synchronization;
the AIRT-ROS real-time system and the non-real-time system comprise a real-time system and a non-real-time system, a master clock is arranged in the real-time system, a slave clock is arranged in the non-real-time system, the synchronous message/delay request detection circuit captures the message of a synchronous message/delay request message by detecting the writing operation of the master clock to a first base address data register to enable the latching function of a synchronous message/delay request time latch, a time event state register generates the current time counting value to be used as a receiving and sending time stamp of a time message and sends the receiving and sending time stamp to the slave clock, the message is received and the time stamp is extracted from the slave clock, the slave clock calculates the time deviation between the master clock and the slave clock according to the time stamp and adjusts and compensates the time deviation, and thereby the clock synchronization of the dual-core system is completed.
2. The dual core system clock synchronization method based on time stamp marking circuit as claimed in claim 1, wherein said first and second base address data registers are both array type ring buffers.
3. The dual system clock synchronization method based on timestamp marking circuits according to claim 1, wherein said master clock puts a timestamp containing data into the tail end of the first base address data register, and removes data from the head of the first base address data register from the slave clock, and when the tail end of the first base address data register is reached, the master clock wraps around to the head of the first base address data register.
4. The dual-core system clock synchronization method based on the timestamp marking circuit according to claim 1, wherein the message types required by the master clock and the slave clock in the clock synchronization process include a synchronization type, a following type, a delay request type and a delay reply type, the master clock periodically sends the synchronization type message, the time event status register generates the current time count value as the sending timestamp of the time message and sends the sending time t1 to the slave clock, the slave clock receives the synchronization type message and records the time t2 when the synchronization type message is received; the slave clock sends a delay request type message to the master clock and records a sending time t3, at the moment, t3 is an estimated value, the slave clock sends an actual timestamp for sending the delay request to the master clock, the master clock receives the following of the delay request, the time event state register generates a following time count value and returns a sending time t4 to the slave clock, and after the processes, the time deviation between the master clock and the slave clock is obtained as
The slave clock compensates for the time offset.
5. The dual-core system clock synchronization method based on the timestamp marking circuit as claimed in claim 2, wherein the AIRT-ROS real-time system and the non-real-time system include a real-time system and a non-real-time system, a master clock is set in the real-time system, a slave clock is set in the non-real-time system, the synchronization message/delay request detection circuit captures the message of the synchronization message/delay request message by detecting the write operation of the slave clock to the second base address data register to enable the latch function of the synchronization message/delay request time latch, the time event status register generates the current time count value as the transceiving timestamp of the time message and transmits the timestamp to the master clock, the master clock receives the message and extracts the timestamp therefrom, and the master clock calculates the time deviation between the master clock and the slave clock according to the timestamp and adjusts and compensates the time deviation, thereby completing the clock synchronization of the dual-core system.
6. The dual core system clock synchronization method based on timestamp marking circuits of claim 5, wherein the slave clock places a message containing a timestamp into the tail end of the second base address data register, the master clock removes data from the head of the second base address data register, and the slave clock wraps around to the head of the second base address data register when the tail end of the second base address data register is reached.
7. The dual-core system clock synchronization device based on the timestamp marking circuit is characterized by being applied to an AIRT-ROS real-time system and a non-real-time system, wherein the timestamp marking circuit comprises a local clock unit, a frequency compensation register, a synchronous message/delay request detection circuit, a synchronous message/delay request time latch, a first base address data register, a second base address data register and a time event state register; writing the address of the second base address data register into the first base address data register, and writing the address of the first base address data register into the second base address data register; the synchronous message/delay request detection circuit captures the message of the synchronous message/delay request message by detecting the write operation of the CPU to the first base address data register or the second base address data register to enable the latching function of the synchronous message/delay request time latch, the time event state register records the current time count value as the receiving and sending timestamp of the time message to generate time event interrupt, the CPU reads each timestamp of the time event state register and sets the time compensation value of the synchronous message or the delay request, thereby completing clock synchronization;
the AIRT-ROS real-time system and the non-real-time system comprise a real-time system and a non-real-time system, a main clock is arranged in the real-time system, a slave clock is arranged in the non-real-time system, the synchronous message/delay request detection circuit captures the message of the synchronous message/delay request message by detecting the write operation of the main clock to a first base address data register so as to enable the latching function of a synchronous message/delay request time latch, a time event state register generates the current time counting value as the receiving and sending time stamp of the time message and sends the receiving and sending time stamp to the slave clock, the message is received and the time stamp is extracted from the slave clock, the slave clock calculates the time deviation of the main clock and the slave clock according to the time stamp and adjusts and compensates the time deviation, and therefore the clock synchronization of the dual-core and dual system is completed.
8. The dual system clock synchronization apparatus based on timestamp marking circuits according to claim 7, wherein said first and second base address data registers are both array type ring buffers.
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