JP6516217B2 - Synchronization message transmitter, time synchronization system, synchronization message transmission method and program - Google Patents

Description

  The present invention relates to a synchronous message transmission device, a time synchronization system, a synchronous message transmission method, and a program.

  In an asynchronous network such as Ethernet (registered trademark), IEEE 1588 v2 (Precision Time Protocol, hereinafter referred to as PTP) is known as a time synchronization means. In PTP, Grandmaster Clock (GMC) has extremely accurate time information obtained from GNSS (Global Navigation Satellite System (s), Global Navigation Satellite System), etc. in a format specified by PTP. A time synchronization packet is stamped and transmitted to a slave that is a time synchronization target device. The slave can obtain the frequency, phase, and absolute time information synchronized with the GMC by receiving a packet from the GMC and performing an operation determined by the PTP.

When time synchronization is performed between GMC and a slave by PTP, delay and fluctuation of transmission time in the network and fluctuation of transmission interval of time synchronization packet in GMC are factors that lower the accuracy of time synchronization.
Among these, regarding the delay and fluctuation of the transmission time in the network, a countermeasure using transparent clock (Transparent Clock (TC)) and boundary clock (Boundary Clock (BC)) has been proposed in IEEE 1588 v2.

Further, in relation to the improvement of time synchronization accuracy, the time synchronization system described in Patent Document 1 performs processing other than time synchronization processing with a time synchronization processing unit that performs time synchronization processing by communicating time synchronization packets. A master that has a main processing unit and assigns different IP addresses to the time synchronization processing unit and the main processing unit, and when communicating with the main processing unit among the masters, communication of a normal packet to the IP address of the main processing unit When performing time synchronization communication, connect multiple slaves that communicate time synchronization packets to the IP address of the time synchronization processing unit, and the master and the slave, and distribute packets to be communicated for each IP address, The relay apparatus provided with the 1st buffer and the 2nd buffer for every IP address is provided.
According to Patent Document 1, with such a configuration, even when packets are concentrated, the time synchronization accuracy is improved by reducing variations in network delay.

JP, 2013-143748, A

In order to improve the accuracy of time synchronization between GMC and slaves, measures are also required for fluctuations in the transmission interval of time synchronization packets in GMC. In particular, if the GMC is transmitting a packet other than the time synchronization packet when the transmission timing of the time synchronization packet arrives, the time synchronization packet is sent by waiting for the transmission completion of the packet being transmitted and transmitting the time synchronization packet. Transmission delays, and fluctuations occur in the transmission interval of time synchronization packets.
As a countermeasure against the transmission delay of the synchronization packet and the fluctuation of the transmission interval, a method of transmitting the synchronization packet and the packets other than the synchronization packet with different IP addresses can be considered using the technique described in Patent Document 1. However, in this method, it is necessary to assign a plurality of IP addresses to the GMC, and management of the IP addresses becomes complicated.

  The present invention reduces fluctuations in the transmission interval of time synchronization packets in a GMC (grand master clock device) without the need to use separate IP addresses for transmission of time synchronization packets and transmission of packets other than time synchronization packets. The present invention provides a synchronous message transmission device, a time synchronization system, a synchronous message transmission method, and a program.

According to a first aspect of the present invention, a synchronous message transmitting apparatus is a synchronous message transmitting apparatus that transmits a synchronous message including time information, which is executed by a CPU to obtain information on the synchronous message transmission interval. and sync registration processing unit, and the CPU operates with the high accuracy clock signal than the clock signal to be used, the synchronization message and sending unit for sending a general message is a message other than the synchronization message, the CPU A scheduler that operates using a clock signal that is more accurate than the clock signal used by the device, and determines whether it is the transmission timing of the synchronization message based on the information of the transmission interval of the synchronization message acquired by the Sync registration processing unit And the sending unit is configured to send the synchronization message by the scheduler unit. If it is determined that it is timing, the transmission of the new synchronization message and the general message is suppressed, and the synchronization message is transmitted after a specified time defined as the time required for the transmission of the general message has elapsed.
A synchronization message generation unit that generates the synchronization message, and a general message generation unit that generates a general message that is a message other than the synchronization message, the synchronization message generation unit being a layer lower than the general message generation unit May be provided.

The first counter that counts each interval defined as the minimum value of the synchronization message transmission interval for the same time synchronization target device, and the minimum value of the synchronization message transmission interval for the same time synchronization target device The scheduler unit is specified by the value of the second counter among the information of the synchronization message transmission timing set for each of the time synchronization target devices , and includes a second counter for counting at intervals divided by a number. It is determined whether it is the timing to send a synchronization message to the time synchronization target device based on comparison of the information of the synchronization message transmission timing of the time synchronization target device with the value of the first counter, and the transmission Section determines that it is the timing at which the scheduler section sends out a synchronization message. Sends a synchronization message, it may be.

  The specified time may be the maximum time required to send a general message.

According to a second aspect of the present invention, a time synchronization system includes a synchronization message transmission device and a time synchronization target device, and the synchronization message transmission device transmits a synchronization message including time information. A Sync registration processing unit that is executed by the CPU and acquires information on the transmission interval of the synchronization message, and operates using a clock signal that is more accurate than the clock signal used by the CPU, the synchronization message, and A sending unit that sends a general message that is a message other than the synchronization message, and a clock signal that is more accurate than a clock signal used by the CPU , and that sends the synchronization message acquired by the Sync registration processing unit It is determined whether or not it is the transmission timing of the synchronization message based on the information of the interval. And the sending unit suppresses sending of a new synchronization message and a general message when the scheduler unit determines that it is a sending timing of a synchronization message, and defines the time required for sending the general message. The synchronization message is sent out after the specified period of time has passed, and the time synchronization target device performs time synchronization with the synchronization message transmission device based on the synchronization message sent by the synchronization message transmission device. .

According to a third aspect of the present invention, a synchronization message transmission method is a synchronization message transmission method of a synchronization message transmission device for transmitting a synchronization message including time information, which is executed by a CPU, and the transmission interval of the synchronization message. Obtaining information , and sending out a synchronous message and a general message which is a message other than the synchronous message, operating using a clock signal that is more accurate than the clock signal used by the CPU . Operating using a clock signal that is more accurate than a clock signal used by the CPU, and determining whether it is a transmission timing of the synchronization message based on information of the transmission interval of the synchronization message. In the sending step, the sending step of the synchronization message in the determining step If it is determined that the timing is "imming", the transmission of the new synchronization message and the general message is suppressed, and the synchronization message is transmitted after a predetermined time defined as the time required for the transmission of the general message has elapsed.

According to a fourth aspect of the present invention, the program is executed by a CPU in a computer that controls a synchronization message transmitting apparatus that transmits a synchronization message including time information, and acquires information on the transmission interval of the synchronization message. When, than the clock signal the CPU is used to operate with a high-precision clock signal, the synchronization message, and a sending step of sending the general message is a message other than the synchronization message, the clock signals the CPU is used Operating using a clock signal with a higher accuracy than that, and determining whether it is a transmission timing of the synchronization message based on the information of the transmission interval of the synchronization message, and If it is the transmission timing of the synchronization message in the determination step It is a program for suppressing transmission of a new synchronization message and a general message, and transmitting the synchronization message after a predetermined time defined as the time required for transmission of the general message has elapsed.

  According to the present invention, it is possible to reduce the fluctuation of the transmission interval of the time synchronization packet in the GMC without having to use separate IP addresses for the transmission of the time synchronization packet and the transmission of packets other than the time synchronization packet.

It is a schematic block diagram which shows the apparatus structure of the time synchronization system in one Embodiment of this invention. It is explanatory drawing which shows the hierarchical structure in IEEE1588v2 time synchronization process. It is a schematic block diagram which shows the example of a structure of the conventional grand master clock apparatus. It is explanatory drawing which shows the example of the delay and fluctuation | variation in the synchronous message which the conventional grand master clock apparatus sends. It is explanatory drawing which shows the hierarchical structure in the time synchronization process of the embodiment. It is a schematic block diagram which shows the structural example of the grand master clock apparatus in the embodiment. It is explanatory drawing which shows the example of the delay in the synchronous message which the grand master clock apparatus in the embodiment sends. It is explanatory drawing which shows the format of the synchronous message of IEEE1588v2. It is explanatory drawing which shows the example of the data structure of the global profile which the global profile memory | storage part in the embodiment memorize | stores. It is explanatory drawing which shows the example of the data structure of the SMID profile which the SMID profile memory | storage part in the embodiment memorize | stores. It is explanatory drawing which shows the example of the data structure of the SMID table which the SMID table memory | storage part in the embodiment memorize | stores. It is a schematic block diagram which shows the function structure of the MAC part in the embodiment. It is explanatory drawing which shows the example of the data structure of the synchronous message in the embodiment. FIG. 8 is an explanatory view showing an example of a transmission interval of a synchronization message in a network in which a plurality of slave devices exist in the same embodiment. It is explanatory drawing which shows the example of the data structure of the SMID table in the embodiment. It is explanatory drawing which shows the example of operation | movement of the scheduler in the embodiment. It is explanatory drawing which shows the example of the flow of data at the time of synchronous message transmission in the embodiment. FIG. 14 is an explanatory view showing an example of an operation performed by the Sync sending unit in the case of the forced discard method in the embodiment. FIG. 14 is an explanatory view showing an example of an operation performed by the Sync sending unit in the case of the high priority sending method in the embodiment. FIG. 14 is an explanatory diagram showing an example of an operation performed by the Sync sending unit in the case of the transmission time reservation method in the embodiment. In the same embodiment, it is an explanatory view showing how much transmission standby occurs in the transmission time reservation method.

Hereinafter, although the embodiment of the present invention is described, the following embodiment does not limit the invention concerning a claim. Moreover, not all combinations of features described in the embodiments are essential to the solution of the invention.
FIG. 1 is a schematic block diagram showing an apparatus configuration of a time synchronization system according to an embodiment of the present invention. In the same figure, the time synchronization system 1 comprises a Grandmaster Clock device 100, an antenna 200, a Transparent Clock device 300, and one or more slave devices 400.

Grand master clock device 100 and transparent clock device 300 are connected via network 810. The transparent clock device 300 and the slave device 400 are also connected via the network 810. The transparent clock device 300 and the slave device 400 may be connected via the L2 switch 820 in addition to the network 810. In relation to the grand master clock device 100 and the slave device 400, the transparent clock device 300, the L2 switch 820 and the network 810 are included in the communication path 800 connecting the grand master clock device 100 and the slave device 400.
Also, the antenna 200 receives positioning information obtained from the positioning system 900, and the antenna 200 is connected to the grand master clock device 100.

The network 810 is an asynchronous communication network, such as a communication network by Ethernet (registered trademark), for example.
The positioning system 900 is a positioning system using satellites (Global Navigation Satellite System; GNSS, Global Navigation Satellite System). Examples of the positioning system 900 may include, but not limited to, GPS (Global Positioning System), Quasi Zenith Satellite System (QZSS), or Global Navigation Satellite System (GLONASS). The positioning system 900 is a system that performs triangulation based on high precision time and navigation information of satellite as the principle of positioning, and the time is always so that the time coincides with several cesium atomic clocks installed on the ground We are correcting the information. The time synchronization system 1 uses the positioning system 900 as a time source. Specifically, the time synchronization system 1 detects the time using the highly accurate time information transmitted by the artificial satellite of the positioning system 900.

The antenna 200 receives the positioning information transmitted by the satellite of the positioning system 900, and outputs the obtained positioning information to the grand master clock device 100.
The grand master clock device 100 is a time synchronization source that is the center of the time synchronization system 1, detects the time based on the positioning information received from the positioning system 900 via the antenna 200, and detects the time based on the detected time. Time information in the form of synchronization packets is generated and transmitted to each of the slave devices 400. The grand master clock device 100 transmits time information to the slave device 400 for the purpose of synchronizing the time of the slave device 400 that is the time synchronization target with the time of the positioning system 900. Transmission is also referred to as transmission. The grand master clock device 100 corresponds to an example of a synchronous message transmission device.

The transparent clock unit 300 and the L2 switch 820 both relay communication between the grandmaster clock unit 100 and the slave unit 400.
The transparent clock device 300 receives the time synchronization packet from the grandmaster clock device 100 and transmits it to the slave device 400 of the transmission destination. At this time, the transparent clock device 300 subtracts the reception time from the transmission time to calculate the delay time in the transparent clock device 300, and writes the calculated delay time in the time synchronization packet (stamps). The slave device 400 that has received the time synchronization packet performs correction based on the delay time written in the time synchronization packet, thereby delaying or delaying (jitter) the transmission time of the transparent clock device 300 with respect to time synchronization. Can reduce the effects of
On the other hand, the L2 switch 820 is a general multiport switch and does not perform processing such as identification of a time synchronization packet. The time required for the time synchronization packet to pass through the L2 switch 820 contributes to the delay and fluctuation of the transmission time on the communication path 800.

  The slave device 400 is a device for time synchronization in the time synchronization system 1. The slave device 400 synchronizes the internal time of the slave device 400 with the internal time of the grand master clock device 100 using the time synchronization packet received from the grand master clock device 100 via the communication path 800. Here, the time inside the device is obtained by correcting the clock included in the device with a time synchronization packet.

The apparatus configuration shown in FIG. 1 is the same as the apparatus configuration in the conventional time synchronization system. There is no need to add a special device in the present embodiment, and the internal configuration of the grand master clock device 100 differs from that of the conventional time synchronization system as described later.
Also, in order to identify the slave device 400 that is the time synchronization target, the grand master clock device 100 gives the slave device 400 an SMID (SYNC message ID). The SMID is an integer serial number having a value unique to each slave device 400.
However, the SMID is not stored in the slave device 400, and the grand master clock device 100 is stored in the grand master clock device 100 in order to identify the slave device 400.

In the present embodiment, a case where up to 500 slave devices 400 can be registered in the grand master clock device 100 will be described as an example. The grand master clock device 100 assigns an SMID of 0 to 499 to 500 slave devices 400.
However, the number of slave devices 400 that can be registered in the grand master clock device 100 is not limited to 500 or less. When the grandmaster clock device 100 performs time synchronization to 1000 slaves, it is possible to easily scale up the SMID by increasing the SMID bit by 1 bit as compared with the case of 500 slaves. When one grand master clock device 100 synchronizes a large number of slave devices 400 with time, the configuration of communication path 800 becomes complicated, and L2 switches 820 other than the switches supporting time synchronization such as transparent clock device 300 are multistaged. It should be noted that there is a possibility of getting caught.

  The connection relationship between the grandmaster clock device 100 and the slave device 400 is not limited to that shown in FIG. For example, the grand master clock device 100 and the slave device 400 may be connected on a one-to-one basis. Also, the grandmaster clock device 100 and the slave device 400 may be connected simply via the network 810 without the transparent clock device 300 or the L2 switch 820.

Here, with reference to FIGS. 2 to 4, fluctuation of the transmission interval of the time synchronization packet in the grand master clock device according to the IEEE 1588 v 2 time synchronization process will be described. In general, the grandmaster clock unit operates according to the IEEE 1588v2 time synchronization process.
FIG. 2 is an explanatory view showing a hierarchical structure in the IEEE 1588v2 time synchronization process. In the figure, a grand master clock device 1100 and a slave device 1400 are shown, and the grand master clock device 1100 and the slave device 1400 are connected by a communication path 1800.

  In addition, both the grand master clock device 1100 and the slave device 1400 operate according to a protocol forming a five-layer hierarchical structure. The five hierarchical structures are, from the lower level, a physical layer (PHY layer), a media access controller (MAC) layer, an internet protocol (IP) layer, a user datagram protocol (UDP) layer, It is a Precision Time Protocol (PTP) layer. The media access controller layer includes a time stamp unit (TSU).

  The grand master clock device 1100 is a time synchronization source, and the slave device 1400 is a time synchronization target. In both the grand master clock device 1100 and the slave device 1400, the PTP layer, which is a protocol necessary for time synchronization, is located at the highest layer, and processing is usually performed by a central processing unit (CPU). The time synchronization packet is also transmitted to the lower layer at scheduled timings in the process of the PTP layer.

The UDP layer and the IP layer are both protocol stack layers, and are implemented in the OS (Operating System). Since the time synchronization packet generated in the PTP layer is a UDP packet, it is usually transmitted to the lower layer via the UDP layer and the IP layer.
The MAC layer performs processing such as addition of MAC address information, FCS (Frame Check Sequence) calculation processing, and the like to PTP packets encapsulated by the PTP layer, the UDP layer, and the protocol stack of the IP layer, and an interface with the physical layer. Act as. Also, the time stamp unit included in the MAC layer implements the time stamp that is an important element of the PTP layer.

The advantage of IEEE 1588 v 2 over other time synchronization schemes is that it has a timestamp unit in the MAC layer. As a result, PTP packets issued from the PTP layer are not affected by delay or jitter in the PTP layer above the MAC layer, the UDP layer, and the IP layer with respect to time stamp stamping.
On the other hand, in the conventional grand master clock device, the packet transmission timing is affected by delay (Delay) and jitter (Jitter) in the PTP layer, the UDP layer and the IP layer. This point will be described with reference to FIG.

FIG. 3 is a schematic block diagram showing a configuration example of a conventional grand master clock device.
In the figure, a grand master clock device 1100 includes a GNSS synchronous frequency oscillator (GNSSDO) 1110, a physical layer chip (PHY) 1120, a media access controller (MAC) unit 1130, and a crystal oscillator 1150. , And a CPU (Central Processing Unit) 1170. The GNSS synchronous frequency oscillator 1110 includes a GNSS receiver 1111, a clock adjuster 1112 and a crystal oscillator 1113. The MAC unit 1130 includes a receive time stamp unit (RTSU) 1131, a receive FIFO (first-in first-out) 1132, a transmit FIFO 1133, and a transmit time stamp unit (TTSU) 1137. And a Precision Time Counter Unit (PRTCU) 1142. The CPU 1170 includes a hardware (HW) access unit 1171, a driver 1172, an operating system (OS) kernel 1173, a GNSS management daemon (GNSSD) 1174, a protocol stack 1175, a Delayreq transmission processing unit 1176, and a Sync transmission processing. A section 1177, a scheduler 1178, and a memory controller 1181.

The CPU 1170 implements each unit in the CPU 1170 by reading and executing a program from a storage device provided in the grand master clock device 1100. On the other hand, the GNSS synchronous frequency oscillator 1110, the physical layer chip 1120, and the MAC unit 1130 are configured by hardware.
Also, the physical layer chip 1120 executes processing of the physical layer, the MAC unit 1130 executes processing of the MAC layer, and the CPU 1170 executes processing of the IP layer, the UDP layer, and the PTP layer.

The grand master clock device 1100 is connected to an antenna (ANT) 1200 for receiving positioning information from the positioning system. Specifically, the antenna 1200 is connected to the GNSS synchronous frequency oscillator 1110 via a coaxial cable, and outputs time information extracted from the received positioning information to the GNSS synchronous frequency oscillator 1110.
The GNSS synchronous frequency oscillator 1110 reports ToD (Time Of Day, year, month, day, hour, minute, second time information), 1 PPS (accurate one second from the GNSS signal obtained from the antenna 1200) A pulse signal) and a 125 megahertz (MHz) frequency signal are acquired and provided inside the grand master clock device 1100.

  The GNSS receiver 1111 extracts time information and navigation information of the GNSS from the GNSS signal received by the antenna 1200. Then, the GNSS receiver 1111 determines the current position of the satellite (the relative position between the satellite and the grand master clock device 1100 according to the principle of triangulation based on the navigation information of the GNSS and the time information periodically sent from the GNSS. To identify). When the current position is determined, the GNSS receiver 1111 converts the time information.

  The time information included in the GNSS is periodically corrected by the cesium atomic clock placed on the ground, and the time information obtained from the GNSS signal indicates a very accurate time. The time information obtained from the GNSS signal can be regarded as synchronizing to the world's only absolute time, so to speak. Since the time information is information on frequency and phase simultaneously, the clock adjuster 1112 corrects the crystal oscillator 1113 in response to the injection of a pulse per second. Thus, the clock adjuster 1112 corrects the frequency of the crystal oscillator 1113 so as to match the frequency of 125 MHz with high accuracy. In the present embodiment, the case where 125 MHz is used as the fundamental frequency is described as an example, but it is possible to replace the fundamental frequency with a predetermined frequency, such as 10 MHz or 25 MHz.

In the MAC unit 1130, the reception time stamp unit 1131 writes the reception time in the reception packet (the packet received by the grand master clock device 1100) (the reception time stamp is stamped).
The receive FIFO 1132 temporarily stores the received packet.
The transmission FIFO 1133 temporarily stores transmission packets (packets transmitted by the grand master clock device 1100).
The transmission time stamp unit 1137 writes the transmission time in the transmission packet (stamps the transmission time stamp).

The crystal unit 1150 is a crystal unit whose frequency accuracy is lower than that of the crystal unit 1113. The crystal oscillator 1150 is used as a reference clock of the CPU 1170.
The main memory 1160 is configured using a storage device provided in the grand master clock device 1100, and stores various information.

In the CPU 1170, a hardware access unit 1171 connects the bus and the driver 1172, and the driver 1172 controls the hardware. The bus is generally provided by a PCI bus or a local bus.
The CPU 1170 performs ToD acquisition and transmission / reception packet handling via the hardware access unit 1171. In transmission and reception packet handling, the CPU 1170 outputs the main memory address instructed from the OS kernel 1173 to the main memory controller 1181 and reads transmission packet information from the main memory 1160 for the transmission packet. Then, the CPU 1170 outputs the read transmission packet information to the MAC unit 1130. The CPU 1170 stores the packet received from the MAC unit 1130 in the main memory address of the main memory 1160 instructed by the OS kernel 1173, contrary to the case of the transmission packet for the received packet.

  Here, in the transmission / reception packet processing, a system directly implemented by the main memory 1160, the main memory controller 1181, and the MAC unit 1130 without using the operation unit of the CPU 1170 using DMA (direct memory access) is the mainstream. In the grand master clock device 1100 shown in FIG. 3, a DMA is built in the memory controller 1181, and transmit / receive packet processing is performed using this DMA.

The OS kernel 1173 is the core of the operating system such as Linux (registered trademark), UNIX (registered trademark), and windows, and controls the scheduler 1178 that performs execution management of various processes and allocates memory space.
The GNSSD 1174 is a control daemon that controls the GNSS synchronous frequency oscillator 1110, and based on the ToD information obtained from the GNSS, the time adjustment of the second or more granularity of the precision time counter unit 1142 of the MAC unit 1130, and the GNSS synchronous frequency. The state monitoring of the oscillator 1110 is performed. Specifically, the GNSSD 1174 performs time alignment based on the time alignment (correction of oscillation of the crystal oscillator 1113) previously performed by the GNSS synchronous frequency oscillator 1110. Then, the GNSSD 1174 manages state changes such as the crystal oscillator 1113 in the GNSS synchronous frequency oscillator 1110 becoming a free-running state (Holdover) according to the reception status of GNSS radio waves, etc. Conduct.

  The protocol stack 1175 performs processing of each layer of UDP and IP. The protocol stack 1175 may be compiled and implemented with the OS kernel 1173 or may be additionally introduced. A standard protocol is generally compiled and implemented with the OS kernel 1173 to reduce the burden of the user in implementing the protocol stack 1175.

The scheduler 1178 manages the execution of the various processes as described above.
The Sync transmission processing unit 1177 transmits the ID of the slave device to be transmitted to the scheduler 1178 based on the synchronization interval (Sync interval, Sync interval) previously negotiated (negotiated) with the slave device 1400 according to the PTP protocol. (Hereinafter referred to as slave ID) is registered. The scheduler 1178 refers to the slave ID area (area where the ID of the slave device is registered) with a fixed granularity (for example, 500 us), and transmits the slave ID to the Sync transmission processing unit 1177 if the slave ID exists. The Sync transmission processing unit 1177 generates a synchronization message (Synchronous message (Sync message)) relating to the slave ID as a time synchronization packet, and outputs it with the additional information to the protocol stack 1175.

  Here, the granularity of scheduler 1178 can be a major issue for time synchronization systems. For example, in a time synchronization system that sends synchronization messages at a granularity of 500 us, if it is desired to send 128 synchronization messages per second, the correct interval is 1/128 = 7,812 microseconds (us) and a neighborhood of 500 us The numerical value is 8,000 microseconds or 7,500 microseconds. In both 8,000 microseconds and 7,500 microseconds, there is a difference from 7,812 microseconds which is the correct interval, and this difference generates jitter.

In addition, the fact that the CPU 1170 is not synchronized with the high-precision crystal oscillator 1113 synchronized with the time extracted from the GNSS can also be a factor that generates jitter in one direction or jitter. Furthermore, since the CPU 1170 is executing various processes, there is no guarantee that the Sync transmission process (synchronization message transmission process) can be started at the time designated by the scheduler 1178. Furthermore, when the Sync transmission timing (the transmission timing of the synchronization message) arrives, if the transmission processing of the packet of the general message other than the synchronization message has already been performed, it is necessary to wait for the transmission processing end.
Here, the general message indicates, for example, a message other than the synchronization message, such as a management message or a delay resp message described later, for which the CPU 1170 performs transmission processing.

  When the grandmaster clock device 1100 receives the delayreq message (delayreq message) from the slave device, the Delayreq transmission processing unit 1176 records the reception time and records the recorded reception time in the delayresp message. Then, the Delayreq transmission processing unit 1176 performs processing of transmitting a delayresp message (delayresp message) to the slave device that has transmitted the delayreq message in a format prescribed by IEEE 1588 v2. The delayresp message is used by the slave device to calculate the network delay time.

As described above, CPU processing has many fluctuation factors, and it is difficult to maintain an accurate Sync interval (interval for sending a synchronization message). On the other hand, the MAC unit 1130 corrects the PTP packet in the reception time stamp unit 1131 and the transmission time stamp unit 1137 by the reception FIFO 1132 and the transmission FIFO 1133 and the precision time counter unit 1142 which is an accurate time source equivalent to GNSS. I stamp a good time.
The physical layer chip (PHY) 1120 communicates with the slave device 1400 via a network.

FIG. 4 is an explanatory view showing an example of delay and fluctuation in a synchronization message transmitted by the conventional grandmaster clock device. In the figure, the horizontal axis represents time, and indicates the later time toward the right of the figure. Further, the vertical lines in the figure show each part in the synchronous message transmission path.
In FIG. 4, the Sync transmission processing unit 1177 negotiates with the slave device 1400 as transmitting synchronization messages at regular intervals of every second (1 PPS), and the synchronization message ID is sent to the scheduler 1178 every one second. Write
Note that FIG. 4 shows an example where the transmission interval of the synchronization message is 1 PPS, so the problem of the granularity described with reference to FIG. 3 will not be mentioned.

Since the scheduler 1178 operates with the low-precision crystal oscillator 1150 which is the reference clock of the CPU, the operation of the scheduler 1178 has fluctuations with respect to the absolute time axis. That is, due to an error of the clock by the quartz oscillator 1150, the transmission timing of the synchronization message indicated by the scheduler 1178 may include an error for one second interval.
Next, when the scheduler 1178 detects the transmission timing of the synchronization message, the Sync transmission processing unit 1177 writes the synchronization message at the transmission timing to the main memory 1160. At this time, a delay due to the writing to the main memory 1160 occurs. Also, jitter may occur if another process accesses the same main memory while writing a synchronization message.

  The synchronization message stored in the main memory 1160 is stamped with the accurate transmission time from the grandmaster clock device 1100 by the TTSU 1137 in the MAC 1130 operated by the high precision quartz oscillator 1113. Then, the synchronization message whose transmission time has been stamped is transmitted from the grand master clock device 1100.

Here, when the network delay is expressed as Δdelayi (i is a positive integer), the arrival time of the packet arriving at the slave device 1400 is as shown in “Δdelay1 + 100 ns”, “Δdelay2 + 300, 500 ns”,. Distributed to In particular, when the network delay fluctuation is small, fluctuation components generated in the grandmaster clock device 1100 have a great influence on the arrival interval of the synchronization message.
Also, the granularity problem described with reference to FIG. 3 further reduces the accuracy of the arrival interval of the synchronization message to the slave device 1400.

  FIG. 5 is an explanatory view showing a hierarchical structure in the time synchronization process of the present embodiment. In the figure, a grand master clock device 100 and a slave device 400 are shown, and the grand master clock device 100 and the slave device 400 are connected by a communication path 800.

  Further, both the grand master clock device 100 and the slave device 400 operate according to a protocol forming a five-layer hierarchical structure. The five hierarchical structures are, from the lower level, a physical layer (PHY layer), a media access controller (MAC) layer, an internet protocol (IP) layer, a user datagram protocol (UDP) layer, It is a Precision Time Protocol (PTP) layer. The media access controller layer includes a time stamp unit (TSU).

The grand master clock device 100 is a time synchronization source, and the slave device 400 is a time synchronization target. The slave device 400 processes PTP, which is a protocol necessary for time synchronization, in the highest layer using the CPU.
On the other hand, the grandmaster clock device 100 executes the process of transmitting the synchronization message in the process in the MAC layer based on the interval designated by the profile from the CPU, the information on the slave device 400, and the like. As described above, the grandmaster clock device 100 separates the synchronous message transmission process from the CPU and executes it.

  Since PTP is a UDP packet, it is usually transmitted to a lower layer via UDP and IP protocol stacks implemented in the OS. On the other hand, when specializing in synchronization messages, the size and field position of the packet are constant for all slave devices 400, the other party's address is different for each slave device 400, and sequence numbers, UDP checksums, etc. are unique when transmitted. It will be the data to be determined.

The grand master clock device 100 stores, as a profile, information output from each protocol stack of PTP, UDP, and IP in the MAC layer. At that time, the MAC layer divides and stores the global profile, the SMID profile (synchronization message profile), and the SM table (synchronization message table). As described later, the global profile is a collection of constant data for all slave devices 400. Also, the SMID profile is a collection of different data for each slave device 400. The SMID table is a collection of data uniquely determined at the time of transmission (data having different values for each synchronization message).
Then, the grandmaster clock device 100 sends out the synchronization message at the time scheduled by the very high precision clock originating from GNSS in the MAC layer, thereby eliminating the fluctuation of the delivery timing due to the processing in the CPU layer, Realize synchronous message transmission with only a fixed delay.

FIG. 6 is a schematic block diagram showing a configuration example of the grand master clock device in the present embodiment.
In the figure, the grand master clock device 100 includes a GNSS synchronous frequency oscillator (GNSSDO) 110, a physical layer chip (PHY) 120, a media access controller (MAC) unit 130, and a crystal oscillator 150. , A main memory 160, and a CPU (Central Processing Unit) 170. The GNSS synchronous frequency oscillator 110 includes a GNSS receiver 111, a clock adjuster 112, and a crystal oscillator 113. The MAC unit 130 includes a reception time stamp unit (RTSU) 131, a reception FIFO (first-in first-out) 132, a transmission FIFO 133, a sync profile storage unit 134, a sync generation unit 135, and a sync. A transmission unit 136, a transmission time stamp unit (TTSU) 137, a scheduler 141, and a precision time counter unit (PRTCU) 142 are provided. The more detailed configuration of the MAC unit 130 will be described later.
The CPU 170 includes a hardware (HW) access unit 171, a driver 172, an OS (Operating System) kernel 173, a GNSS management daemon (GNSSD) 174, a protocol stack 175, a Delayreq transmission processing unit 176, and a Sync registration process. And a memory controller 181.

The CPU 170 implements each unit in the CPU 170 by reading and executing a program from a storage device provided in the grand master clock device 100. On the other hand, the GNSS synchronous frequency oscillator 110, the physical layer chip 120, and the MAC unit 130 are configured by hardware.
Also, the physical layer chip 120 executes processing of the physical layer, the MAC unit 130 executes processing of the MAC layer, and the CPU 170 executes processing of the IP layer, the UDP layer, and the PTP layer.

The configuration and function of the GNSS synchronous frequency oscillator 110 are the same as the configuration and function of the GNSS synchronous frequency oscillator 1110 in FIG.
The functions of the reception time stamp unit 131 and the transmission time stamp unit 137 in the MAC unit 130 are the same as the functions of the reception time stamp unit 1131 and the transmission time stamp unit 1137 in FIG.
Further, the functions of the crystal unit 150 and the main memory 160 are the same as the functions of the crystal unit 1150 and the main memory 1160 in FIG. 3, respectively, and the description will be omitted.
The CPU 170 is the same as the CPU 1170 of FIG. 3 except that a Sync registration processing unit 177 is provided instead of the Sync transmission processing unit 1177 and the scheduler 1178 of FIG. 3. Although the CPU 170 also executes the scheduler function of the OS, the CPU scheduler is not shown in FIG. 6 because the function is not directly used in sending the synchronization message. The CPU 170 corresponds to an example of a general message generation unit, and generates a general message as in the CPU 1170 of FIG.

The Sync registration processing unit 177 notifies the MAC unit 130 of the synchronization message interval negotiated with the slave device 400, the destination address, and the like via the hardware access unit 171. This eliminates the need to use the scheduler function of the CPU 170 when sending out a synchronization message. Therefore, in the transmission of the synchronization message, the fluctuation of the transmission timing caused by the low-precision crystal oscillator 150 and the fluctuation of the transmission timing caused by the scheduler granularity do not occur.
Further, since the CPU 170 is released from the periodic synchronization message transmission processing, it is possible to devote a lot of time to other processing such as GNSSD processing and Delayreq transmission processing, and it is possible to expect improvement in the performance of the apparatus. The function of the Delayreq transmission processing unit 176 is the same as the function of the Delayreq transmission processing unit 1176 in FIG.

  The MAC unit 130 receives an instruction from the Sync registration processing unit 177, and stores Sync characteristics for each slave device 400 in the Sync profile storage unit 134. Specifically, the MAC unit 130 acquires the Sync interval (the transmission interval of the synchronization message), the address information leading to the slave device 400, and each of the elements constituting the synchronization message, and the three in the Sync profile storage unit 134. Disassemble into elements and store. The three elements will be described later.

  The MAC unit 130 further includes a scheduler 141, and the scheduler 141 has an SMID as described later. The SMID counts up at intervals of 15,625 nanoseconds obtained by further dividing the 7,812,500 nanoseconds by 500.

The scheduler 141 counts up the SMID after receiving 1 PPS which is a pulse per second, and determines whether or not there is a synchronization message to be sent at the current time by comparing nextInterval in the SMID_tabel with the SYNCID counter. If it is determined that the nextInterval and the SYNCID counter are equal, the scheduler 141 outputs a sync transmission pulse (Transmit pulse) to the Sync transmission unit 136.
The scheduler 141 corresponds to an example of a scheduler unit.

The Sync generation unit 135 merges three elements constituting the synchronization message set in advance by the Sync registration processing unit 177 of the CPU 170, generates a synchronization message, and presents the synchronization message obtained to the Sync transmission unit 136. The Sync generation unit 135 corresponds to an example of a synchronization message generation unit.
The Sync sending unit 136 sends the synchronization message by any of the three methods described later. The Sync sending unit 136 corresponds to an example of the sending unit.

  Note that the part that transmits the synchronization message is not limited to the MAC unit 130. For example, a part other than the MAC unit 130 may be configured to transmit a synchronization message using an FPGA. In this case, the physical layer chip, the FPGA, and the MAC are configured in order from the lower layer, and the time stamp is stamped with the FPGA.

FIG. 7 is an explanatory view showing an example of a delay in a synchronization message transmitted by the grand master clock device in the present embodiment. In the figure, the horizontal axis represents time, and indicates the later time toward the right of the figure. Further, the vertical lines in the figure show each part in the synchronous message transmission path.
In FIG. 7, the Sync registration processing unit 177 negotiates with the slave device 400 to send synchronization messages at regular intervals of every second (1 PPS), and the Sync profile storage unit 134 of the MAC unit 130 transmits the transmission interval, Register each element that composes the synchronization message. The process performed by the CPU 170 in connection with the transmission of the synchronization message is limited to the registration process in the Sync profile storage unit 134. This allows the CPU 170 to concentrate on the execution of processes necessary for other PTP processing and device management.

  The transmission of the synchronization message in 1 PPS is registered in the SYNC profile storage unit 134, and manages the profile in units of SMID (Sync message ID) described later. In the MAC unit 130, the internal logic circuit operates with the high-precision crystal oscillator 113 originating from GNSS. The MAC unit 130 periodically monitors the SMID, assembles a synchronization message when there is an SMID to be transmitted, and performs transmission.

  The Sync sending unit 136 performs the sending process of the synchronization message based on any of the three rules described later. In particular, in the forced discard method and transmission time reservation method described later, it is possible to send out a synchronization message every every second. Therefore, the fluctuation component of the synchronization message transmission timing in the grandmaster clock device 100 is eliminated, and the synchronization message can be transmitted to the slave device 400 only by the delay component or fluctuation component in the communication path. In particular, when the delay component Δdelayi (i is a positive integer) in the communication path is constant, the synchronization message arrives at the slave device 400 exactly at regular intervals. As described above, by eliminating the fluctuation component in the CPU, it is possible to improve the time accuracy in the slave device 400 and shorten the time synchronization time.

FIG. 8 is an explanatory view showing the format of an IEEE 1588 v2 synchronization message. In the figure, 32 bits (bit), that is, 4 bytes (BYTE) are shown in the horizontal direction, and are transmitted to the line from the leftmost bit.
In the downward direction of the figure, a set of 32 bits is represented as continuous data, and is transmitted to the line from the data of the upper row to the data of the lower row in order.
Further, 1, 5, 9,... Described at the left end of the figure indicate the left end of the set of 32 bits, that is, the byte position which is first sent to the network. For example, the leftmost bit of the first line from the top is included in the first byte, and the leftmost bit of the second line from the top is included in the fifth byte.

As shown in FIG. 8, the synchronization message has a fixed length of 86 bytes when it does not include the FCS (Frame Check Sequence). Although the length may be changed by a VLAN tag or the like, the length is fixed in the grand master clock device 100.
The synchronization message is composed of multiple protocols.

  The Ether header is an area given to all packets propagating Ethernet (registered trademark), MAC-DA which is a destination MAC address, and MAC-SA which is a transmission source MAC address (MAC address of the grand master clock device 100). , And EtherType indicating the type of protocol to be continued. In addition, since it is IPv4 in the case of a synchronous message, it is fixed to Ethertype = 0x0800.

  IP header is IP version number (version = 4), IP header length (length = 5), service type (TOS), datagram length (data length = 72), ID (random value), flag field (Flag) and fragment offset (fragment offset, = 0x00), TTL (= 1), protocol number (protocol No, = 17: UDP), header checksum (header checksum, IP header part checksum value, calculation method is Defined in RFC 1071).

  The UDP header is a source (grand master clock device 100) UDP port number (UDP-SP, = 319: fixed value defined in IEEE 1588 v2), destination (slave device 400) UDP port number (UDP-DP, = 319: 1's complement of 3 parts: fixed value specified in IEEE 1588 v 2), UDP packet length (UDP-length, = 52), UDP checksum (UDP-checksum, UDP pseudo header 12 bytes + UDP header + UDP payload) Is the value calculated by the sum of By setting the value of the UDP checksum to 0, the UDP checksum calculation is invalidated in the destination device and the check is not performed. Since the time stamp changes in real time in the implementation of the grand master clock device, the implementation that sets the UDP checksum area to 0 is simple and implemented in many grand master clock devices and software-based grand master clock devices, however It is not desirable to compromise the reliability of the most important timestamps in time synchronization due to any problem on the network or in the device. Therefore, the grand master clock device 100 calculates the UDP checksum for each packet and stores it in the UDP checksum area.

  The PTP header is a header format for time synchronization packets defined in IEEE 1588 v 2 and includes synchronization messages. Transmitspecific is a 4-bit value (default = 1) freely configurable by the administrator of the grandmaster clock device 100 for future expansion. The message type (MessageType) is a synchronization message (= 0). In this application, version PTP is based on PTPv2 (= 2).

  The message length is fixed in the case of a synchronization message (= 44). The domain number is set by the administrator of the grandmaster clock device for the time synchronization group = domain to which the grandmaster clock device belongs. FlagField is a field for setting the characteristics of the grandmaster clock device, and is set by the manager of the grandmaster clock device. The correction field is an area not used in the grand master clock device. clockIdentity is an identifier uniquely indicating a grandmaster clock device, and is an effective area when there are a plurality of grandmaster clock devices on the network, etc. In IEEE 1588v2, a MACSA, that is, a MAC address having only one MAC address on the network It is defined that a total of 8 bytes can be obtained by dividing every 3 bytes and inserting FF-FF between them. sourcePortID is an area indicating which port of the grandmaster clock device is the message output from. The sequenceID is a number sequentially assigned to the transmission of the synchronization message, and appears to be incremented by one when viewed from a single slave device. It is possible to detect the omission of the synchronization message in this ID and take some action. Moreover, it becomes possible to delete the factor which disturbs time synchronization, such as reversal of ID by a route. controlField represents a synchronization message (= 0). logMessagePeriod is usually 0. Synchronization Message Payload is composed of originTimestamp if it is a synchronization message. The originTimestamp is composed of a 48-bit second area and a 32-bit nanosecond area, and the originTimestamp is an area for stamping an absolute time originating from GNSS when the synchronization message is sent from the grandmaster clock device 100. . As described above, it is necessary to send a lot of information in addition to the time information which is the information that the synchronization message wants to send. Further, in FIG. 8, information to be generated is classified into four types. The first is an area having the same value in all synchronization messages transmitted from the same grand master clock device. The second is an area sent from the same grand master clock device and having the same value in the synchronization message sent to the same slave device. The third is an area having a different value for each synchronization message. The fourth is a reserve area for future expansion.

FIG. 9 is an explanatory view showing an example of the data structure of the global profile (Gloval profile) stored by the Sync profile storage unit 134 (global profile storage unit 134-1).
The global profile is a collection of data of areas (first areas) having the same value in all synchronization messages transmitted from the same grand master clock device among the areas shown in FIG.

The 48 bytes shown in FIG. 9 are always the same value (a value common to each synchronization message) including the reserved area (RSVD), and the Sync profile storage unit 134 stores one global profile. Managing in a single memory area is an effective means in terms of device cost.
An exception is an ID (random value) area, and the value of the ID (random value) area differs every packet. The values in the ID (random value) area are literally random, and there is no need to keep unique values in the Gloval profile. However, in the example of FIG. 9, an area is secured for use such as setting a seed value (initial value) for generating a random value. In addition, a well-known random value production | generation system can be used as a random value production | generation system of ID (random value) area | region.

FIG. 10 is an explanatory drawing showing an example of the data structure of the SMID profile (SMID_profile) stored by the Sync profile storage unit 134 (SMID profile storage unit 134-2).
The SMID profile is data of an area (second area) having the same value in the synchronization message transmitted from the same grand master clock device and transmitted to the same slave device among the areas shown in FIG. Give up on As shown in FIG. 10, a reserve area (RSVD) is included.
The Sync profile storage unit 134 stores an SMID profile for each slave device 400. The SMID profile shown in FIG. 10 is composed of 28 bytes. When time synchronization is performed on 500 slave devices 400, the Sync profile storage unit 134 stores the SMID profile using an area of 28 × 500 = 14,000 bytes.

FIG. 11 is an explanatory drawing showing an example of the data structure of the SMID table (SMID_table) stored by the Sync profile storage unit 134 (SMID table storage unit 134-3).
The SMID table is a table in which data of areas (third areas) having different values for each synchronization message among the areas shown in FIG. 8 are collected. Note that, as shown in FIG. 11, a reserve area (RSVD) is included.
The SMID table shown in FIG. 11 is composed of 8 bytes. When time synchronization is performed on 500 slave devices 400, the Sync profile storage unit 134 stores the SMID table using an area of 8 × 500 = 4,000 bytes.

  From the above, the storage capacity necessary for the Sync profile storage unit 134 to store the Gloval profile, the SMID profile, and the SMID table can be determined by Expression (1).

      48 + 14,000 + 4,000 = 18,048 (bytes) (1)

  The area of about 18 kilobytes (k BYTE) is extremely small in modern memory technology and does not pose an obstacle for mounting in an ASIC or FPGA.

  FIG. 12 is a schematic block diagram showing a functional configuration of the MAC unit 130. As shown in FIG. In the figure, the MAC unit 130 includes a reception time stamp unit (RTSU) 131, a reception FIFO 132, a transmission FIFO 133, a Sync profile storage unit 134, a Sync generation unit 135, a Sync transmission unit 136, and a transmission time stamp unit. (TTSU) 137, a SYNC message FIFO 139, a scheduler 141, and a precision time counter unit (PRTCU) 142. The Sync profile storage unit 134 includes a global profile storage unit 134-1, a SIMD profile storage unit 134-2, and an SMID table storage unit 134-3.

  The MAC unit 130 receives a high-precision 1 PPS (second pulse) originating from GNSS and a clock signal of 125 MHz. Then, each process in the MAC unit 130 operates at extremely accurate timing at 125 MHz. Also, ToD is date and time information.

  The precision time counter unit 142 is a device internal time source, and stores a Sec field storing 48 bits of date, hour, minute, and second information of the current time, and subseconds with a minimum unit of 8 nanoseconds, which is the reciprocal of 125 MHz. And an Nsec area for storing time information in 30 bits. The precision time counter unit 142 acquires ToD, determines the second information, and counts up the Nsec region at 8 ns, which is the reciprocal of 125 MHz. Further, the precision time counter unit 142 has a mechanism for resetting the Nsec counter to 0 with 1 PPS pulse and finely adjusting Nsec in every positive second. The second information and nanosecond information generated by the precision time counter unit 142 are notified to the reception time stamp unit (RTSU) 131 and the transmission time stamp unit (TTSU) 137, and are stamped in the originalTimestamp field when the synchronization message is generated.

The Sync profile storage unit 134 is configured by a DPRAM (dual port RAM). As a result, it is possible to eliminate waiting due to the CPU 170 and each process of the MAC unit 130 accessing the Sync profile area 134 asynchronously. The Sync profile storage unit 134 is a memory space for storing the global profile, the SMID profile <0 to 499>, and the SMID table <0 to 499> described above with reference to FIGS. 9, 10 and 11. Specifically, the global profile storage unit 134-1 stores a global profile. The SMID profile storage unit 134-2 stores an SMID profile. The SMID table storage unit 134-3 stores the SMID table.
In access to the Sync profile storage unit 134, the CPU 170 writes each data by specifying an address (ADDR) and data (DATA). The data written by the CPU 170 is treated as a fixed value by each process of the MAC unit 130. In addition, it is possible to monitor the current sending state of the synchronization message by using the read function.

  The reception FIFO 132 is a memory space for storing PTPs received by the physical layer chip 120 from the network 810 and packets other than PTPs. The reception FIFO 132 stores the reception data received from the reception time stamp unit 131 in a FIFO format while DataEnable (signal indicating that there is data) is asserted. Also, the receive FIFO 132 has an EmptyFlag, and negates the EmptyFlag if data is present. Thus, the presence of valid reception data can be transmitted to the CPU 170.

  The CPU 170 periodically monitors the EmptyFlag and performs processing for loading the received DATA into the CPU 170 in synchronization with the CPU clock (using the low-precision crystal oscillator 150). The data acquired by the CPU 170 may be various other than PTP.

The transmission FIFO 133 is a memory space for storing a packet output from the CPU 170 to the MAC unit 130. The packet output from the CPU 170 to the MAC unit 130 is a packet other than the synchronization message (a packet of a general message). The CPU 170 outputs the transmission DATA to the transmission FIFO 133 when FullFlag is negated. On the other hand, when FullFlag is asserted, the CPU 170 does not perform packet transmission processing, and stores data to be transmitted in the main memory or the like. The transmission FIFO 133 is also connected to the Sync transmission unit 136 in each path of EmptyFlag, ReadPulse, and transmission DATA.
The Sync transmission unit 136 outputs ReadPulse (a signal for reading data from the FIFO) when there is no synchronization message, and executes reading of the transmission DATA.

  The SYNC message FIFO 139 is an area in which only the synchronization message is stored, and stores the synchronization message generated by the Sync generation unit 135. The SYNC message FIFO 139 always stores one or less synchronization messages. Also, the SYNC message FIFO 139 is connected to the Sync sending unit 136 by Empty Flag, Read Pulse, and transmission DATA. The SYNC message FIFO 139 sends out the transmission DATA according to the ReadPulse after any time timing according to the rule of the Sync sending unit 136 when the EmptyFlag (signal indicating no data) is asserted.

The scheduler 141 has a SYNC ID counting up at 1 second / 128. The SYNCID corresponds to the SyncInterval in sync message transmission.
Further, the scheduler 141 includes SMID which is a counter that counts up at the timing when one cycle of the SYNCID is further divided into 500.

  The scheduler 141 also converts the SMID value into the address of the SMID table and the address of the SMID profile, and sets the address information in the Sync profile. The scheduler 141 reads nextInterval information, syncInterval, and sequenceID from the SMID table determined by the address. If the nextInterval matches the SYNCID, the scheduler 141 determines that it is the timing to transmit a synchronization message, and outputs TransmitPulse to the Sync generator 135 and the Sync transmitter 136. Also, when the nextInterval matches the SYNCID, the scheduler 141 updates the value of the nextInterval and the value of the sequenceID. Specifically, the scheduler 141 updates the value of nextInterval to the next transmission timing calculated from the value of syncInterval. Also, the scheduler 141 writes a numerical value obtained by incrementing 1 in sequenceID to the SMID table.

  Here, nextInterval is information for corresponding to the synchronization message transmission interval set for each slave device 400. With respect to the slave device 400 in which the synchronization message transmission interval is set to 128 PPS, the grand master clock device 100 may transmit the synchronization message at the same interval as the SyncID incrementing interval. On the other hand, for the slave device 400 in which the synchronization message transmission interval is set to 64 PPS, the grand master clock device 100 needs to transmit the synchronization message at the same interval as the interval in which the SyncID is incremented by two.

Therefore, the scheduler 141 compares the nextInterval stored in the Sync profile storage unit 134 with the SMID for each slave device 400. If it is determined that the value of nextInterval and the value of SMID are the same, the scheduler 141 determines that the timing for transmitting the synchronization message has come.
Further, the scheduler 141 calculates the next transmission timing from the sync Interval stored in the Sync profile storage unit 134 for each slave device 400 and writes the next transmission timing. Since 128 PPS is the standard minimum interval, the calculation formula is set to 128 ÷ Sync Interval, and the above calculation result is added to the current next Interval value.
For example, in the case of the slave device 400 in which the synchronous message transmission interval is set to 64 PPS, 128 ÷ 64 = 2, and 2 is added to the value stored in nextInterval to write (update) in the nextInterval area.
Further, in the case of the slave apparatus 400 in which the synchronization message transmission interval is set to 32 PPS, 128 ÷ 32 = 4, 4 is added to the value stored in nextInterval, and writing (updating) to the nextInterval area is performed.

When receiving the Transmit pulse from the scheduler 141, the Sync generation unit 135 reads data from the SMID table and the SMID profile. Since the address has already been determined by the scheduler 141, there is no need to read it. Also, the Sync generation unit 135 reads a global profile common to all synchronization messages, and assembles the synchronization message shown in FIG. The assembly process is completed with only simple field movement. In addition, since a random value is expected for the ID area, the Sync generation unit 135 inserts a random value with a random value generator. The random value generator used by the Sync generation unit 135 may be any random value generator that can generate a random value, and a known random value generator can be used.
The Sync generation unit 135 outputs the synchronization message to the SYNC message FIFO 139 as soon as the assembly of the synchronization message is completed.

  The Sync transmission unit 136 has a register area in which the synchronization message transmission rule (Sync transmit rule) can be set from the CPU 170. In the register, one of three types of transmission methods can be set: (1) forced discard method (Discard), (2) high priority transmission method (H.Priority), and (3) transmission time reservation method (Reserved) It is. For example, the administrator of the grandmaster clock device 100 performs the setting of the synchronous message transmission rule in consideration of the characteristics of the network to which the grandmaster clock device 100 is applied.

(1) In the forced discard method, when the transmission timing of a synchronization message arrives, transmission of packets (general message packets, hereinafter referred to as CPU packets) other than all synchronization messages currently being transmitted is interrupted and the synchronization message is output. It is a method of sending. The packet whose transmission has been interrupted is discarded until the end of the packet.
This is a particularly effective method when the partner apparatus detects an error but retransmission by the upper layer can be expected.
(2) In the high priority transmission method, when the transmission timing of the synchronization message comes, the CPU packet waiting for the current transmission is waited for completion, and the next transmission always transmits the synchronization message. Even if CPU packets are issued consecutively, the synchronization message is transmitted with the highest priority.
(3) In the transmission time reservation method, focusing on the fact that the maximum value of the CPU packet is determined to be 1518 bytes by Ethernet (registered trademark), 1518 bytes before the transmission timing of the synchronization message (actually IFG At the time of 1542 octets (octet time before) due to the presence of the FCS and the FCS, transmission of a new CPU packet is suppressed. This makes it possible to send out the synchronization message with certainty after 1542 octets. The 1542 octets correspond to an example of defined time defined as the time required to send a general message. The CPU packet also corresponds to an example of a synchronization message and a general message.
In the transmission time reservation method, the transmission interval of messages is always constant by starting transmission of synchronization messages when 1542 octets have passed. In time synchronization, the arrival time of the message does not matter, and the transmission time reservation scheme is effective because the message interval and the accuracy of the time stamp in the message are important. In addition, since transmission of CPU packets is stopped only when there is a synchronization message in the transmission time reservation method, even if the transmission interval (Sync interval) of synchronization messages is long, such as when the number of slave devices 400 is small, the CPU message Can be sent out efficiently.
Here, although the maximum time required for sending a general message is defined as a specified time, the present invention is not limited to this, and the specified time may be any time required for sending a general message. Even in this case, the transmission interval of the synchronization message is constant.

The reception time stamp unit 131 performs processing for imprinting time information obtained from the precision time counter unit 142 on the received time synchronization packet.
The transmission time stamp unit 137 performs processing for imprinting time information obtained from the precision time counter unit 142 on the time synchronization packet to be transmitted.
The reception time stamp unit 131 and the transmission time stamp unit 137 both recognize the time synchronization packet and stamp time information. Since the synchronization message is also a time synchronization packet, the transmission timestamp unit 137 also stamps accurate time information in the synchronization message.

  The physical layer chip 120 performs conversion processing between the physical interface of the network 810 and the physical interface of the MAC unit 130.

FIG. 13 is an explanatory view showing an example of the data structure of the synchronization message. The left side of the figure is the MSB, which is the first data transmitted to the network 810. According to Ethernet (registered trademark), an interframe gap (IFG) needs at least 12 octets. An interframe gap is provided to separate the frames.
The preamble + FSD is composed of 7 octet preamble and 1 octet FSD (Frame Start Delimiter). The preamble + FSD is a flag area indicating that the payload of the Ether packet starts thereafter.

  The IEEE 1588 v2 synchronization message (Sync message) is an area in which a synchronization message of a format defined in the IEEE 1588 v2 is stored. The IEEE 1588 v2 synchronization message is composed of a plurality of elements shown in FIG. 8 and transmits time information from the grand master clock unit 100 to the slave unit 400. The size of the IEEE 1588 v2 synchronization message is a fixed length, and is 86 bytes when the synchronization message is configured by UDP.

  The FCS is a frame check sequence, which is a checksum area uniquely calculated from the data area of the Ether packet. The FCS is provided to be able to discard the packet when some failure occurs on the transmission path and the data area of the packet can not be trusted. Also, the FCS may be used as an index indicating the quality of the line.

  If all the elements of the synchronization message are combined, the size is 110 octets. Also, since one octet is composed of 8 bits, 110 octets are 880 bits. Here, in order to calculate how much the 880 bits affect the bandwidth, the packet occupancy time when transmitting at 10 gigabits per second (Gbps) and 1 gigabit per second, respectively, is 10 gigabits per second Is 88 nanoseconds, and 1 gigabit per second is 880 nanoseconds. Here, it is possible that the synchronization message can be issued up to 128 times per second. It is specified in 8265, and it becomes an interval of 1 sec / 128 times = 7,812,500 nanoseconds. Therefore, when time synchronization is performed for a single slave device 400, synchronization messages can be sent without problems at any line rate of 10 Gigabits per second or 1 gigabit per second.

  FIG. 14 is an explanatory drawing showing an example of a transmission interval of synchronization messages in a network in which a plurality of slave devices 400 exist. The figure shows the worst case of the transmission interval of the synchronization message. Specifically, an example is shown in which the network bandwidth is the closest. As noted above, each synchronization message will be at least 7,812,500 nanoseconds apart. FIG. 14 shows the case where this synchronization message is sent to 500 slave devices 400.

  The 7,812,500 nanoseconds are further divided into 500 which is the number of slave devices 400. The transmission interval of synchronization messages that can be assigned to one slave device 400 is 7,812,500 nanoseconds / 500 = 15,625 nanoseconds. This 15,625 nanoseconds is defined as the minimum time interval for synchronous messages. Among the packet occupation times described with reference to FIG. 13, even at 1 gigabit per second, where the line speed is the slowest and the transmission time of one synchronization message is the longest, 15,625 nanoseconds> 880 nanoseconds. Therefore, when focusing on the synchronization message, the bandwidth can be secured. However, it is necessary to allocate the product of the number of slave devices 400 controlled by the grandmaster clock device 100 at one time by the SYNC interval of each slave device 400 to an appropriate value according to the amount of communication other than the synchronization message. The SYNC interval can be set for each slave device 400.

In FIG. 14, SyncID 0 is assigned to the first Sync slot at the beginning of one second, and the SyncID counts up up to 127. SyncID becomes 0 after being 127. Also, in order to generate timing for sending a synchronization message, an SMID is introduced, and an area for storing information on the slave device 400 is provided in association with each SMID.
The SMID takes a positive integer value of 0 to 499 and counts up in 15,625 nanoseconds. Note that it is necessary to associate the same SMID with the synchronization message information for the same slave device 400 without fail. The manager of the grandmaster clock device 100 determines, for example, which SMID to use. In order to make the synchronization message interval constant, the SMID corresponding to one slave device 400 needs to be unique.
The SyncID corresponds to an example of the first counter. The SMID corresponds to the example of the second counter.

FIG. 15 is an explanatory view showing an example of the data structure of the SMID table.
The SMID table includes an 11-bit area for registering an SMID, a SyncInterval area as a transmission interval of a synchronization message, and NextInterval for determining the next transmission timing when transmitting a synchronization message corresponding to the SMID, one each. It is configured including sequenceID in which data is incremented. Next Interval is a value determined by 128 ÷ Sync Interval, and is updated after sending out a synchronization message. The sequenceID is only written by incrementing the read value by one. The slave device 400 uses this sequence ID to confirm that there is no SYNC messge omission or order reversal.

FIG. 16 is an explanatory view showing an example of the operation of the scheduler 141. As shown in FIG. The scheduler 141 is configured by hardware, and executes the processes of steps S101 to S110 of FIG. 16 and the processes of steps S120 to S130 in parallel.
Upon acquiring the pulse per second from the precision time counter unit 142, the scheduler 141 executes step S101. In step S101, the scheduler 141 sets SyncID, SMID, SMID. Execute 0 clear of 3 counters of counter. SMID. The counter is a counter for detecting the timing of incrementing the SMID by one.

In step S102, the scheduler 141 determines whether it is time to transmit a synchronization message. Specifically, the scheduler 141 sets the SMID. It is determined whether the value of counter is 15,625 nanoseconds, which is the time boundary of SMID. SMID. The fact that the value of counter is a time boundary indicates that it is the timing to transmit a synchronization message.
If it is determined that the time is a time boundary (step S102: YES), the scheduler 141 increments the SMID by one in step S103. By this, the processing shifts to the processing of the next SMID.
In step S104, the scheduler 141 clears SMID.counter to 0 and generates an SMID pulse for the processing in step S120. This SMIDpulse indicates that the minimum period (128 PPS) for sending a synchronization message has elapsed. After step S104, the process proceeds to step S105.

On the other hand, in step S102, the SMID. If it is determined that the counter does not reach 15,625 nanoseconds (step S102: NO), the scheduler 141 determines in step S110 that the SMID. The counter is incremented by 1 and the process proceeds to step S102.
In step S105, the scheduler 141 determines whether the SMID has reached its maximum value 499.

If it is determined that the SMID has not reached 499 (step S105: NO), there is still an unprocessed SMID, and the process transitions to step S102.
On the other hand, when it is determined that the SMID has reached 499 (step S105: YES), this means that all the SMID processing has been completed, so that the scheduler 141 sets SMI = 0, that is, the initial value in step S106. Do.

In step S107, the scheduler 141 increments the Sync ID by one. By this, it proceeds to the process of the next SyncID.
In step S108, the scheduler 141 determines whether all SyncID processing has been completed. Specifically, the scheduler 141 determines whether the Sync ID is 127 or not.
When it is determined that the SyncID is 127 (Step S108: YES), the scheduler 141 sets SyncID = 0 in Step S109. After step S109, the process proceeds to step S102.
On the other hand, when it is determined in step S108 that the SyncID is other than 127 (step S108: No), there is a SyncID to be processed, so the process transitions to step S102.

In step S120, the scheduler 141 determines whether or not the SMID pulse is generated, that is, whether or not the synchronization message transmission timing has come.
If it is determined that the synchronization message transmission timing has come (step S120: YES), the process proceeds to step S121.
In step S121, the scheduler 141 converts the address of the DPRAM into the top address in which the SMID is stored.

In step S122, the scheduler 141 acquires Next Interval based on the offset value for which the start address has been determined.
In step S123, the scheduler 141 determines whether the NextInterval acquired in step S122 is the same as the Sync ID. If it is determined that they are not the same (step S123: No), the process proceeds to step S120. As a result, an SMID pulse waiting state is established.

On the other hand, when it is determined that the SyncID and the NextInterval are the same (step S123: Yes), this is the timing for transmitting the synchronization message, and the process transitions to step S124.
In step S124, the scheduler 141 reads SyncInterval from the SMID table.
In step S125, the scheduler 141 calculates 128 ÷ SyncInterval to update the current NextInterval.

In step S126, the scheduler 141 writes a value obtained by adding 128 ÷ Sync Interval to Next Interval into the SMID table. When the value of NextInterval becomes greater than 127 as a result of addition, a value obtained by subtracting 128 from the value is written to the SMID table.
In step S127, the scheduler 141 reads sequenceID from the SMID table.
Since IEEE 1588 v2 stipulates that sequenceID is incremented by one, in step S128, the scheduler 141 increments sequenceID.

In step S129, the scheduler 141 writes sequenceID back to the SMID table.
Since the process related to the series of synchronization messages is completed as described above, in step S130, the scheduler 141 transmits the synchronization message transmission pulse to the sync generation unit, and the process transitions to step S120.

FIG. 17 is an explanatory view showing an example of the flow of data at the time of sending a synchronization message.
In the figure, the transmission FIFO 133 is a FIFO memory for temporarily storing packets (CPU packets) other than the synchronization message among all the transmission packets from the grandmaster clock device 100.
In each packet, in addition to packet information, an SOF (start of frame) and an EOF (end of frame) are added before and after to clarify a break between packets.
TFIFO.EmptyFlag is a flag for notifying that the transmission FIFO 133 is empty.

TFIFO.ReadPulse is a pulse signal of one clock (CLK) for reading a bit width (hereinafter, one line) on the read side of the FIFO. When sending data continuously, TFIFO.ReadPulse may be asserted continuously.
TFIFO. DATA is packet data other than EOF, SOF or synchronization message, which is output one cycle after the pulse signal of TFIFO.ReadPulse.

The SYNC message FIFO 139 is an area in which a synchronization message is stored. Specifically, the synchronization message generated by the SYNC generation unit 135 is stored in the SYNC message FIFO 139.
SFIFO.EmptyFlag is a flag indicating the presence or absence of a synchronization message.
SFIFO. ReadPulse is a read pulse for performing the same operation as TFIFO.ReadPulse on the SYNC message FIFO.

SFIFO. DATA is data of one line constituting a synchronization message, which is output one cycle after the read pulse.
The Sync transmission unit 136 has a Sync Transmit rule ID area for selecting one of (1) forced discarding method, (2) high priority transmission method, and (3) transmission time reservation method. Then, the SYNC transmission unit 136 reads packet data from either the transmission FIFO 133 or the SYNC message FIFO 139 in accordance with the rule set in the Sync Transmit rule ID area. Then, the Sync sending unit 136 outputs the transmission data and DataEnable indicating that the transmission data is valid, to the transmission time stamp unit 137 which is a processing block of the subsequent stage.

FIG. 18 is an explanatory view showing an example of an operation performed by the Sync sending unit 136 in the case of the forced discard method.
In step S201, the Sync transmission unit 136 resets a counter or the like, and waits for a SYNC transmission start signal from the OS.
Next, the process proceeds to step S202, and the SYNC transmission unit 136 sets DataEnable = 0. The above is pre-processing.

In step S203, the SYNC transmission unit 136 determines the presence or absence of a synchronization message by referring to the SFIFO.EmptyFlag. If it is determined that a synchronization message exists (step S203: Not Empty), the process proceeds to step S204, and proceeds as transmission data, and the synchronization message SFIFO. Select DATA.
At S205, the SYNC sending unit 136 sets DataEnable = 1.
Thereafter, the process proceeds to step S203, and transmission processing is continued until transmission of the synchronization message is completed.

On the other hand, if it is determined in step S203 that no synchronization message is present (step S203: Empty), the process proceeds to step S210, and TFIFO. It is determined whether the transmission FIFO 133 is empty with reference to EmptyFlag.
If it is determined that the transmission FIFO 133 is empty (step S210: Empty), the process proceeds to step S202.

On the other hand, when it is determined that the transmission FIFO 133 is not empty (step S210: Not Empty), the process proceeds to step S211, and the SYNC transmission unit 136 transmits transmission data = TFIFO. Assume it is DATA.
In step S212, the SYNC transmission unit 136 performs data transmission processing (that is, transmission processing of CPU packets) other than the synchronization message with DATAEnable = 1.

In step S213, the SYNC transmission unit 136 determines the presence or absence of a synchronization message by referring to the SFIFO.EmptyFlag.
When it is determined that the synchronization message does not exist (step S213: Empty), the SYNC transmitting unit 136 continues the packet transmission processing other than the synchronization message.
On the other hand, when it is determined that the synchronization message is present (step S213: Not Empty), the process branches to step S204 and step S213. The processes after step S204 and the processes after step S213 are executed simultaneously and in parallel.

In step S214, the SYNC transmission unit 136 discards the data of the transmission FIFO 133 (TFIFO.DATA = discard).
In step S215, the SYNC sending unit 136 continuously processes the data read from the transmission FIFO 133.
In step S216, the SYNC transmission unit 136 determines whether the data read from the transmission FIFO 133 is EOF (TFIFO.DATA = EOF).

If it is determined that it is EOF (step S216: EOF), the process proceeds to step S203.
On the other hand, when it is determined that it is other than EOF (Step S216: Not EOF), the process proceeds to Step S214. In this case, the discarding process is continued in the loop of steps S214 to S216 until data of one packet is read out from the transmission FIFO 133 (until EOF).

FIG. 19 is an explanatory view showing an example of an operation performed by the Sync sending unit 136 in the case of the high priority sending method.
In step S301, the Sync sending unit 136 resets a counter or the like, and waits for a SYNC transmission start signal from the OS.
In step S302, the SYNC transmission unit 136 sets DataEnable = 0.

In step S303, the SYNC sending unit 136 outputs SFIFO. It is determined whether or not a synchronization message exists with reference to EmptyFlag. If it is determined that the synchronization message is present (Step S303: Not Empty), the transmission of the synchronization message is performed in Steps S304 to S305.
On the other hand, when it is determined in step S303 that no synchronization message exists (step S303: Empty), the process proceeds to step S310.

In step S310, the SYNC sending unit 136 outputs T.sub.FIFO. It is determined whether or not data (synchronization message) exists in the transmission FIFO 133 with reference to EmptyFlag. If it is determined that the transmission FIFO 133 is empty (the synchronization message does not exist) (step S310: Empty), the process proceeds to step S303.
On the other hand, when it is determined that data exists in the transmission FIFO 133 (step S310: Not Empty), the general message is sent out in steps S311, S312 and S313.

In step S313, the SYNC sending unit 136 outputs T.sub.FIFO. It is determined whether it is EOF or not with reference to DATA. If it is determined to be EOF (step S313: EOF), the process proceeds to step S302.
On the other hand, when it is determined that it is other than EOF (step S313: Not EOF), the process proceeds to step S310.

FIG. 20 is an explanatory view showing an example of an operation performed by the Sync sending unit 136 in the case of the transmission time reservation method.
In the transmission time reservation method, transmission of synchronization messages is started after waiting for 1542 octets time, which is the maximum packet size of IPv4. In the wait state in which the synchronization message exists, WaitFlag = 1. The WaitFlag is evaluated only at the start of transmission of a normal packet (CPU packet). When WaitFlag = 1, the normal packet is in the transmission suppression state. On the other hand, evaluation of WaitFlag is not performed during transmission of a normal packet. Furthermore, in the transmission time reservation method, the first routine for monitoring the status of the synchronization message and the operation of WaitFlag, and the second routine for starting transmission when WaitFlag = 0 at the start of transmission of the normal packet are simultaneously performed. To be executed.

  In the process of FIG. 20, in each of steps S401 and S420, the Sync sending unit 136 resets a counter or the like, and waits for a SYNC transmission start signal from the OS. The START1 state of step S401 and the START2 state of step S420 are assumed to be started at the same time.

In step S402, the SYNC transmission unit 136 sets DataEnable = 0.
In step S403, the SYNC transmission unit 136 sets WaitFlag = 0.
In step S404, the SYNC sending unit 136 outputs SFIFO. It refers to EmptyFlag to determine whether a synchronization message exists.
If it is determined that the synchronization message is present (Step S404: Not Empty), the process proceeds to Step S405.

  On the other hand, when it is determined that the synchronization message does not exist (the SYNC message FIFO 139 is empty) (step S404: Empty), the process proceeds to step S404. That is, a loop process is performed to reevaluate step S404.

In step S405, the SYNC transmission unit 136 substitutes SendWait = 1542, and advances the process to step S406.
In step S406, the SYNC transmission unit 136 sets WaitFlag = 1 and advances the process to step S407.
In step S407, the SYNC sending unit 136 subtracts one from SendWait.
In step S408, the SYNC transmission unit 136 determines whether SendWait is 0 or not. If it is determined that SendWait is not 0 (step S408: No), the process proceeds to step S407. In this case, the loop process of steps S407 to S408 is executed until SendWait = 0.

If it is determined in step S408 that SendWait = 0 (step S408: Yes), the process proceeds to step S409.
In step S409, the SYNC transmission unit 136 selects a synchronization message as transmission data (transmission data = SFIFO.DATA).
In step S410, the SYNC sending unit 136 sets DataEnable = 1.

In step S411, the SYNC sending unit 136 outputs SFIFO. It is determined whether the transmission FIFO 133 is empty with reference to EmptyFlag.
If it is determined that the transmission FIFO 133 is empty (step S411: Empty), the process proceeds to step S402.
On the other hand, when it is determined that the transmission FIFO 133 is not empty (a synchronization message exists) (step S411: Not Empty), the process proceeds to step S408. In this case, transmission of the synchronization message is continued.

In step S421, the SYNC transmitting unit 136 outputs T.sub.FIFO. It is determined whether the transmission FIFO 133 is empty with reference to EmptyFlag.
If it is determined that the transmission FIFO 133 is empty (step S421: Empty), the process proceeds to step S421. That is, a loop process of re-evaluating step S421 is executed.

On the other hand, if it is determined that the transmission FIFO 133 is not empty (step S421: Not Empty), that is, if it is determined that a general message exists, the process proceeds to step S422.
In step S422, the SYNC transmission unit 136 determines whether the WaitFlag is 0 or not. If it is determined that the WaitFlag is not 0 (WaitFlag = 1) (Step s422: No), that is, if it is a waiting time for sending a synchronization message, the process proceeds to Step S421.
If it is determined that WaitFlag = 0 (step S422: Yes), that is, if it is determined that it is not the transmission waiting time of the synchronization message, the process proceeds to step S423.
In step S423, the SYNC transmission unit 136 uses the general message TFIFO. Select DATA.
In step S424, DataEnable is set to 1.
After that, in step S425, the SYNC sending unit 136 outputs T.sub.FIFO. It is determined whether or not DATA = EOF.
If it is determined that it is EOF (step S425: EOF), the process proceeds to step S426. On the other hand, when it is determined that it is other than EOF (Step S425: Not EOF), the process proceeds to Step S423. In this case, transmission of the CPU packet (packet other than the synchronization message) is continued.
In step S426, the SYNC transmission unit 136 sets DataEnable = 0, and the process transitions to step S421.

FIG. 21 is an explanatory view showing how much transmission standby occurs in the transmission time reservation method.
The components of the packet shown in the figure are the same as in the case of FIG.
In FIG. 21, the SMID slot length is a time interval that can be assigned to one synchronization message when it is assumed that 128 synchronization messages per second are sent to 500 slaves. The SMID slot length = 15,625 ns represents that the minimum value of the synchronization message transmission interval is 15,625 nanoseconds.
The packet of 1542 octets indicates a packet having a maximum packet length of IPv4. The 1542 octets are 12336 bits, and if the line speed is 10 Gbps, the time required for transmission is 1234 nanoseconds. When the line speed is 10 Gbps, the time required to transmit the packet is 12336 nanoseconds. Both are shorter than 15625 nanoseconds and can be transmitted at synchronous message transmission intervals.

As described above, when the scheduler 141 determines that it is the transmission timing of the synchronization message, the Sync transmission unit 136 suppresses the transmission of the new synchronization message and the general message, and is defined as the time required to transmit the general message. After the specified time has elapsed, send a synchronization message.
As a result, the Sync sending unit 136 can always send the synchronization message from the state where the message sending is not performed after the specified time defined as the longest time required for sending the general message has elapsed. In this respect, the grand master clock device 100 can immediately transmit the synchronization message when the transmission timing of the synchronization message comes, and the transmission of the synchronization message (for example, time synchronization packet) and the general message (for example, time synchronization packet) The transmission interval of the synchronization message can be reduced without having to use a separate network address (e.g., an IP address) for the transmission of the packet.
Further, only when the scheduler 141 determines that it is the transmission timing of the synchronization message, the frequency at which the transmission of the general message is restricted is small in that the Sync transmission unit 136 suppresses the transmission of a new message. In this regard, the grandmaster clock device 100 can reduce the delay of sending general messages.

Also, SyncID is counted (one increment) at each interval defined as the minimum value of the synchronization message transmission interval to the same slave device 400. The SMID counts (increment by one) every interval obtained by further dividing the minimum value of the synchronization message transmission interval for the same slave device 400 by the number of time synchronization target devices. Then, the scheduler 141 determines, based on the value of SyncID, whether or not it is time to send a synchronization message to the slave device 400 indicated by SMID.
Thus, the scheduler 141 can detect the synchronization message transmission timing by a simple process of comparing the value of SyncID with the value associated with the slave device 400 indicated by the SMID.

  In the above, as shown in FIG. 12, the case where the MAC unit 130 performs each processing of detection of synchronization message transmission timing, generation of synchronization message, transmission of synchronization message and general message has been described as an example. The CPU 170 (FIG. 6) may perform all or part of these processes. For example, the OS kernel 173 may perform all or part of these processes.

  In this embodiment, queuing is always performed based on 1518 which is the maximum packet size in the definition of IEEE 802.3. May be output from the CPU 170. As described above, the grandmaster clock device 100 exchanges relatively short messages, called synchronization messages. The regular time (the above-mentioned waiting period) can be shortened if the general message sent by the grandmaster clock device 100 itself is 100 bytes at maximum using the IP fragmentation mechanism or the like. When the waiting period is shortened, and when a large bandwidth is required, such as a firmware version upgrade of the apparatus, the specified time may be returned to 1518 again.

The present invention is applicable to various time synchronization scenes. For example, the present invention may be applied to the following.
1. The GMC apparatus described in the present application used for time synchronization and frequency synchronization between mobile base stations. 2. GMC apparatus described in the present application used for time synchronization and frequency synchronization of each sensor in the sensor network. The GMC apparatus according to the present invention, which is used for synchronizing operation time of the protection relay apparatus of the power substation. 5. GMC apparatus described in the present application, used for synchronization of time and frequency of cameras, recording devices, video and video signal transmission apparatuses, management consoles, servers in the AV field such as audio and video. 5. GMC apparatus according to the present invention used for time and frequency synchronization in an in-vehicle network 7. GMC apparatus described in the present application which is used for time synchronization and frequency synchronization in an environment where a plurality of apparatuses such as SDN and NFV are configured and centralization setting is performed. The GMC apparatus according to the present application used in a mechanism for realizing QoS (Quality Of Service)

Note that a program for realizing all or a part of functions of the grandmaster clock device 100 is recorded in a computer readable recording medium, and the computer system reads the program recorded in the recording medium and executes it. The processing of each part may be performed by Here, the “computer system” includes an OS and hardware such as peripheral devices.
The "computer system" also includes a homepage providing environment (or display environment) if the WWW system is used.
The term "computer-readable recording medium" refers to a storage medium such as a flexible disk, a magneto-optical disk, a ROM, a portable medium such as a ROM or a CD-ROM, or a hard disk built in a computer system. Furthermore, “computer-readable recording medium” dynamically holds a program for a short time, like a communication line in the case of transmitting a program via a network such as the Internet or a communication line such as a telephone line. In this case, the volatile memory in the computer system which is the server or the client in that case, and the one that holds the program for a certain period of time is also included. The program may be for realizing a part of the functions described above, or may be realized in combination with the program already recorded in the computer system.

  The embodiment of the present invention has been described in detail with reference to the drawings, but the specific configuration is not limited to this embodiment, and design changes within the scope of the present invention are also included.

100 Grandmaster clock device 110 GNSS synchronous frequency oscillator 111 GNSS receiver 112 clock adjuster 113 crystal oscillator 120 physical layer chip 130 media access controller section 131 reception time stamp unit 132 reception FIFO
133 Transmit FIFO
134 Sync profile storage unit 134-1 Global profile storage unit 134-2 SMID profile storage unit 134-3 SMID table storage unit 135 Sync generation unit 136 Sync transmission unit 137 Transmission time stamp unit 139 Sync message FIFO
141 scheduler 142 precision time counter unit 150 crystal oscillator 160 main memory 170 CPU
171 hardware access unit 172 driver 173 OS kernel 174 GNSS management daemon 175 protocol stack 176 delayreq transmission processing unit 177 sync registration processing unit 181 memory controller

Claims (7)

A synchronous message transmitting apparatus for transmitting a synchronous message including time information, comprising:
A Sync registration processing unit that is executed by the CPU and acquires information on the transmission interval of the synchronization message;
A sending unit that operates using a clock signal that is more accurate than the clock signal used by the CPU , and sends the synchronization message and a general message that is a message other than the synchronization message;
It operates using a clock signal with higher accuracy than the clock signal used by the CPU, and determines whether it is the transmission timing of the synchronization message based on the information of the transmission interval of the synchronization message acquired by the Sync registration processing unit. The scheduler unit to
Equipped with
When the transmission unit determines that the scheduler unit is the transmission timing of the synchronization message, the transmission unit suppresses the transmission of the new synchronization message and the general message, and the specified time defined as the time required for the transmission of the general message has elapsed. Send out the synchronization message after
Synchronous message sender. A synchronization message generator for generating the synchronization message;
A general message generator for generating a general message which is a message other than the synchronization message;
Equipped with
The synchronization message generation unit is provided in a layer lower than the general message generation unit,
The synchronous message transmission device according to claim 1. A first counter that counts at intervals specified as the minimum value of the synchronization message transmission interval for the same time synchronization target device;
And a second counter for counting the minimum value of the synchronization message transmission interval for the same time synchronization target device by the number of time synchronization target devices.
The scheduler unit includes information on synchronization message transmission timing of a time synchronization target device specified by the value of the second counter among information on synchronization message transmission timing set for each of the time synchronization target devices , and the first information. Based on the comparison with the value of the counter, it is determined whether or not it is time to send a synchronization message to the time synchronization target device ,
The transmission unit transmits the synchronization message when it is determined that it is the timing to transmit the synchronization message by the scheduler unit.
The synchronous message transmission device according to claim 1 or 2 . The specified time is the maximum time required to send the general message.
The synchronous message transmission device according to any one of claims 1 to 3 . A synchronization message sending device and a time synchronization target device;
The synchronous message sending device
A synchronous message transmitting apparatus for transmitting a synchronous message including time information, comprising:
A Sync registration processing unit that is executed by the CPU and acquires information on the transmission interval of the synchronization message;
A sending unit that operates using a clock signal that is more accurate than the clock signal used by the CPU , and sends the synchronization message and a general message that is a message other than the synchronization message;
It operates using a clock signal with higher accuracy than the clock signal used by the CPU, and determines whether it is the transmission timing of the synchronization message based on the information of the transmission interval of the synchronization message acquired by the Sync registration processing unit. The scheduler unit to
Equipped with
When the transmission unit determines that the scheduler unit is the transmission timing of the synchronization message, the transmission unit suppresses the transmission of a new synchronization message and a general message, and the specified time defined as the time required to transmit the general message has elapsed And send out the synchronization message,
The time synchronization target device is
The time synchronization with the synchronous message transmitting device is performed based on the synchronous message transmitted by the synchronous message transmitting device.
Time synchronization system. A synchronous message transmitting method of a synchronous message transmitting device for transmitting a synchronous message including time information, comprising:
Executed by the CPU to obtain information on the sending interval of the synchronization message;
A sending step operating with a clock signal that is more accurate than a clock signal used by the CPU , and sending the synchronization message and a general message that is a message other than the synchronization message;
Determining using a clock signal that is more accurate than a clock signal used by the CPU, and determining whether it is a transmission timing of the synchronization message based on information of a transmission interval of the synchronization message;
Have
In the transmission step, when it is determined in the determination step that it is the transmission timing of the synchronization message, transmission of a new synchronization message and a general message is suppressed, and a prescribed time defined as a time required for transmission of the general message Sending out the synchronization message after
Synchronous message transmission method. A computer that controls a synchronization message transmitting device that transmits a synchronization message including time information;
Executed by the CPU to obtain information on the sending interval of the synchronization message;
A sending step operating with a clock signal that is more accurate than a clock signal used by the CPU , and sending the synchronization message and a general message that is a message other than the synchronization message;
Determining using a clock signal that is more accurate than a clock signal used by the CPU, and determining whether it is a transmission timing of the synchronization message based on information of a transmission interval of the synchronization message;
To run
In the transmission step, when it is determined in the determination step that it is the transmission timing of the synchronization message, transmission of a new synchronization message and a general message is suppressed, and a prescribed time defined as a time required for transmission of the general message A program for sending out the synchronization message after a lapse of.

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