CN114553350B - Deterministic low-delay message processing method - Google Patents
Deterministic low-delay message processing method Download PDFInfo
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- CN114553350B CN114553350B CN202011327510.1A CN202011327510A CN114553350B CN 114553350 B CN114553350 B CN 114553350B CN 202011327510 A CN202011327510 A CN 202011327510A CN 114553350 B CN114553350 B CN 114553350B
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- H04J3/00—Time-division multiplex systems
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- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- H—ELECTRICITY
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- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
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- H04L1/0017—Systems modifying transmission characteristics according to link quality, e.g. power backoff characterised by the adaptation strategy where the mode-switching is based on Quality of Service requirement
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Abstract
The invention relates to a rapid message processing method, in particular to a message processing circuit and a method which are used for an industrial network, are realized based on hardware, and have the characteristics of time certainty, low transmission delay and the like. The system comprises a receiving circuit, a digital phase-locked loop, a transmitting circuit and a local message interaction processing module. The circuit of the invention is oriented to an industrial network, and can provide low delay and low delay jitter based on hardware implementation. The method adopts the circuit structures of a fast forwarding circuit, a control state machine and the like, and provides lower and fixed message forwarding delay for messages which are not processed by industrial network nodes and only need to be forwarded to other nodes to be rapidly sent to a sending circuit. The circuit adopts circuit structures such as a digital phase-locked loop, a receiving circuit and the like, can synchronize a serial bus receiving signal to a local working clock, and can provide more accurate signal processing delay.
Description
Technical Field
The invention relates to a rapid message processing method, in particular to a message processing circuit and a method which are used for an industrial network, are realized based on hardware, and have the characteristics of time certainty, low transmission delay and the like.
Background
In the application scene of the industrial network, the certainty and low-delay index of message processing are important indexes of the industrial network, and the indexes are closely related to the performance of the industrial network system. The delay of message processing in the industrial network refers to the time spent by a certain node in the industrial network from the time of receiving the messages of other nodes to the time of starting to send the messages of the node; the certainty of message processing in an industrial network means that the delay jitter degree of the delay keeps a certain stability. The delay and the certainty among the network nodes have larger correlation with the performance of the industrial network system, and the technical indexes such as the response speed, the synchronization performance, the number of nodes, the minimum cycle period and the like of the industrial network system are determined.
The traditional industrial network message processing method comprises the following steps: whether the message is the message of the current node or not, the message is processed by a processor in the current node and then forwarded to the next node. In the process of processing the message by the node, the message needs to be processed by a processor or DMA, and is subjected to processes such as memory storage forwarding, so that larger delay is additionally introduced, and the controllability of delay jitter is poor. The message processing method adopts a hardware processing structure, and the message is directly transferred out of the sending port from the receiving port through fixed delay. Compared with the hardware message processing scheme, the traditional processing method has poorer performance in terms of time delay and certainty, and is not applicable to industrial network application scenes with strong real-time requirements; meanwhile, the clock at the network side is not synchronous with the local clock of the network node, so that the certainty of the data transmission delay cannot be ensured.
Disclosure of Invention
Aiming at the defects in the traditional industrial network message processing, the invention aims to provide a hardware-based low-delay deterministic message processing circuit and method for industrial network nodes, which are oriented to industrial network application scenes with strong real-time requirements. The circuit comprises two improvements on the traditional industrial network message processing circuit: firstly, a digital phase-locked loop circuit is added, and clock phase correction is carried out after a node receives a message and before the node sends the message; and secondly, a hardware processing structure is adopted, a fast forwarding circuit is added, and the message which is originally required to be processed by the memory store-and-forward structure is directly forwarded to the next node.
The technical scheme adopted by the invention for achieving the purpose is as follows:
a deterministic low-delay message processing method comprises the following steps:
the receiving circuit receives serial bus receiving signals from a network side, extracts an industrial network clock and outputs the industrial network clock to the digital phase-locked loop;
the digital phase-locked loop receives an industrial network clock and a local reference clock, generates a local working clock and a sending circuit clock, respectively sends the local working clock to the receiving circuit and the local message interaction processing module, and sends the sending circuit clock to the sending circuit;
the receiving circuit receives a local working clock, synchronizes a serial bus receiving signal to the local working clock, generates a serial bus receiving signal 1, and sends the serial bus receiving signal 1 to the local message interaction processing module;
the local message interaction processing module processes the serial bus receiving signal 1, generates a serial bus transmitting signal 1 and transmits the serial bus transmitting signal 1 to the transmitting circuit;
the transmitting circuit receives the serial bus transmitting signal 1 and transmits the serial bus transmitting signal to the industrial network in combination with the transmitting circuit clock.
The phase difference between the local working clock and the industrial network clock is kept fixed, and the phase difference between the sending circuit clock and the industrial network clock is kept fixed.
The processing of the serial bus receiving signal 1 by the local message interaction processing module comprises the following steps:
the checking circuit receives the serial bus receiving signal 1, generates a checking indication signal and sends the checking indication signal to the outside of the local message interaction processing module, namely other functional modules in the node;
the receiving serial-parallel conversion circuit receives a serial bus receiving signal 1 and a control signal 1 from a control state machine, converts the serial bus receiving signal 1 into parallel receiving data, sends the parallel receiving data to the outside of a local message interaction processing module, namely other functional modules in the local node, simultaneously generates a receiving timestamp latching signal, sends the receiving timestamp latching signal to the outside of the local message interaction processing module, namely other functional modules in the local node, and sends the parallel receiving data to the control state machine after receiving the control signal 1 from the control state machine;
the control state machine receives parallel received data, generates a received data field indication, sends the received data field indication to the outside of the local message interaction processing module, namely other functional modules in the node, sends a control signal 1 to a receiving serial-parallel conversion circuit, sends a control signal 2 to a sending parallel-serial conversion circuit, sends a control signal 3 to a fast forwarding circuit, and sends a control signal 4 to a verification generation circuit;
after receiving the control signal 2, the transmitting parallel-serial conversion circuit converts local parallel transmitting data from the outside of the local message interaction processing module into local transmitting data, transmits the local transmitting data to the fast forwarding circuit, and simultaneously generates a transmitting timestamp latching signal and transmits the transmitting timestamp latching signal to the outside of the local message interaction processing module, namely other functional modules in the node;
the fast forwarding circuit selectively processes the serial bus receiving signal 1 or local transmitting data according to the control signal 3 and transmits the serial bus receiving signal 1 or the local transmitting data as transmitting data to the verification generating circuit;
after receiving the transmission data, the check generating circuit generates transmission check data according to the control signal 4 and transmits the transmission check data to the quick forwarding circuit;
the fast forwarding circuit sends the serial bus receiving signal 1 or the local sending data plus the sending verification data as the serial bus sending signal 1 to the sending circuit according to the control signal 3.
The check indication signal is generated by any one of parity check, accumulation and check, or cyclic redundancy check.
A deterministic low latency message processing system comprising: the system comprises a receiving circuit, a digital phase-locked loop, a local message interaction processing module and a transmitting circuit, wherein:
the receiving circuit is used for receiving the serial bus receiving signal from the network side, extracting an industrial network clock, outputting the industrial network clock to the digital phase-locked loop and receiving a local working clock, synchronizing the serial bus receiving signal to the local working clock, generating a serial bus receiving signal 1, and sending the serial bus receiving signal 1 to the local message interaction processing module;
the digital phase-locked loop is used for receiving the industrial network clock and the local reference clock, generating a local working clock and a sending circuit clock, respectively sending the local working clock to the receiving circuit and the local message interaction processing module, and sending the sending circuit clock to the sending circuit;
the local message interaction processing module is used for processing the serial bus receiving signal 1, generating a serial bus sending signal 1 and sending the serial bus sending signal to the sending circuit;
and the transmitting circuit is used for receiving the serial bus transmitting signal 1 and transmitting the serial bus transmitting signal to the industrial network by combining a transmitting circuit clock.
The local message interaction processing module comprises: the system comprises a checking circuit, a receiving serial-parallel conversion circuit, a control state machine, a transmitting parallel-serial conversion circuit, a quick forwarding circuit and a checking generation circuit, wherein:
the checking and checking circuit is used for receiving the serial bus receiving signal 1, generating a checking indication signal and sending the checking indication signal to the outside of the local message interaction processing module;
the receiving serial-parallel conversion circuit is used for receiving the serial bus receiving signal 1 and the control signal 1 from the control state machine, converting the serial bus receiving signal 1 into parallel receiving data, sending the parallel receiving data to the outside of the local message interaction processing module, generating a receiving timestamp latching signal at the same time, sending the receiving timestamp latching signal to the outside of the local message interaction processing module, and sending the parallel receiving data to the control state machine after receiving the control signal 1 from the control state machine;
the control state machine is used for receiving parallel received data, generating a received data field indication, a control signal 1, a control signal 2, a control signal 3 and a control signal 4, sending the received data field indication to the outside of the local message interaction processing module, namely other functional modules in the node, sending the control signal 1 to a receiving serial-parallel conversion circuit for enabling serial-parallel conversion, sending the control signal 2 to a sending serial-parallel conversion circuit for controlling the conversion of local parallel sending data to local sending data, sending the control signal 3 to a quick forwarding circuit for controlling the multiplexing selection of the serial bus received signal 1, the local sending data and sending check data, and sending the control signal 4 to a check generation circuit for controlling the generation of sending check data;
the transmitting parallel-serial conversion circuit is used for converting the local parallel transmitting data from the outside of the local message interaction processing module into local transmitting data after receiving the control signal 2, transmitting the local parallel transmitting data to the fast forwarding circuit, generating a transmitting timestamp latching signal at the same time, and transmitting the transmitting timestamp latching signal to the outside of the local message interaction processing module;
the fast forwarding circuit is used for selectively processing the serial bus receiving signal 1 or the local transmitting data according to the control signal 3, transmitting the serial bus receiving signal 1 or the local transmitting data as transmitting data to the check generating circuit, and transmitting the serial bus receiving signal 1 or the local transmitting data plus the transmitting check data as the serial bus transmitting signal 1 to the transmitting circuit according to the control signal 3.
And the check generating circuit is used for generating the transmission check data according to the control signal 4 after receiving the transmission data and transmitting the transmission check data to the quick forwarding circuit.
The invention has the following beneficial effects and advantages:
1. the circuit of the invention is oriented to an industrial network, and can provide low delay and low delay jitter based on hardware implementation.
2. The circuit adopts circuit structures such as a digital phase-locked loop, a receiving circuit and the like, can synchronize a serial bus receiving signal to a local working clock, and can provide more accurate signal processing delay.
3. The invention adopts the circuit structures of a fast forwarding circuit, a control state machine and the like, and provides lower and fixed message forwarding delay for messages which are not processed by industrial network nodes and only need to be forwarded to other nodes to be rapidly sent to a sending circuit.
4. The circuit adopts circuit structures such as a digital phase-locked loop, a transmitting circuit and the like, and can adjust the clock of the serial bus transmitting signal 1 to a signal with a fixed phase difference with an industrial network clock, thereby avoiding the influence of local clock drift on industrial network data transmission.
Drawings
FIG. 1 is a block diagram of deterministic low latency message processing circuitry;
FIG. 2 is a schematic diagram of an industrial network circuit delay;
FIG. 3 is a schematic diagram of a fast forwarding circuit generating a message;
fig. 4 is a schematic diagram of the internal operation of the fast forwarding circuit;
FIG. 5 is a schematic diagram of the internal workings of the control state machine;
fig. 6 is a state transition diagram inside the state machine 1.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples.
When an asynchronous serial signal on the industrial network side passes through the receiving circuit, the receiving circuit can clock and sample the signal, and the serial signal is clock-synchronous with a local working clock.
The serial signal after clock synchronization is sent to a fast forwarding circuit, and the other path is sent to the local network node through a serial-parallel circuit; the local transmitting data can be changed into serial signals through the parallel-serial conversion circuit and sent to the quick forwarding circuit, the quick forwarding circuit can select to directly forward the serial signals from the network under the indication signal of the control state machine, the local serial data can also be transmitted, and meanwhile the check generating circuit is controlled to check the two serial data and generate check data.
The transmitting circuit adjusts the phase of the serial signal transmitted by the fast forwarding circuit according to the clock signal given by the digital phase-locked loop to form a signal with a fixed phase difference with the industrial network clock, and then the signal is transmitted to the industrial network.
The principle of the circuit of the invention is described as follows:
the receiving circuit is used for clock sampling of an asynchronous serial signal at the industrial network side, extracting of the clock signal at the industrial network side and clock synchronization of the asynchronous serial signal and a local working clock.
The digital phase-locked loop is used for generating a local working clock signal and a transmitting circuit clock signal which are at fixed phase offset with the industrial network clock according to the local reference clock and the industrial network clock.
The fast forwarding circuit acts like a selector, and under the instruction of the control signal 3 sent by the state control machine, the serial bus receiving signal 1 from the receiving circuit or the local transmitting data from the transmitting parallel-serial conversion circuit and the corresponding check data of the two data can be selected to be transmitted.
The function of the receiving serial-parallel conversion circuit is to convert the serial bus receiving signal 1 from the receiving circuit into multiple parallel signals, send the converted parallel receiving data to the local processor, and latch the time when the serial bus receiving signal 1 enters the receiving serial-parallel conversion circuit to generate a receiving timestamp latching signal.
The transmitting parallel-serial conversion circuit is used for carrying out parallel-serial conversion on local parallel transmission data from the local, transmitting the data after parallel-serial conversion to the fast forwarding circuit as local transmission data, and generating a transmission timestamp latching signal at the transmission moment.
The control state machine is used for receiving parallel received data from the receiving serial-parallel conversion circuit and then generating a received data field indication; the control signal 1, the control signal 2, the control signal 3 and the control signal 4 respectively control the serial-to-parallel conversion of the receiving serial-to-parallel conversion circuit, control the parallel-to-serial conversion of the transmitting parallel-to-serial conversion circuit, control the selection of the transmitting data of the quick forwarding circuit and control the generation and the transmission of the check data of the check generation circuit.
The function of the check circuit is to check the serial bus received signal 1 from the receiving circuit and check whether its check data is correct, and then generate a check indication signal.
The check generating circuit is used for performing check operation on the transmission data from the fast forwarding circuit under the instruction of the control signal 4 from the control state machine and sending the generated transmission check data back to the fast forwarding circuit.
The transmitting circuit adjusts the phase of the serial signal transmitted by the fast forwarding circuit according to the clock signal given by the digital phase-locked loop to form a signal with a fixed phase difference with the industrial network clock, and then transmits the signal to the industrial network.
The method of the invention comprises the following steps:
a. the receiving circuit receives serial bus receiving signals from a network side, extracts an industrial network clock and outputs the clock signals to the digital phase-locked loop;
b. the digital phase-locked loop receives an industrial network clock and a local reference clock from a receiving circuit, generates a local working clock and a sending circuit clock which keep a fixed phase difference with the industrial network clock, sends the local working clock to the receiving circuit and a local message interaction processing module, and sends the sending circuit clock to the sending circuit;
c. the receiving circuit receives a local working clock output by the digital phase-locked loop, synchronizes a serial bus receiving signal of a network side to the local working clock, generates a serial bus receiving signal 1, and sends the serial bus receiving signal 1 to a checking circuit, a receiving serial-parallel conversion circuit and a quick forwarding circuit of the local message interaction processing module;
d. the checking circuit receives the serial bus receiving signal 1 output by the receiving circuit, generates a checking indication signal and sends the checking indication signal to the outside of the local message interaction processing module;
e. the receiving serial-parallel conversion circuit receives a serial bus receiving signal 1 from the receiving circuit and a control signal 1 from the control state machine, converts the serial bus receiving signal 1 into parallel receiving data, sends the parallel receiving data to the outside of the local message interaction processing module, simultaneously generates a receiving timestamp latching signal, sends the receiving timestamp latching signal to the outside of the local message interaction processing module, and sends the parallel receiving data to the control state machine after receiving the control signal 1 from the control state machine;
f. the control state machine receives parallel received data from the receiving serial-parallel conversion circuit, generates a received data field indication, sends the received data field indication to the outside of the local message interaction processing module, sends a control signal 2 to the sending parallel-serial conversion circuit, sends a control signal 3 to the fast forwarding circuit, and sends a control signal 4 to the verification generating circuit;
g. after receiving the control signal 2, the transmitting parallel-serial conversion circuit converts local parallel transmitting data from the outside of the local message interaction processing module into local transmitting data, transmits the local transmitting data to the fast forwarding circuit, and simultaneously generates a transmitting timestamp latching signal and transmits the transmitting timestamp latching signal to the outside of the local message interaction processing module;
h. the fast forwarding circuit can selectively process the serial bus receiving signal 1 from the receiving circuit or the local transmitting data from the transmitting parallel-serial converting circuit under the instruction of the control signal 3, and sends the local transmitting data as transmitting data to the check generating circuit;
i. the check generating circuit receives the transmission data from the fast forwarding circuit, generates the transmission check data under the instruction of a control signal 4 from the control state machine and transmits the transmission check data to the fast forwarding circuit;
j. the fast forwarding circuit adds the serial bus receiving signal 1 or the local transmitting data with the transmitting check data under the instruction of the control signal 3, and then sends the serial bus receiving signal 1 or the local transmitting data to the transmitting circuit as the serial bus transmitting signal 1;
k. the transmitting circuit receives the serial bus transmitting signal 1 from the fast forwarding circuit and transmits the serial bus transmitting signal to the industrial network under the clock action of the transmitting circuit from the digital phase-locked loop.
The embodiment is written by using Verilog codes, and can be comprehensively realized by using a Synopsys DesignCompiler comprehensive tool.
The structural block diagram and the connection relation of the present embodiment are shown in fig. 1. In this embodiment, three kinds of data are transmitted, including the serial bus receiving signal 1, the local transmitting data, and the transmitting of the transmitting verification data. The embodiment only shows one implementation mode of the invention patent, and the variety of the transmitted data can be increased or decreased according to actual needs.
An input/output port of a deterministic low-delay message processing circuit implemented in this embodiment includes: the external input port comprises a serial bus receiving signal, a local reference clock and local parallel transmitting data; the external output port includes a serial bus transmit signal, a check indication signal, parallel receive data, receive timestamp latch signal, receive data field indication, transmit timestamp latch signal.
The functional modules of the deterministic low-delay message processing circuit comprise a receiving circuit module, a digital phase-locked loop module, a sending circuit module and a local message interaction processing module, wherein the local message interaction processing module comprises a checking circuit module, a fast forwarding circuit module, a receiving serial-parallel conversion circuit module, a control state machine module, a sending parallel-serial conversion circuit module and a checking generation module.
The connection relation of the present embodiment is as follows:
the external input serial bus receiving signal is connected to the receiving circuit module, and the receiving circuit module outputs the serial bus receiving signal 1 and the industrial network clock; the serial bus receiving signal 1 output by the receiving circuit module is connected to the local message interaction processing module;
the external input local reference clock is connected with the digital phase-locked loop module, the industrial network clock output by the receiving circuit is connected with the digital phase-locked loop module, and the digital phase-locked loop module outputs a local working clock and a sending circuit clock; the local working clock output by the digital phase-locked loop module is connected to the receiving circuit module and the local message interaction processing module, and the transmitting circuit clock output by the digital phase-locked loop module is connected to the transmitting circuit module;
the local message interaction processing module comprises a checking circuit module, a receiving serial-parallel conversion circuit module, a control state machine module, a quick forwarding circuit module, a transmitting parallel-serial conversion circuit module and a checking generation circuit module;
the serial bus receiving signal 1 output by the receiving circuit module is connected to a checking circuit module, a receiving serial-parallel circuit module and a quick forwarding circuit module in the local message interaction processing module;
the checking and checking circuit module outputs a checking indication signal to the outside;
the receiving serial-parallel conversion circuit module outputs parallel receiving data and a receiving timestamp latching signal to the outside, and outputs the parallel receiving data to the control state machine module;
the control state machine module outputs a control signal 1, a control signal 2, a control signal 3 and a control signal 4, and is respectively connected with the receiving serial-parallel conversion circuit module, the transmitting parallel-serial conversion circuit module, the quick forwarding circuit module and the verification generating circuit module to output a received data field indication to the outside;
the local parallel transmission data input from the outside is connected to the transmission parallel-serial conversion circuit module, and the transmission parallel-serial conversion circuit module outputs a transmission time stamp latching signal to the outside and outputs the local transmission data to the quick forwarding circuit module;
the quick forwarding circuit module outputs transmission data to the verification generating circuit module and outputs a serial bus transmission signal 1 to the transmitting circuit module;
the check generating circuit module outputs and sends check data to the quick forwarding circuit module;
the transmitting circuit module outputs a serial bus transmitting signal to the outside;
as shown in fig. 2, the circuit delay in this embodiment includes the delay of the receiving circuit module, the delay of the fast forwarding circuit module, and the delay of the transmitting circuit module.
As shown in fig. 3, the message generated by the fast forwarding circuit in this embodiment is selected from the serial bus receiving signal 1, the local transmitting data and the transmitting check data by the control signal 3.
The control state machine circuit principle is shown in fig. 5, wherein the received data analysis module adopts a general circuit structure, and functions are that a message start instruction, a data check start instruction, a message end instruction, a local data insertion start instruction and a local data insertion end instruction are extracted from parallel received data, the parallel received data is counted by the received data counter, a received data count value is output, the received data count value indicates current message receiving position information, the state machine 1 adopts a typical state machine circuit, the state transition is shown in fig. 6, and comprises an idle state, a state 1, a state 2 and a state 3, wherein the control signal 1 is reset, the control signal 2 is reset, the control signal 3 is reset, the control signal 4 is reset, the data receiving field indication signal indicates a reset state, the control signal 1 is set, the control signal 2 is reset, the control signal 3 is "serial bus receiving signal 1" strobe valid ", the data receiving field indication signal indicates a local data receiving state, the control signal 2 is set, the control signal 3 controls" local transmitting data "strobe valid", the data receiving field indication signal indicates a local data insertion state, the state 3 is shown in fig. 6, the state in which the idle state is shown in fig. 1, the state 3 is reset, the control signal 4 indicates the strobe signal valid, and the control signal indicates the state is set.
The principle of the fast forwarding circuit is shown in fig. 4, the multiplexer is controlled by a control signal 3, the control signal 3 gates the serial bus receiving signal 1, the local transmitting data and the transmitting check data respectively according to the state 1, the state 2 and the state 3 jump in the state controller, the selector outputs the transmitting data, and the transmitting data outputs the serial bus transmitting signal 1 after passing through the trigger. The trigger working clock is a local working clock, and the overall delay of the fast forwarding circuit is the trigger delay, namely the delay 2 in fig. 2.
Claims (4)
1. The deterministic low-delay message processing method is characterized by comprising the following steps of:
the receiving circuit receives serial bus receiving signals from a network side, extracts an industrial network clock and outputs the industrial network clock to the digital phase-locked loop;
the digital phase-locked loop receives an industrial network clock and a local reference clock, generates a local working clock and a sending circuit clock, respectively sends the local working clock to the receiving circuit and the local message interaction processing module, and sends the sending circuit clock to the sending circuit;
the receiving circuit receives a local working clock, synchronizes a serial bus receiving signal to the local working clock, generates a serial bus receiving signal 1, and sends the serial bus receiving signal 1 to the local message interaction processing module;
the local message interaction processing module processes the serial bus receiving signal 1, generates a serial bus transmitting signal 1 and transmits the serial bus transmitting signal 1 to the transmitting circuit;
the transmitting circuit receives the serial bus transmitting signal 1 and transmits the serial bus transmitting signal to the industrial network by combining a transmitting circuit clock;
the processing of the serial bus receiving signal 1 by the local message interaction processing module comprises the following steps:
the checking circuit receives the serial bus receiving signal 1, generates a checking indication signal and sends the checking indication signal to the outside of the local message interaction processing module, namely other functional modules in the node;
the receiving serial-parallel conversion circuit receives a serial bus receiving signal 1 and a control signal 1 from a control state machine, converts the serial bus receiving signal 1 into parallel receiving data, sends the parallel receiving data to the outside of a local message interaction processing module, namely other functional modules in the local node, simultaneously generates a receiving timestamp latching signal, sends the receiving timestamp latching signal to the outside of the local message interaction processing module, namely other functional modules in the local node, and sends the parallel receiving data to the control state machine after receiving the control signal 1 from the control state machine;
the control state machine receives parallel received data, generates a received data field indication, sends the received data field indication to the outside of the local message interaction processing module, namely other functional modules in the node, sends a control signal 1 to a receiving serial-parallel conversion circuit, sends a control signal 2 to a sending parallel-serial conversion circuit, sends a control signal 3 to a fast forwarding circuit, and sends a control signal 4 to a verification generation circuit;
after receiving the control signal 2, the transmitting parallel-serial conversion circuit converts local parallel transmitting data from the outside of the local message interaction processing module into local transmitting data, transmits the local transmitting data to the fast forwarding circuit, and simultaneously generates a transmitting timestamp latching signal and transmits the transmitting timestamp latching signal to the outside of the local message interaction processing module, namely other functional modules in the node;
the fast forwarding circuit selectively processes the serial bus receiving signal 1 or local transmitting data according to the control signal 3 and transmits the serial bus receiving signal 1 or the local transmitting data as transmitting data to the verification generating circuit;
after receiving the transmission data, the check generating circuit generates transmission check data according to the control signal 4 and transmits the transmission check data to the quick forwarding circuit;
the fast forwarding circuit sends the serial bus receiving signal 1 or the local sending data plus the sending verification data as the serial bus sending signal 1 to the sending circuit according to the control signal 3.
2. The method of claim 1, wherein the phase difference between the local operating clock and the industrial network clock is kept fixed, and the phase difference between the transmit circuit clock and the industrial network clock is kept fixed.
3. The method for processing deterministic low-latency messages according to claim 1, wherein said check indication signal is generated by any one of parity check, accumulation and check or cyclic redundancy check.
4. A deterministic low latency message processing system comprising: the system comprises a receiving circuit, a digital phase-locked loop, a local message interaction processing module and a transmitting circuit, wherein:
the receiving circuit is used for receiving the serial bus receiving signal from the network side, extracting an industrial network clock, outputting the industrial network clock to the digital phase-locked loop and receiving a local working clock, synchronizing the serial bus receiving signal to the local working clock, generating a serial bus receiving signal 1, and sending the serial bus receiving signal 1 to the local message interaction processing module;
the digital phase-locked loop is used for receiving the industrial network clock and the local reference clock, generating a local working clock and a sending circuit clock, respectively sending the local working clock to the receiving circuit and the local message interaction processing module, and sending the sending circuit clock to the sending circuit;
the local message interaction processing module is used for processing the serial bus receiving signal 1, generating a serial bus sending signal 1 and sending the serial bus sending signal to the sending circuit;
the transmitting circuit is used for receiving the serial bus transmitting signal 1 and transmitting the serial bus transmitting signal to the industrial network by combining a transmitting circuit clock;
the local message interaction processing module comprises: the system comprises a checking circuit, a receiving serial-parallel conversion circuit, a control state machine, a transmitting parallel-serial conversion circuit, a quick forwarding circuit and a checking generation circuit, wherein:
the checking and checking circuit is used for receiving the serial bus receiving signal 1, generating a checking indication signal and sending the checking indication signal to the outside of the local message interaction processing module;
the receiving serial-parallel conversion circuit is used for receiving the serial bus receiving signal 1 and the control signal 1 from the control state machine, converting the serial bus receiving signal 1 into parallel receiving data, sending the parallel receiving data to the outside of the local message interaction processing module, generating a receiving timestamp latching signal at the same time, sending the receiving timestamp latching signal to the outside of the local message interaction processing module, and sending the parallel receiving data to the control state machine after receiving the control signal 1 from the control state machine;
the control state machine is used for receiving parallel received data, generating a received data field indication, a control signal 1, a control signal 2, a control signal 3 and a control signal 4, sending the received data field indication to the outside of the local message interaction processing module, namely other functional modules in the node, sending the control signal 1 to a receiving serial-parallel conversion circuit for enabling serial-parallel conversion, sending the control signal 2 to a sending serial-parallel conversion circuit for controlling the conversion of local parallel sending data to local sending data, sending the control signal 3 to a quick forwarding circuit for controlling the multiplexing selection of the serial bus received signal 1, the local sending data and sending check data, and sending the control signal 4 to a check generation circuit for controlling the generation of sending check data;
the transmitting parallel-serial conversion circuit is used for converting the local parallel transmitting data from the outside of the local message interaction processing module into local transmitting data after receiving the control signal 2, transmitting the local parallel transmitting data to the fast forwarding circuit, generating a transmitting timestamp latching signal at the same time, and transmitting the transmitting timestamp latching signal to the outside of the local message interaction processing module;
the fast forwarding circuit is used for selectively processing the serial bus receiving signal 1 or the local transmitting data according to the control signal 3, transmitting the serial bus receiving signal 1 or the local transmitting data as transmitting data to the check generating circuit, and transmitting the serial bus receiving signal 1 or the local transmitting data plus the transmitting check data as the serial bus transmitting signal 1 to the transmitting circuit according to the control signal 3;
and the check generating circuit is used for generating the transmission check data according to the control signal 4 after receiving the transmission data and transmitting the transmission check data to the quick forwarding circuit.
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