JP3144078U - Baseband hardware transmission structure - Google Patents

Abstract

A baseband hardware transmission structure is provided.
Baseband hardware transmission structure includes wireless digital signal reception and transmission unit, bidirectional data interface, clock calibration function block, correlator, microcontroller, coder, clock incident control module, data serial parallel conversion module, direct memory access It is a combination design of block, receiving / transmitting module command controller and oscillator. A relatively low-frequency clock microcontroller can be used to provide precise timing synchronization of the frequency hop communication system, reducing power consumption during circuit operation, extending standby time, and effectively transmitting digital data packets And the message stability equivalent effect can be improved. Each type of baseband hardware transmission structure or similar structure can be applied.
[Selection] Figure 1

Description

  The present invention relates to a baseband hardware transmission structure, in particular, a wireless digital signal receiving / transmitting unit, a bidirectional data interface, a clock recovery calibration function block, a correlator, a microcontroller, a coder, a clock incident control module, a data serial parallel conversion module, a direct Including memory access block, receiving / transmitting module command controller, oscillator, clock recovery calibration function block is connected to the bidirectional data interface to extract the clock for recovery calibration, and the signal data from this unit and the transmitting end on the other side And the clock characteristics are received to achieve synchronization, the correlator compares whether the transmitted data and the connection code similarity of the unit reach the set condition, and then interrupts the data packet connection code Generate a signal Controller and the clock incident control module, generate a reception trigger signal, notify the data serial parallel conversion module that it is possible to start receiving signal data from the outside by the recovery calibration clock, the microcontroller Read and shift the control data, the clock incident control module receives the data packet sequence code interruption signal transmitted by the correlator, records the system time at the time of the interruption signal triggered by the hardware method, the data The serial-to-parallel conversion module is set based on the operation mode, and is output to the inside or receives data from the outside, and monitors several hardware system status occurrence system event interruption signals. Keep input in a certain order or run The coder executes forward error correction, cyclic redundancy check or scramble function on the received signal, thereby enabling a relatively low frequency clock microcontroller and the hardware circuit module of the present invention. Can be used to achieve functions that could only be completed with a well-known high-frequency clock microcontroller, can effectively improve the signal transmission and processing capabilities, and achieve accurate timing synchronization in the frequency hop communication system. Provides a base that can reduce the probability of errors occurring during digital signal transmission and processing, reduce power consumption during circuit operation, extend standby time, and achieve high-efficiency baseband digital data packet transmission The present invention relates to a band hardware transmission structure.

In known digital data computation and transmission, the microcontroller is often controlled by software to execute functions such as data extraction, computation, transmission and storage.
However, because the number of interruptions of the microcontroller is relatively large and data shifts are frequent, the microcontroller becomes a normal operating state. Since the system time extraction of the synchronization signal is different in the length of the pre-interrupt execution command, the system timing jitter is likely to increase, thus causing a data transmission error. The microcontroller must execute a meaningless retransmission or link reconstruction step, which reduces the computing power and overall digital data transmission efficiency of the microcontroller, and at the same time increases power consumption. Especially in portable audio equipment that emphasizes environmental protection, power saving, and transmission quality, it does not meet actual needs.

Known portable audio equipment usually needs to have the features of long use time and at the same time compact and lightweight.
In the operation function, if a high-speed calculation or transmission capability is to be provided, a high-clock chip, oscillator or microcontroller must be installed. As a result, the power consumption of the facility increases. If the power supply capacity is expanded, the compact and light weight feature cannot be realized, and the overall weight also increases.
The solution is to reduce the working clock within the unit time of the microcontroller, increase the standby state, and reduce power consumption.

  However, because the custom-made baseband circuit has the lowest energy consumption conditions and can maintain the basic functions of the facility for the first time, the 2.4 GHz ISM waveband Bluetooth (Blue Tooth) radio used in practice. Due to the digital signal module, the baseband circuit front end processing RF digital signal receiving and transmitting unit requires a minimum working clock of the oscillator of about 12 MHz. If the baseband circuit and the digital signal receiving / transmitting unit share the same oscillator, the power consumption of the system can be reduced.

  However, if an oscillator with a working clock of about 12 MHz is operated in transmission data, audio compression and digital signal processing, the clock speed is clearly insufficient. In addition, when a generally known data serial / parallel conversion module receives 8-bit external signal data, it generates one interruption signal to the microcontroller, causing excessive frequent interruption signals and excessive waiting time, and the microcontroller receives and transmits. It takes too much time to wait for data commands, and other tasks that require a relatively high processing clock such as call control or digital signal processing (voice band spectral analysis, voice compression) may be executed. Can not. In severe cases, the overall data transmission efficiency and the calculation speed are reduced, and at the same time, the power consumption is increased. Therefore, the user needs cannot be satisfied in actual use.

  The main objects of the present invention are a wireless digital signal receiving and transmitting unit, a bidirectional data interface, a clock recovery calibration function block (including a received data clock modifier), a correlator (including a shifter and a suffix code comparator), a micro Controller, coder, clock incident control module (including system clock, timer, system time extraction register, outgoing sync pulse generator), data serial parallel conversion module (including two incident monitor, data indicator, logic controller, shifter) The combination of the direct memory access block (including the random access memory and the memory arbitration multiplexer), the receiving / transmitting module command controller, the oscillator, etc., the similarity of the input data is set to a predetermined value by the correlation code comparator in the correlator. Reach Next, a sequence code interruption signal is generated and transmitted to the microcontroller and the clock incident control module at the same time, the system time of the interruption is interrupted, and the timing of the software extraction is relatively shaken by hardware extraction. The clock error generated by the signal is reduced, and the sequence code interruption signal simultaneously notifies the microcontroller system that the message reception has started, and both the microcontroller and the clock incident control module receive a homologous interruption signal (a microcontroller with a known structure is , By still enforcing other software directives, it is possible to avoid the discrepancy of the time it enters the interruption schedule and avoiding errors or delays in the interruption signal extraction timing and count) The microcontroller The time frame deviation error between this unit and the main clock device is adjusted and further corrected so that both maintain the function of communication or data transmission within an allowable error range. The introduction code comparator generates a reception trigger signal to the logic controller of the data serial parallel conversion module, thereby starting transmission of the received data from the serial parallel shifter and entering the memory, and the logic controller periodically performs memory arbitration multiplexing. To start external signal data reception, and at the same time suspend the execution priority of the data in the microcontroller shift memory. This control logic is supported by the direct memory access method and the microcontroller impact weighting mechanism. Expand the practicality of It is possible.

  The next object of the present invention is to generate a wake-up interruption signal, a packet transmission completion interruption signal and a data address interruption signal by two incident monitor and data indicator installed in the data serial / parallel conversion module, respectively. The serial-to-parallel conversion module and the microcontroller are connected to a memory arbitration multiplexer and a shared random access memory, which maintains the input or output of signals to the random access memory in a certain order and data serial parallel Whenever the conversion module receives 8-bit external signal data, it first stores it in a buffer of random access memory, and unlike the known procedure, it is first input to the microcontroller and processed, and the data address signal is received. Data absolute memory address When the received data reaches a certain capacity, the system sends a wake-up interruption signal in a timely manner, notifies the microcontroller to take the highest clock, and passes through the parallel bus and randomly. The access memory is temporarily processed a large amount of received data to greatly improve the microcontroller processing performance, and after packet transmission is completed and the packet data reception is completed, the microcontroller is notified that the data reception is ready. , Microcontrollers can use more time to execute other audio signals, digital signal processing, arithmetic or other applications, providing a baseband hardware transmission structure that can increase overall functionality and efficiency It is to be.

  Still another object of the present invention is to provide a baseband hardware transmission structure, wherein the bi-directional data interface is connected to the clock recovery calibration function block, and the received data clock modifier is installed by the clock recovery calibration function block. The sample clock of the signal received from the outside can be recovered, and at the same time, the function of synchronizing the sample clock with the local clock is provided.

  Still another object of the present invention is to provide a baseband hardware transmission structure, in which the coder performs a cyclic redundancy check on a received signal, and performs forward error correction and scramble functions on a transmitted signal. , Improve the functionality and safety of the signal transmission of the present invention.

In order to solve the above object, the present invention provides the following baseband hardware transmission structure.
Baseband hardware transmission structure is wireless digital signal reception and transmission unit, bidirectional data interface, clock recovery calibration function block, correlator, microcontroller, coder, clock incident control module, data serial parallel conversion module, direct memory access block, reception Including outgoing module command controller, oscillator,
The system time is monitored by the transmission synchronization pulse generator, and one data transmission time localization pulse is generated at the scheduled time. This pulse-triggered data serial / parallel conversion module starts reading and storing data in the random access memory to the shifter. And
The logic controller counts the data capacity already output, periodically fills the data and enters the shifter, the data serial parallel converter and the direct memory access block operation method are similar to the reception mode,
At the same time, the data is written to the random access memory with the highest clock via the microcontroller parallel bus.
As a result, the transmission and reception functions of the present invention achieve precise timing synchronization by using a relatively low-clock microcontroller hardware structure, reduce power consumption when operating the entire system circuit, extend standby time, and substantially In addition, the efficiency and safety of digital data packet transmission can be improved, and the overall utility and functionality can be expanded.

The invention of claim 1 is a wireless digital signal reception / transmission unit, bidirectional data interface, clock calibration function block, correlator, microcontroller, clock incident control module, data serial parallel conversion module, direct memory access block, coder, Receive and transmit module Instruction controller, including oscillator,
The wireless digital signal receiving and transmitting unit receives a signal;
The bidirectional data interface is connected to a wireless digital signal reception / transmission unit, receives a signal of the wireless digital signal reception / transmission unit 10,
The clock calibration function block is connected to the bidirectional data interface, calibrates the clock characteristics of the clock follow end and the clock independent end,
The correlator is connected to the clock calibration function block, and the correlator determines whether or not the joint code similarity of the input signal data reaches a predetermined value, and then generates a joint code interruption signal. , Transmit to the microcontroller and the clock incident control module, generate a reception trigger signal, notify the data serial parallel conversion module that it is possible to start receiving an external signal, the microcontroller authority from the direct memory access block Pause data access,
The microcontroller is connected to a correlator, direct memory access block, and coder, via a parallel bus, controls continuous reading and writing of data with the highest clock, and no output / input waiting time is required.
The clock incident control module is connected to a correlator, a data serial parallel conversion module, and an oscillator, receives a connection code interruption signal transmitted by the correlator, extracts a system time when the interruption signal is triggered, and simultaneously locks the time. Accurately plan the time frame signal synchronization with the system and attached digital time division multiplex audio equipment synchronization,
The data serial parallel conversion module is connected to a correlator, a microcontroller, a clock incident control module, and a direct memory access block, and has a baseband hardware transmission structure characterized by receiving signals.
According to a second aspect of the present invention, in the baseband hardware transmission structure according to the first aspect, the clock calibration function block is provided with a reception data clock modifier, which calculates a signal received from the outside by a local high frequency clock signal, The baseband hardware transmission structure is characterized by being a sample clock.
The invention of claim 3 is the baseband hardware transmission structure according to claim 1, wherein the correlator includes a shifter and a suffix code comparator,
The joint code comparator determines whether the joint code similarity of the input data reaches a predetermined value set in advance, and then generates a joint code interruption signal, which is simultaneously transmitted to the microcontroller and the clock incident control module. The base code hardware transmission structure is characterized by generating a reception trigger signal, notifying the data serial / parallel conversion module, and starting a signal from the other side.
The invention of claim 4 is the baseband hardware transmission structure according to claim 1, wherein the data serial to parallel conversion module is provided with two event monitors and one data indicator, each of which has two types of interruption signals. Generating a wake-up interruption signal (Wake_Int), a packet transmission completion interruption signal (Wrap_Int) and a data address interruption signal (Addr_Int), and the data serial / parallel conversion module connects a microcontroller and a shared random access memory. The baseband hardware transmission structure is as follows.
The invention of claim 5 is the baseband hardware transmission structure according to claim 1, wherein the wireless digital signal reception and transmission unit is further connected to a reception transmission module command controller. .
The invention of claim 6 is the baseband hardware transmission structure according to claim 1, wherein the direct memory access block includes a random access memory and a memory arbitration multiplexer.
A baseband hardware transmission structure according to claim 1, wherein a logic controller is installed in the data serial / parallel conversion module to control a received data arrangement of the system. It has a hardware transmission structure.
The invention according to claim 8 is the baseband hardware transmission structure according to claim 1, wherein the clock incident control module is provided with a system time extraction register, and the system time when the sequence code comparator generates an interruption signal, and The count is extracted and recorded, and by time lock, the clock follow end generates accurate system timing, serves as a reference for use by the attached correlation unit, and serves as a counter for the communication synchronization time frame reception transmission time slot The baseband hardware transmission structure is as follows.
The invention according to claim 9 is the baseband hardware transmission structure according to claim 1, wherein the coder transmits signal data from a random access memory to the coder by a microcontroller after receiving signal data, and error detection and decoding such as cyclic redundancy check. The baseband hardware transmission structure is characterized in that the above functions are implemented.

The invention of claim 10 is a wireless digital signal receiving / transmitting unit, bidirectional data interface, clock calibration function block, correlator, microcontroller, clock incident control module, data serial parallel conversion module, direct memory access block, coder , Including receiving and sending module command controller, oscillator,
The digital signal receiving / transmitting unit transmits a signal,
The bidirectional data interface is connected to the digital signal reception / transmission unit, and is used for signal transmission of the wireless digital signal reception / transmission unit.
The microcontroller is connected to a correlator, direct memory access block, and coder, via a parallel bus, controls continuous reading and writing of data with the highest clock, and no output / input waiting time is required.
The clock incident control module is connected to a correlator, a data serial parallel conversion module, and an oscillator;
The data serial parallel conversion module is connected to a correlator, a microcontroller, a clock incident control module, and a direct memory access block, and has a baseband hardware transmission structure characterized by transmitting signals.
The invention of claim 11 is a baseband hardware transmission structure according to claim 10, wherein the wireless digital signal reception and transmission unit is further connected to a reception transmission module command controller. .
A twelfth aspect of the invention is the baseband hardware transmission structure according to the tenth aspect, wherein the direct memory access block includes a random access memory and a memory arbitration multiplexer.
The invention of claim 13 is the baseband hardware transmission structure according to claim 10, wherein a logic controller is installed in the data serial / parallel conversion module to control data schedule transmission of the system. It has a hardware transmission structure.
The invention of claim 14 is the baseband hardware transmission structure according to claim 10, wherein the coder transmits data from the random access memory to the coder by a microcontroller before sending out the signal data, and functions of forward error correction and scramble. The baseband hardware transmission structure is characterized by the following.

  The present invention achieves functions that could only be completed with a relatively high-speed clock microcontroller by means of a relatively low-frequency clock microcontroller hardware structure, and substantially effective signal transmission efficiency and processing capability. Can improve message stability, provide accurate timing synchronization of radio frequency hop communication system, reduce the probability of error during signal transmission and processing, reduce power consumption during circuit operation, and reduce waiting time Extending and achieving high efficiency digital data packet transmission equivalent effect, can enhance the overall function and efficiency.

  As shown in FIG. 1, the baseband hardware transmission structure of the present invention includes a wireless digital signal receiving / transmitting unit 10, a bidirectional data interface 20, a clock calibration function block 30 (including a received data clock modifier 31), a correlator ( Correlator) 40 (including shifter 41 and connection code comparator 42), microcontroller (MCU-Micro Control Unit) 50, coder (Coder) 90, clock incident control module 60 (system clock 61 (System Clock), transmission synchronization) Including a pulse generator 62, a system time extraction register 63, a timer 64), a data serial / parallel conversion module 70 (including two event monitors 71 and 72, a data indicator 73, a shifter 74, and a logic controller 75), Direct memory access block 100 (random An access memory (RAM-Random-Access Memory) 80, a memory arbitration multiplexer 130), a reception / transmission module command controller 120, and an oscillator 110.

The bidirectional data interface 20, the clock calibration function block 30, the correlator 40, the microcontroller 50, the clock incident control module 60, the data serial / parallel conversion module 70, the coder 90, the direct memory access block 100, and the reception / transmission module command controller 120. Constitutes the system module 150.
The wireless digital signal reception / transmission unit 10 receives and transmits a wireless digital signal.
The bidirectional data interface 20 is connected to the wireless digital signal reception / transmission unit 10 and transmits signals through the wireless digital signal reception / transmission unit 10.
The clock calibration function block 30 is connected to the bidirectional data interface 20. The clock calibration function block 30 is provided with a reception data clock corrector 31 to calibrate and synchronize the data and clock characteristics of this apparatus and external signals.

The order code comparator 42 of the correlator 40 is connected to the clock calibration function block 30. The function will be described below.
It is compared and contrasted whether or not the similarity of the joint code of the signal received from the outside reaches a predetermined value set in advance. After completion of the comparison, a sequence code interruption signal (Access Code_Int) is generated and transmitted to the microcontroller 50 and the system time extraction register 63 of the clock event control module 60. The hardware extracts and records the time of the connection code interruption signal triggering system, uses it as a reference for system timing adjustment, improves the accuracy of signal timing synchronization, and avoids the occurrence of signal extraction errors due to timing fluctuations can do. In addition, since the microcontroller 50 having a known structure is still executing another software command, the time when it enters the interruption schedule is inconsistent, and the timing generation error of the connection code interruption signal or the inconsistency delay is caused. It is possible to simultaneously avoid inadequate accuracy of system synchronization.

Thus, the microcontroller 50 has accurate data and the time adjusts the time frame shift error, so that the clock follow end and the clock voluntary end maintain the communication or data transmission function within an allowable error range.
The comparator 42 of the correlator 40 generates a reception trigger signal (Rx_Trig), notifies the logic controller 75 of the data serial / parallel conversion module 70, generates a control signal, and starts receiving data from the shifter 74. When the periodic data is completed, the authority of the memory arbitration multiplexer 130 is acquired, and the microcontroller 50 temporarily stops data access from the random access memory 80. In addition, the received data is stored in a random memory based on the data indexer 73 localization index. When the received external data reaches a certain capacity, the incident monitor 71 of the data serial / parallel conversion module 70 transmits a wake-up interruption signal (Wake_Int) in a timely manner based on the actual request and notifies the microcontroller 50 of the standby state. The random access memory 80 is temporarily stopped to process a large amount of data that has already been received, thereby expanding the capacity and efficiency of the microcontroller processing.
After the data reception is completed, the event monitor 72 of the data serial / parallel conversion module 70 transmits a packet transmission completion interruption signal (Wrap_Int) and notifies the microcontroller 50 to complete the data reception, thus reading, processing and computing the data. Or transmit the data signal to other attached audio processing units to expand the practicality and functionality of the entire invention (see FIG. 2).

  The microcontroller 50 includes a correlator 40, a direct memory access block 100, a coder 90 (the coder 90 is used for forward error correction (FEC), cyclic redundancy check (CRC), and scramble (Scramble). Three types of functions can be executed: before sending the signal data and after receiving the signal data, the microcontroller 50 transmits the data from the random access memory 80 to the coder 90, and errors such as forward error correction, scramble or cyclic redundancy check, etc. Detecting, encoding and decoding functions are implemented to improve the data safety and system stability of the present invention.) And connected to the data serial to parallel conversion module 70 to control data access (including the correlator). 40 is a shifter 41 and a joint code comparator ( Thresholder) 42, and the joint code comparator 42 determines whether the joint code similarity of the input signal data has reached a predetermined value, and then transmits a joint code interruption signal. It communicates to the microcontroller 50 and the clock incident control module 60. The joint code comparator 42 also generates a reception trigger signal (Rx_Trig), notifies the data serial parallel conversion module 70, and starts receiving data from the other side. be able to).

The clock incident control module 60 is connected to the correlator 40 and the data serial / parallel conversion module 70, receives a connection code interruption signal (Access Code_Int) transmitted by the connection code comparator 42 of the correlator 40, and receives the interruption. Extract and record the system time at the time of the signal incident. At the same time, the clock follow-end locked radio communication system timing is readjusted by time comparison, and a reference for use is provided to the attached correlation unit, and the communication synchronization time frame reception transmission time slot (Time Slot) is the starting point.
The data serial / parallel conversion module 70 includes two incident monitors 71 and 72 and a data indicator 73, and generates interruption signals for the two types of control microcontrollers 50, respectively.
The wake-up interruption signal (Wake_Int), the packet transmission completion interruption signal (Wrap_Int), and the data access address signal are used as an address reference index for storing data in the random access memory 80. Thus, the data is extracted from the subsequent time slot (Time Slot), Processing and calculation are executed.

  In the shipping state (see FIG. 3), the system time slot (Time Slot) is planned to be controlled by the clock incident control module 60, and one pulse is sent to the data serial / parallel conversion module 70 via the transmission synchronization pulse generator 62. The instruction logic controller 75 generates a control signal to the memory arbitration multiplexer 130, temporarily stops accessing data from the random access memory 80 at the slot position of the microcontroller 50, and further via the parallel bus. The maximum clock periodicity compensated transmission data is taken and sent to the shifter 74 of the data serial / parallel conversion module 70, and the signal is thus conceived through the bidirectional data interface 20 and the wireless digital signal receiving / transmitting unit 10.

Among them, the wireless digital signal reception / transmission unit 10 further connects a reception / transmission module command controller 120.
Separately, the random access memory 80 further connects a memory arbitration multiplexer 130, which first connects the microcontroller 50 and the data serial to parallel conversion module 70 so that the signals are in a fixed schedule order. Write or read random access memory to control data access.
In addition, the oscillation clock of the system module 150 is uniformly provided by the oscillator 110, and the oscillation clock of the system module 150 is also output to the wireless digital signal receiving / transmitting unit 10 to share the design of the same oscillator 110, thereby Power consumption can be reduced, clock synchronization accuracy can be enhanced, and overall functionality can be expanded.

It is a connection block chart of an example of the present invention. 5 is a flowchart of a receiving embodiment of the present invention. It is a flowchart of this invention dispatch example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Wireless digital signal reception transmission unit 20 Bidirectional data interface 30 Clock calibration function block 31 Reception data clock modifier 40 Correlator 41 Shifter 42 Order code comparator 50 Microcontroller 60 Clock incident control module 61 System clock 62 Transmission synchronous pulse generation Device 63 System time extraction register 64 Timer 70 Data serial parallel conversion module 71 Incident monitor 72 Incident monitor 73 Data indicator 74 Shifter 75 Logic controller 80 Random access memory 90 Coder 100 Direct memory access block 110 Oscillator 120 Receive transmission module command controller 130 Memory Arbitration Multiplexer 150 System Module

Claims (14)

Wireless digital signal reception and transmission unit, bidirectional data interface, clock calibration function block, correlator, microcontroller, clock incident control module, data serial parallel conversion module, direct memory access block, coder, reception transmission module command controller, Including an oscillator,
The wireless digital signal receiving and transmitting unit receives a signal;
The bidirectional data interface is connected to a wireless digital signal reception / transmission unit, receives a signal of the wireless digital signal reception / transmission unit 10,
The clock calibration function block is connected to the bidirectional data interface, calibrates the clock characteristics of the clock follow end and the clock independent end,
The correlator is connected to the clock calibration function block, and the correlator determines whether or not the joint code similarity of the input signal data reaches a predetermined value, and then generates a joint code interruption signal. , Transmit to the microcontroller and the clock incident control module, generate a reception trigger signal, notify the data serial parallel conversion module that it is possible to start receiving an external signal, the microcontroller authority from the direct memory access block Pause data access,
The microcontroller is connected to a correlator, direct memory access block, and coder, via a parallel bus, controls continuous reading and writing of data with the highest clock, and no output / input waiting time is required.
The clock incident control module is connected to a correlator, a data serial parallel conversion module, and an oscillator, receives a connection code interruption signal transmitted by the correlator, extracts a system time when the interruption signal is triggered, and simultaneously locks the time. Accurately plan the time frame signal synchronization with the system and attached digital time division multiplex audio equipment synchronization,
A baseband hardware transmission structure, wherein the data serial to parallel conversion module is connected to a correlator, a microcontroller, a clock incident control module and a direct memory access block to receive a signal.   2. The baseband hardware transmission structure according to claim 1, wherein the clock calibration function block is a sample clock that is provided with a reception data clock modifier, calculates a signal received from the outside by a local high frequency clock signal, and reduces the signal. Feature baseband hardware transmission structure. The baseband hardware transmission structure of claim 1, wherein the correlator includes a shifter and a suffix code comparator;
The joint code comparator determines whether the joint code similarity of the input data reaches a predetermined value set in advance, and then generates a joint code interruption signal, which is simultaneously transmitted to the microcontroller and the clock incident control module. The baseband hardware transmission structure characterized in that the connection code comparator generates a reception trigger signal, notifies the data serial / parallel conversion module, and starts a signal from there.   2. The baseband hardware transmission structure according to claim 1, wherein the data serial / parallel conversion module includes two incident monitors and one data indicator, each of which has two types of interruption signals, a wake-up interruption signal (Wake_Int ), A packet transmission completion interruption signal (Wrap_Int) and a data address interruption signal (Addr_Int) are generated, and the data serial-to-parallel conversion module connects a microcontroller and a shared random access memory. Construction.   2. The baseband hardware transmission structure according to claim 1, wherein the wireless digital signal reception / transmission unit is further connected to a reception transmission module command controller.   2. The baseband hardware transmission structure according to claim 1, wherein the direct memory access block includes a random access memory and a memory arbitration multiplexer.   2. The baseband hardware transmission structure according to claim 1, wherein a logic controller is installed in the data serial / parallel conversion module to control a received data arrangement of the system.   The baseband hardware transmission structure of claim 1, wherein the clock incident control module has a system time extraction register to extract and record the system time and count when the sequence code comparator generates a break signal; Baseband hardware transmission characterized by time-locking, clock follow-end generates accurate system timing, serves as a reference for use by the attached correlation unit, and serves as a counter for communication synchronization time frame reception transmission time slot Construction.   2. The baseband hardware transmission structure according to claim 1, wherein after receiving the signal data, the coder transmits data from the random access memory to the coder by a microcontroller to perform error detection and decoding functions such as cyclic redundancy check. Feature baseband hardware transmission structure. Wireless digital signal reception and transmission unit, bidirectional data interface, clock calibration function block, correlator, microcontroller, clock incident control module, data serial parallel conversion module, direct memory access block, coder, reception transmission module command controller, Including an oscillator,
The digital signal receiving / transmitting unit transmits a signal,
The bidirectional data interface is connected to the digital signal reception / transmission unit, and is used for signal transmission of the wireless digital signal reception / transmission unit.
The microcontroller is connected to a correlator, direct memory access block, and coder, via a parallel bus, controls continuous reading and writing of data with the highest clock, and no output / input waiting time is required.
The clock incident control module is connected to a correlator, a data serial parallel conversion module, and an oscillator;
A baseband hardware transmission structure, wherein the data serial to parallel conversion module is connected to a correlator, a microcontroller, a clock incident control module, and a direct memory access block to transmit a signal.   11. The baseband hardware transmission structure according to claim 10, wherein the wireless digital signal reception / transmission unit is further connected to a reception transmission module command controller.   11. The baseband hardware transmission structure according to claim 10, wherein the direct memory access block includes a random access memory and a memory arbitration multiplexer.   11. The baseband hardware transmission structure according to claim 10, wherein a logic controller is installed in the data serial / parallel conversion module to control system data schedule transmission.   11. The baseband hardware transmission structure according to claim 10, wherein the coder transmits data from a random access memory to a coder by a microcontroller before sending out signal data, and performs forward error correction and scramble functions. Baseband hardware transmission structure.

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