WO2024067131A1 - Power consumption optimization method, communication device, and computer readable storage medium - Google Patents

Abstract

The present application discloses a power consumption optimization method, a communication device, and a computer readable storage medium. The power consumption optimization method is applied to a receiving module, and comprises: receiving a power-saving state indication signal (S410); and according to the power-saving state indication signal, performing link setup state protection processing on a first data link layer of the receiving module, performing clock data recovery state locking processing on a first serial-to-parallel conversion interface of the receiving module, and disabling data processing-based first clock gating in the first serial-to-parallel conversion interface (S420).

Description

Power consumption optimization method, communication device and computer readable storage medium

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based on the Chinese patent application with application number 202211214427.2 and application date September 30, 2022, and claims the priority of the Chinese patent application. The entire content of the Chinese patent application is hereby introduced into this application as a reference.

Technical Field

The present application relates to the field of communication technology, and in particular to a power consumption optimization method, a communication device, and a computer-readable storage medium.

Background technique

ADC and DAC technology, namely analog/digital and digital/analog conversion technology, is a bridge between the analog and digital worlds. It is widely used in medical, instrumentation, communication, radar and other fields, and is an important part of modern digital signal processing systems. In communication systems, with the advent of the 5G era, data service needs are rapidly expanding, requiring larger bandwidth and smaller latency, and also requiring higher interface throughput between ADC, DAC and digital processing chips. Based on this technology development trend, multiple versions of the data converter interface standard JESD204 have been released. This protocol is based on the SERDES interface, which enables high-speed data transmission between ADC/DAC and data processing chips. Although the JESD204 protocol solves the requirements of high-throughput interfaces, as the throughput increases, the line rate of the serial-to-parallel conversion interface becomes higher and higher, and the power consumption of the serial-to-parallel conversion interface also increases. For power-sensitive product equipment, each system is adopting a power reduction solution.

In the related art, during the interface application stage, the serial-to-parallel conversion interface is in a reset state when the system is in sleep mode to reduce power consumption. When the SERDES interface is in a reset state, the receiving side and the transmitting side are in a disconnected state. To recover from a low-power state to a normal working state, it is necessary to re-establish the link. The process of re-establishing the link is complicated, and the link establishment time is long, making it difficult to quickly switch from a low-power state to a normal working state.

Summary of the invention

Embodiments of the present application provide a power consumption optimization method, a communication device, and a computer-readable storage medium.

In the first aspect, an embodiment of the present application provides a power consumption optimization method, which is applied to a receiving module, including: receiving a power saving status indication signal; performing link establishment status protection processing on the first data link layer of the receiving module according to the power saving status indication signal, performing clock data recovery status locking processing on the first serial-to-parallel conversion interface of the receiving module, and closing the first clock gating related to data processing in the first serial-to-parallel conversion interface.

In the second aspect, an embodiment of the present application provides a power consumption optimization method, which is applied to a sending module, including: receiving a power saving status indication signal; and according to the power saving status indication signal, shutting down a fourth clock gating related to data processing in a second serial-to-parallel conversion interface of the sending module.

In a third aspect, an embodiment of the present application further provides a communication device, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the power consumption optimization method as described in the first aspect or the second aspect is implemented.

In a fourth aspect, an embodiment of the present application further provides a computer-readable storage medium storing computer-executable instructions, wherein the computer-executable instructions are used to execute the power consumption optimization method as described in the first aspect or the second aspect.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram of power saving of a time division duplex communication system provided by an embodiment of the present application;

FIG2 is a functional structure diagram of a communication interface provided by an embodiment of the present application;

3 is a functional structure diagram of a communication interface with a power saving function provided by an embodiment of the present application;

FIG4 is a flow chart of a power consumption optimization method applied to a receiving module provided in an embodiment of the present application;

FIG5 is a schematic flow chart of a method of step S420 in FIG4 ;

FIG6 is a schematic diagram of the structure of block data provided by an embodiment of the present application;

FIG7 is a schematic diagram of a jump of a synchronization header locking process of block data provided by an embodiment of the present application;

FIG8 is a schematic diagram of the structure of multiple frames of data provided by an embodiment of the present application;

FIG9 is a schematic diagram of a jump of a frame header locking process of multi-frame data provided by an embodiment of the present application;

FIG10 is a flow chart of another method of step S420 in FIG4 ;

FIG11 is a schematic diagram of a reference clock relationship of a communication interface provided by an embodiment of the present application;

FIG12 is a flow chart of a power consumption optimization method applied to a receiving module according to another embodiment of the present application;

13 is a schematic flow chart of a power consumption optimization method applied to a sending module according to an embodiment of the present application;

14 is a schematic flow chart of a power consumption optimization method applied to a sending module according to another embodiment of the present application;

15 is a schematic diagram of a power saving working state in a communication interface provided by an embodiment of the present application when the communication interface does not support clock gating shutdown;

FIG. 16 is a schematic diagram of the structure of a communication device provided in an embodiment of the present application.

Detailed ways

In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the embodiments described herein are only used to explain the present application and are not used to limit the present application.

It should be noted that, in the description of the present application, the meaning of "several" is one or more, the meaning of "more" is more than two, and "greater than", "less than", "exceeding", etc. are understood to not include the number itself. In addition, although the logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in an order different from that in the flowchart. The terms "first", "second", etc. in the specification are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

In the communication system, with the advent of the 5G era, the demand for business data has expanded rapidly, requiring larger bandwidth and smaller latency, and also requiring higher interface throughput between ADC, DAC and digital processing chips. Multiple versions of the data converter interface standard JESD204 standard have been released one after another. The protocol is based on the SERDES interface, which enables high-speed data transmission between ADC/DAC and data processing chips. However, with the increase in throughput, the line rate of the serial-to-parallel conversion interface is getting higher and higher, and the power consumption of the serial-to-parallel conversion interface is also getting higher and higher. In the related art, in the interface application stage, the serial-to-parallel conversion interface is reset when the system is dormant to reduce power consumption. When the SERDES interface is in the reset state, the receiving side and the sending side are in a broken link state. To recover from a low-power state to a normal working state, it is necessary to re-establish the link. The process of re-establishing the link is complicated, and the link establishment time is long, requiring several milliseconds, and it is difficult to quickly switch from a low-power state to a normal working state.

Based on this, the present application provides a power consumption optimization method, a communication device, and a computer-readable storage medium. According to the solution of the embodiment of the present application, the receiving module of the communication device receives the power saving state indication signal; then, according to the power saving state indication signal, the first data link layer of the receiving module performs link state protection processing; finally, the first serial-to-parallel conversion interface of the receiving module The first serial-to-parallel conversion interface performs clock data recovery state locking processing, and turns off the first clock gating related to data processing in the first serial-to-parallel conversion interface. That is to say, the solution of the embodiment of the present application can effectively reduce the power consumption of the communication interface and achieve power saving by turning off the first clock gating in the first serial-to-parallel conversion interface of the sending module and performing link establishment state protection processing at the first data link layer, thereby improving the energy efficiency of the system and being able to quickly switch between the power saving state and the communication state.

The embodiments of the present application are described below in conjunction with the accompanying drawings.

Referring to FIG. 1 , FIG. 1 is a schematic diagram of power saving of a time division duplex communication system provided by an embodiment of the present application. The time division duplex mode is to divide the time according to a certain ratio, the downlink works in a period of time, and the uplink works in another period of time. As shown in FIG. 1 , the time division duplex communication system includes a sending channel and a receiving channel. Among them, the time division duplex communication system has a sending period and a receiving period. In the sending period, the sending channel is in a normal communication state, and the receiving channel is in a power saving state; and in the receiving period, the sending channel is in a power saving state, and the receiving channel is in a normal communication state. It can be understood that the time division duplex communication system has a timing control unit, and the timing control unit can preset the sending period and the receiving period, and generate an indication signal (such as an indication point level) that can identify the sending period and the receiving period. In some embodiments, when the sending channel or the receiving channel enters the normal communication state, the time division duplex communication system can generate a communication state indication signal; when the sending channel or the receiving channel enters the power saving state, the time division duplex communication system can generate a power saving state indication signal.

In order to meet the rapidly expanding data services, communication interfaces are provided on both the sending channel and the receiving channel of the time division duplex communication system. In some embodiments, the communication interface is a JESD204C interface. Referring to Figure 2, Figure 2 is a functional structure diagram of a communication interface provided by an embodiment of the present application. The communication interface includes a receiving module 100 and a sending module 200, wherein the sending module 200 includes: a second transmission layer 210, a second data link layer 220 and a second serial-to-parallel conversion interface 230, the input end of the second data link layer 220 is connected to the output end of the second transmission layer 210, and the output end of the second data link layer 220 is connected to the input end of the second serial-to-parallel conversion interface 230, and in addition, the second data link layer 220 includes an scrambling unit 221, a framing unit 222 and an encoding unit 223, the input end of the framing unit 222 is connected to the output end of the scrambling unit 221, and the output end of the framing unit 222 is connected to the input end of the encoding unit 223; the receiving module 100 includes: the second transmission layer 210, the second data link layer 220 and the second serial-to-parallel conversion interface 230, the input end of the second data link layer 220 is connected to the output end of the second transmission layer 210, and the output end of the second data link layer 220 is connected to the input end of the second serial-to-parallel conversion interface 230, and the second data link layer 220 includes an scrambling unit 221, a framing unit 222 and an encoding unit 223. A transport layer 110, a first data link layer 120 and a first serial-to-parallel conversion interface 130, the input end of the first data link layer 120 is connected to the output end of the first serial-to-parallel conversion interface 130, the output end of the first data link layer 120 is connected to the input end of the first transport layer 110, in addition, the first data link layer 120 includes a de-framing unit 123, a descrambling unit 122, a checking unit 124 and an alignment unit 121, the input end of the de-framing unit 123 is connected to the output end of the first serial-to-parallel conversion interface 130, the output end of the de-framing unit 123 is respectively connected to the input end of the descrambling unit 122 and the checking unit 124, and the output end of the descrambling unit 122 is connected to the input end of the alignment unit 121. The output end of the second serial-to-parallel conversion interface 230 of the sending module 200 is connected to the input end of the first serial-to-parallel conversion interface 130 of the receiving module 100, so that the sending module 200 and the receiving module 100 are connected in communication.

In some embodiments, the second transport layer 210 of the sending module 200 is configured to map the channel data into unscrambled link data and transmit it to the second data link layer 220. In the second data link layer 220, the link data is sequentially transmitted through the scrambling unit 221, the framing unit 222 and the encoding unit 223. According to the JESD204C protocol, when the data is transmitted from the transport layer in the form of frames to the data link layer in the form of blocks, scrambling begins, and the scrambling unit 221 in the second data link layer 220 scrambles the link data, which can improve the fault tolerance and stability of the link in high-speed transmission applications. The scrambling unit 221 outputs the scrambled block data, and then the framing unit 222 frames the scrambled block data. The encoding unit 223 encodes the framed link data. In some embodiments, the encoding unit 223 is a 64B/66B encoding unit 223, and the 64B/66B encoding combines the data signal and the control signal through the synchronization header for transmission. The encoded data is transmitted to the second serial-to-parallel conversion interface 230, which converts the parallel data into serial data and sends the serial data to the first serial-to-parallel conversion interface 130 of the receiving module 100 at high speed. The switching interface 130 completes the reception of high-speed data, converts the serial data into parallel data, and transmits the parallel data to the first data link layer 120 of the receiving module 100. The parallel data passes through the deframing unit 123, the descrambling unit 122 and the alignment unit 121 of the first data link layer 120 in sequence. Correspondingly, the deframing unit 123 performs deframing processing on the data and outputs the deframing data to the descrambling unit 122. The descrambling unit 122 performs descrambling processing on the data, and then the alignment unit 121 performs alignment processing on the descrambled data and outputs the link data to the first transmission layer 110; the first transmission layer 110 is configured to map the link data output by the first data link layer 120 into channel data and transmit it to the channel of the time division duplex communication system.

In order to reduce the power consumption of the communication interface, in one embodiment of the present application, the traditional communication interface shown in FIG2 is improved so that it can realize the power saving function. Referring to FIG3, FIG3 is a functional structure diagram of a communication interface with a power saving function provided by an embodiment of the present application. The communication interface with a power saving function includes a receiving module 100 and a sending module 200, wherein the sending module 200 includes: a second transmission layer 210, a second data link layer 220 and a second serial-to-parallel conversion interface 230, and in addition, the second data link layer 220 includes a scrambling unit 221, a framing unit 222 and an encoding unit 223; the receiving module 100 includes: a first transmission layer 110, a first data link layer 120 and a first serial-to-parallel conversion interface 130, and in addition, the first data link layer 120 includes a deframing unit 123, a descrambling unit 122, a checking unit 124 and an alignment unit 121, and the connection relationship between the various units in the receiving module 100 and the sending module 200 is the same as the connection relationship shown in FIG2, and will not be repeated here. In addition, a first control unit 140 is newly added to the receiving module 100, and a second control unit 240 is newly added to the sending module 200, wherein the first control unit 140 includes a first data link layer control unit 141 and a first serial-to-parallel conversion interface control unit 142, and the second control unit 240 includes a second data link layer control unit 241 and a second serial-to-parallel conversion interface control unit 242.

In some embodiments, when receiving the power-saving state indication signal, the first data link layer control unit 141 is configured to perform link establishment state protection processing on the first data link layer 120 according to the power-saving state indication signal, and turn off the second clock gating of the descrambling unit 122 and the verification unit 124 of the first data link layer 120; the first serial-to-parallel conversion interface control unit 142 is configured to perform clock data recovery state locking processing on the first serial-to-parallel conversion interface 130 according to the power-saving state indication signal, and turn off the first clock gating related to data processing in the first serial-to-parallel conversion interface 130; the second data link layer control unit 241 is configured to turn off the fifth clock gating of the scrambling unit 221 and the encoding unit 223 in the second data link layer 220 according to the power-saving state indication signal; the second serial-to-parallel conversion interface control unit 242 is configured to turn off the fourth clock gating related to data processing in the second serial-to-parallel conversion interface 230. After the above processing, the communication interface enters the power-saving state, and certain protection control is performed on the state of the link.

It can be understood that, in the case of receiving the communication state indication signal, the first serial-to-parallel conversion interface control unit 142 is also configured to enable the first clock gating related to data processing in the first serial-to-parallel conversion interface 130 according to the communication state indication signal, and perform clock data recovery state tracking processing on the first serial-to-parallel conversion interface 130, and the first data link layer control unit 141 is also configured to enable processing on the first data link layer 120. After the above processing, the communication interface can quickly switch from the power saving state to the communication state.

It can be understood that the system structure, interface and application scenario described in this application are intended to more clearly illustrate the technical solution of the embodiments of this application, and do not constitute a limitation on the technical solution provided by the embodiments of this application. Those skilled in the art can understand that with the evolution of system structure and interface technology and the emergence of new application scenarios, the technical solution provided by the embodiments of this application is also applicable to similar technical problems.

Based on the above system structure, various embodiments of the power consumption optimization method of the present application are proposed below.

Referring to Figure 4, Figure 4 is a flow chart of a power consumption optimization method applied to a receiving module provided in an embodiment of the present application. The power consumption optimization method can be applied to the receiving module in the communication interface shown in Figure 3. The power consumption optimization method includes but is not limited to step S410 and step S420.

Step S410: receiving a power saving status indication signal;

Step S420: According to the power saving status indication signal, the first data link layer of the receiving module is protected in link state, the first serial-to-parallel conversion interface of the receiving module is locked in clock data recovery state, and the first clock gating related to data processing in the first serial-to-parallel conversion interface is turned off.

In an embodiment of the present application, by executing the power consumption optimization method of step S410 to step S420, the receiving module receives a power saving status indication signal; then, according to the power saving status indication signal, the first data link layer of the receiving module is subjected to link establishment status protection processing; finally, the first serial-to-parallel conversion interface of the receiving module is subjected to clock data recovery status locking processing, and the first clock gating related to data processing in the first serial-to-parallel conversion interface is turned off, which can effectively reduce the power consumption of the communication interface, achieve power saving, and facilitate rapid switching between the power saving state and the communication state.

It can be understood that the power saving status indication signal is sent by the timing control unit in the time division duplex communication system. At this time, the sending channel or the receiving channel is in the power saving state, and the communication interface, as a part of the sending channel and the receiving channel, will also enter the power saving state. By reducing the power consumption of the communication interface, power saving is achieved, thereby improving the energy efficiency ratio of the time division duplex communication system.

When the first serial-to-parallel conversion interface enters the power-saving state, the first data link layer will detect an error and make a link break judgment, causing the communication interface to enter the re-establishment process, which will take a long time to restore stability, and the re-establishment will cause the transmission time of the communication interface to change, so that more processes will have to restart. Based on this, in an embodiment of the present application, the first control unit newly added in the receiving module will perform link establishment state protection processing on the first data link layer, and lock the link in the state before entering the power-saving state, so that it can be switched back to the communication state from the power-saving state relatively quickly later.

Referring to Figure 5, Figure 5 is a flow chart of a method of step S420 in Figure 4. In step S420, according to the power saving status indication signal, the first data link layer of the receiving module is subjected to link state protection processing, including but not limited to step S510, step S520 and step S530.

Step S510: performing frame header locking processing on multiple frames of data to lock the positions of multiple frame headers;

Step S520: performing synchronization head locking processing on the block data to lock the synchronization head position;

Step S530: shielding the check result obtained through the cyclic redundancy check process.

In an embodiment of the present application, the first control unit of the receiving module performs frame header locking processing on multi-frame data, locks the position of multi-frame frame headers, and performs synchronization header locking processing on block data, locks the position of synchronization headers, and shields the verification result obtained by cyclic redundancy check processing. At this time, the data in the first data link layer is abnormal, and the abnormal data will not be output to the first transmission layer, but data 0 will be output to the first transmission layer. While saving power, it is conducive to realizing rapid switching between power saving state and communication state.

In one embodiment of the present application, the correct boundary of the block data is the basis for the correct parsing of the receiving module. The second serial-to-parallel conversion interface of the sending module is sent to the first serial-to-parallel conversion interface in a serial manner, and the receiving module needs to find the boundary of the block data according to the 64B/66B encoding rule. Once the boundary is lost, it is necessary to search again, which takes a long time. Therefore, the locking of the synchronization head position can be achieved through step S520, so as to facilitate the subsequent recovery of the link communication state, and effectively reduce the time required for the communication interface to recover from the power saving state to the communication state.

According to the JESD294C protocol, the 66-bit signal after 64B/66B encoding is composed of a 2-bit synchronization header and 64-bit data. This 66-bit data is called a block in the JESD294C protocol. As shown in Figure 6, Figure 6 is a schematic diagram of the structure of block data provided by an embodiment of the present application. The SH in the block data is the synchronization header, which is the boundary of the block data. S0 to S7 are the transmitted data, where SH is 2 bits, S0~S7 are 8 bits each, a total of 66 bits, and valid data is 64 bits. The synchronization header is a 2-bit unscrambled value located at the beginning of each block data, and the bit values of the valid synchronization header are inconsistent. Based on this, it is necessary to perform synchronization header locking processing on the block data to lock the synchronization header position.

As shown in FIG. 7 , FIG. 7 is a jump diagram of the synchronization head locking process of the block data provided by an embodiment of the present application. The synchronization head locking process is to add a function in the state machine of the 64B/66B boundary search: when the power saving is enabled, the synchronization head error count is not accumulated. When the state machine is reset or the synchronization head is not locked, it is necessary to find the synchronization head of the 64B/66B block data; then find the synchronization head initial state, and when continuous and inconsistent 2-bit data is found, the 2-bit data is used as the synchronization head of the first 64B/66B block data found; after the synchronization head is found for the first time, the state machine enters the search state; during the search process, a judgment is made every 66 bits. If the state machine detects 64 consecutive synchronization heads, it is confirmed that the synchronization head is found, and then the synchronization head is locked, and the power saving is enabled, and the synchronization error count is cleared; and during the search process, if the state machine detects a synchronization head error, the state machine will re-execute the step of finding the synchronization head initial state; when the synchronization head is locked, if the synchronization head error count exceeds the threshold value, the state machine will move back 1 bit and re-execute the step of finding the synchronization head initial state.

After the second serial-to-parallel conversion interface of the sending module enters the power-saving state, the boundary of the normal multi-frame data in the receiving module will be lost, which will result in the need to re-search the multi-frame boundary when exiting the power-saving state, which will consume a certain amount of time and affect the speed of restoring stability. Based on this, in one embodiment of the present application, it is necessary to protect the multi-frame header when entering the power-saving state to maintain its position before entering the power-saving state. That is, in the process of performing link state protection processing on the first data link layer of the receiving module, it is also necessary to perform frame header locking processing on the multi-frame data to lock the multi-frame header position.

As shown in Figure 8, Figure 8 is a schematic diagram of the structure of multi-frame data provided by an embodiment of the present application. Every 32 64B/66B blocks of data constitute a frame, and E frames constitute multi-frame data. E is a parameter preset by the receiving module and the sending module. A multi-frame data is also a mapping operation unit of the transport layer. The multi-frame header is used to indicate the boundary of the multi-frame, which is important for the delay alignment processing performed in the data link layer and the demapping processing performed in the transport layer. Once the multi-frame position is wrong, the subsequent data parsing processing in the transport layer will be wrong, resulting in incorrect data transmission.

In addition, referring to FIG. 9, FIG. 9 is a jump diagram of the frame header locking processing of multi-frame data provided by an embodiment of the present application. The frame header locking processing is to add a function in the multi-frame check state machine: when power saving is enabled, the multi-frame frame header error count is not accumulated. When the state machine is reset, the frame header of the multi-frame data needs to be found; that is, a multi-frame initial state search is performed, and when the multi-frame frame header is found for the first time, the state machine enters the multi-frame search state; during the multi-frame search process, if the state machine detects 4 multi-frame headers in succession, it is confirmed that the multi-frame header is found, jumps to the multi-frame locking state, realizes the multi-frame header locking, performs power saving enabling processing, and clears the multi-frame frame header error count; and during the multi-frame search process, when the state machine detects a multi-frame frame header error, the state machine will jump back to the multi-frame initial state search state; when the state machine performs multi-frame locking, if the multi-frame frame header error count exceeds the threshold, the state machine will jump back to the multi-frame initial state search state. Based on the above steps, the link state locking is implemented in the first data link layer, which is conducive to quickly restoring the communication state of the link.

In one embodiment of the present application, the verification result obtained through the cyclic redundancy check processing is shielded, that is, the verification result is not received, and no subsequent judgment is performed on it, and the output of the first data link layer is switched to data 0. This can prevent the first data link layer from protecting and error counting subsequent links after identifying an error, thereby affecting the normal operation and maintenance test function.

10 , which is a flowchart of another method of step S420 in FIG. 4 , wherein the clock data recovery state locking process is performed on the first serial-to-parallel conversion interface of the receiving module in step S420 , including but not limited to step S1010 .

Step S1010: Stop the phase check operation in the clock data recovery process of the first serial-to-parallel conversion interface.

In this step, the first control unit in the receiving module stops the phase check operation in the clock data recovery process of the first serial-to-parallel conversion interface.

It is understandable that the first serial-to-parallel conversion interface includes a clock data recovery circuit that can perform clock data recovery processing and can use the data that has been embedded with the clock to recover the clock and data synchronized with the clock. The clock data recovery circuit can input the input data into the phase-locked loop, recover the clock, and then sample the input data through the clock so that the clock is synchronized with the recovered data. The goal of the clock data recovery process is to find the best sampling time, which requires the data to have rich jumps. There is an indicator in the clock data recovery process called the maximum continuous 0 or 1 length tolerance (MaxRun Length or Consecutive Identical Digits) capability. If the data does not jump for a long time, the clock data recovery process cannot be accurately trained, and the sampling time of the clock data recovery circuit will drift, which may sample more 1 or 0 than the real data. And when the data is restored to jump again, wrong sampling may occur. For example, some clock data recovery circuits are implemented using a phase-locked loop. If the data stops jumping for a long time, the output frequency of the phase-locked loop will drift. The clock data recovery circuit includes a frequency detector, a phase detector, a phase-locked loop, a voltage-controlled oscillator, and a frequency divider, etc. The structure of the clock data recovery circuit and its internal connection relationship are not specifically illustrated and explained here. In order to quickly recover from the power saving state to the communication state, the first control unit stops the phase check operation in the clock data recovery process of the first serial-to-parallel conversion interface and locks the phase to the state before entering the power saving state. That is, the clock data recovery process no longer performs phase following. However, the working clock related to the delay in the first serial-to-parallel conversion interface needs to be maintained, and the phase-locked loop and frequency divider in the clock data recovery processing circuit do not save power.

Since the clock data recovery process is no longer followed, in order to make the phase relationship of the serial-to-parallel conversion interface at both ends of the transceiver module follow within a certain period of time, the serial-to-parallel conversion interface at both ends of the transceiver module must input the same reference clock. Referring to Figure 11, Figure 11 is a schematic diagram of the reference clock relationship of the communication interface provided by an embodiment of the present application. In some embodiments, chip A includes a second serial-to-parallel conversion interface and a phase-locked loop module, and chip B includes a first serial-to-parallel conversion interface and a phase-locked loop module. The output end of the phase-locked loop module of chip A is connected to the input end of the second serial-to-parallel conversion interface, and the output end of the second serial-to-parallel conversion interface is connected to the input end of the first serial-to-parallel conversion interface. The input end of the first serial-to-parallel conversion interface is also connected to the output end of the phase-locked loop module of chip A. The input ends of the phase-locked loop modules of chip A and chip B are both connected to the same clock chip. The clock chip outputs the same reference clock to the phase-locked loop modules of chip A and chip B through the same voltage-controlled oscillator. The same reference clock is output to the second serial-to-parallel conversion interface and the first serial-to-parallel conversion interface through the phase-locked loop modules of chip A and chip B respectively, so that the serial-to-parallel conversion interfaces at both ends of the transceiver module can achieve phase relationship following.

In one embodiment of the present application, the first data link layer includes a first data processing unit group, and after receiving the power saving state indication signal, it also includes: turning off the second clock gating of the first data processing unit group. In some embodiments, the first data processing unit group includes a descrambling unit and a verification unit. In some embodiments, in the receiving module, the first data processing unit group in the first data link layer refers to a descrambling unit and a verification unit, the descrambling unit uses the second clock gating to participate in the descrambling process, and the verification unit uses the second clock gating to participate in the verification process. Turning off the second clock gating can effectively reduce the power consumption of the communication interface, achieve power saving, and thus improve the energy efficiency of the system. The principle of turning off the clocks of multiple working units is that the control link clock is not turned off, and the clock that affects the link delay state is not turned off. Based on this, the working clock related to the control logic in the first data link layer of the receiving module is retained, including the deframing unit and the alignment unit.

In one embodiment of the present application, after receiving the power saving status indication signal, it also includes: gating off the third clock related to data processing in the random access memory in the first transmission layer of the receiving module, retaining the read and write address control logic clock of the first transmission layer of the receiving module, which can reduce the power consumption of the communication interface, achieve power saving, and thus improve the energy efficiency of the system.

Referring to FIG. 12 , FIG. 12 is a flow chart of a power consumption optimization method applied to a receiving module provided in another embodiment of the present application, wherein the power consumption optimization method includes but is not limited to step S1210 , step S1220 , and step S1230 .

Step S1210: receiving a communication status indication signal;

Step S1220: according to the communication status indication signal, enable the first clock gating related to data processing in the first serial-to-parallel conversion interface, and perform clock data recovery status tracking processing on the first serial-to-parallel conversion interface of the receiving module;

Step S1230: enabling the first data link layer of the receiving module.

In this step, the first control unit enables the first data link layer of the receiving module to restore the communication of the first data link layer. In some embodiments, the first control unit turns on the second clock gating of the first data processing unit group, turns on the phase check operation in the clock data recovery process of the first serial-to-parallel conversion interface, and performs phase following; then restores the block data synchronization process in the first data link layer according to the synchronization header position; restores the multi-frame synchronization process according to the multi-frame header position; receives the check result obtained by the cyclic redundancy check process, enables the redundant cyclic check judgment, and turns on the output data of the first data link layer, switching to normal data output.

In an embodiment of the present application, by executing the power consumption optimization method of steps S1210 to S1230, the receiving module receives a communication status indication signal, and then, according to the communication status indication signal, turns on the first clock gating related to data processing in the first serial-to-parallel conversion interface, performs clock and data recovery state tracking processing on the first serial-to-parallel conversion interface of the receiving module, and releases the clock and data recovery state lock of the first serial-to-parallel conversion interface, and performs clock and data recovery state tracking, that is, CDR state tracking; finally, the first data link layer of the receiving module is enabled so that the receiving module can quickly switch from the power saving state to the communication state.

It can be understood that the communication status indication signal is sent by the timing control unit in the time division duplex communication system. At this time, the sending channel or the receiving channel is in the communication state. The communication interface is part of the sending channel and the receiving channel. The sending module of the communication interface quickly switches to the communication state, which can ensure the normal communication of the time division duplex communication system.

Referring to Figure 13, Figure 13 is a flow chart of a power consumption optimization method applied to a sending module provided by an embodiment of the present application. The power consumption optimization method can be applied to the sending module in the communication interface shown in Figure 3. The power consumption optimization method includes but is not limited to step S1310 and step S1320.

Step S1310: receiving a power saving status indication signal;

Step S1320: according to the power-saving state indication signal, turn off the fourth clock gating related to data processing in the second serial-to-parallel conversion interface of the sending module.

In an embodiment of the present application, by executing the power consumption optimization method of steps S1310 to S1320, when the receiving module receives the power saving status indication signal and enters the power saving status, the sending module also receives the power saving status indication signal, and then the sending module turns off the fourth clock gating related to data processing in the second serial-to-parallel conversion interface of the sending module according to the power saving status indication signal, and enters the power saving state.

In one embodiment of the present application, the second data link layer of the sending module includes a second data processing unit group, and after receiving the power saving state indication signal, it also includes: turning off the fifth clock gating of the second data processing unit group. In some embodiments, the second data processing unit group includes a scrambling unit and an encoding unit. In some embodiments, in the sending module, the second data processing unit group in the second data link layer refers to a scrambling unit and an encoding unit, and the fifth clock gating is used in the scrambling unit for scrambling processing, and the fifth clock gating is used in the encoding unit for encoding processing. Turning off the fifth clock gating can effectively reduce the power consumption of the communication interface, achieve power saving, and thus improve the energy efficiency ratio of the system. The principle of turning off the clocks of multiple working units is that the control link clock is not turned off, and the clock that affects the link delay state is not turned off. Based on this, the working clock related to the control logic in the second data link layer of the sending module is retained, such as the framing unit.

In one embodiment of the present application, after receiving the power saving status indication signal, it also includes: turning off the sixth clock gating related to data processing in the random access memory in the second transmission layer of the sending module, retaining the read and write address control logic clock of the second transmission layer of the sending module, which can reduce the power consumption of the communication interface, achieve power saving, and thus improve the energy efficiency of the system.

Referring to FIG. 14 , FIG. 14 is a flow chart of a power consumption optimization method applied to a sending module provided in another embodiment of the present application. The power consumption optimization method includes but is not limited to step S1410 and step S1420.

Step S1410: receiving a communication status indication signal;

Step S1420: according to the communication status indication signal, enable the fourth clock gating related to data processing in the second serial-to-parallel conversion interface, and enable the fifth clock gating of the second data processing unit group.

In an embodiment of the present application, by executing the power consumption optimization method of steps S1410 to S1420, when the receiving module receives the communication status indication signal and quickly recovers from the power saving state to the communication state, the sending module also receives the communication status indication signal. Then, the second control unit of the sending module turns on the fourth clock gating related to data processing in the second serial-to-parallel conversion interface according to the communication status indication signal, and turns on the fifth clock gating of the second data processing unit group, so that the sending module can quickly switch from the power saving state to the communication state.

It can be understood that the communication status indication signal is sent by the timing control unit in the time division duplex communication system. At this time, the sending channel or the receiving channel is in the communication state. The communication interface is part of the sending channel and the receiving channel. The sending module of the communication interface quickly switches to the communication state, which can ensure the normal communication of the time division duplex communication system.

Through the above method, the serial-to-parallel conversion interface of the modules on both sides of the entire communication interface is in a power-saving state and the link is not interrupted. Such a power-saving method can quickly recover from the power-saving state to the normal communication state without rebuilding the link. When exiting the power-saving process, the sending module first exits the power-saving state, and then the receiving module exits the power-saving state from the physical layer (including: serial-to-parallel conversion interface) and the data link layer in turn. The sending module and the receiving module have a homologous reference clock, so that the first data link layer of the receiving module can keep the locked state and the restored state consistent when the sending module turns off the output, ensuring the synchronization of the sending module and the receiving module clock; in addition, the power-saving parts in the receiving module and the sending module can not affect the delay changes of the entire transmission process in the system. According to the scheme of the embodiment of the present application, the power consumption of the communication interface can be effectively reduced, power saving can be achieved, and fast switching between the power-saving state and the communication state can be achieved, thereby improving the energy efficiency ratio of the system.

In addition, it is understandable that in some cases, the chip including the first serial-to-parallel conversion interface and the chip including the second serial-to-parallel conversion interface cannot support clock gating closure, and the communication interface in the time division duplex communication system does not support clock gating closure. In such a case, the above method of reducing the power consumption in the communication interface by closing the data link layer at both ends of the transmitter and receiver and part of the clock gating of the serial-to-parallel conversion interface will be difficult to implement. In these cases, in order to ensure that the first serial-to-parallel conversion interface of the receiving module can correctly receive data, the second serial-to-parallel conversion interface of the sending module needs to avoid outputting 0 or 1 for a long time, so it is necessary to perform scrambling processing through the scrambling unit in the first data link layer to convert the constant into changing data, and the data flip rate after scrambling reaches about 35% to 40%. Too high a data flip rate will also increase the power consumption in the communication interface. Therefore, reducing the data flip rate can also reduce the power consumption in the communication interface to a certain extent and achieve power saving.

In one example, after receiving a power-saving status indication signal, on the one hand, when the sending module does not support clock gating shutdown, the second data link layer is controlled to transmit a custom sequence with a low flip rate and turn off the scrambled data output according to the power-saving status indication signal; at the same time, on the other hand, when the receiving module does not support clock gating shutdown, the first data link layer is controlled to output data 0 according to the power-saving status indication signal.

Referring to Figure 15, Figure 15 is a schematic diagram of the power-saving working state in the communication interface provided by an embodiment of the present application when the communication interface does not support clock gating shutdown. In the sending module, the second data link layer is controlled to transmit a custom sequence with a low flip rate to reduce the power consumption in the communication interface and achieve power saving. Since the custom sequence with a low flip rate is useless data in the receiving module, there is no need to ensure the correctness of the data received by the serial-to-parallel conversion interface. Therefore, the custom sequence does not need to pass through the scrambling unit in the first data link layer. In addition to having a low flip rate, the custom sequence also needs to ensure that the clock data recovery of the first serial-to-parallel conversion interface of the receiving module can be locked and that no bit errors occur near the data header. The custom sequence is processed by the framing unit and the encoding unit in the second data link layer in turn, output to the second serial-to-parallel conversion interface, and then received by the first serial-to-parallel conversion interface, and then enters the first data link layer, and passes through the first data link layer in turn. The processing of the deframing unit, descrambling unit and alignment unit of the first data link layer will cause the receiving module to make an erroneous judgment, affecting the operation of the time division duplex communication system. Therefore, in the power saving state, it is necessary to control the first data link layer to output data 0. In the power saving state, transmitting a custom sequence with a low flip rate in the receiving module and the sending module of the communication interface can reduce the power consumption in the communication interface, ensure that the functional modules in the first data link layer and the second data link layer are in a normal working state, and can quickly restore the normal communication state without restarting the functional modules in the first data link layer and the second data link layer.

Referring to FIG. 16, FIG. 16 is a schematic diagram of the structure of a communication device provided in an embodiment of the present application. The communication device 1600 of the embodiment of the present application includes one or more processors 1610 and a memory 1620. FIG. 16 takes one processor 1610 and one memory 1620 as an example. The processor 1610 and the memory 1620 may be connected via a bus or other means, and FIG. 16 takes the connection via a bus as an example.

The memory 1620, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer executable programs. In addition, the memory 1620 may include a high-speed random access memory, and may also include a non-transitory memory, such as at least one disk storage device, a flash memory device, or other non-transitory solid-state storage device. In some embodiments, the memory 1620 includes a memory 1620 remotely arranged relative to the processor 1610, and these remote memories 1620 can be connected to the communication device 1600 respectively via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

Those skilled in the art will appreciate that the device structure shown in FIG. 16 does not constitute a limitation on the communication device 1600 , and may include more or fewer components than shown in the figure, or a combination of certain components, or a different arrangement of components.

The non-transitory software programs and instructions required to implement the power consumption optimization method applied to the communication device 1600 in the above-mentioned embodiment are stored in the memory 1620. When executed by the processor 1610, the power consumption optimization method applied to the communication device 1600 in the above-mentioned embodiment is executed, for example, the method steps in Figures 4, 5, 10, 12, 13 and 14 described above are executed.

The device embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separated, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, an embodiment of the present application also provides a computer-readable storage medium, which stores computer-executable instructions, which are executed by one or more processors, for example, or executed by a processor 1610 in Figure 16, so that the one or more processors 1610 can execute the control method in the above-mentioned method embodiment, for example, execute the method steps in Figures 4, 5, 10, 12, 13 and 14 described above.

The embodiment of the present application includes: the receiving module of the communication device receives the power saving state indication signal; according to the power saving state indication signal, the first data link layer of the receiving module is subjected to link state protection processing; the first serial-to-parallel conversion interface of the receiving module is subjected to clock data recovery state locking processing, and the first clock gating related to data processing in the first serial-to-parallel conversion interface is turned off. According to the scheme of the embodiment of the present application, the receiving module of the communication device receives the power saving state indication signal; then according to the power saving state indication signal, the first data link layer of the receiving module is subjected to link state protection processing; finally, the first serial-to-parallel conversion interface of the receiving module is subjected to clock data recovery state locking processing, and the first clock gating related to data processing in the first serial-to-parallel conversion interface is turned off. That is to say, the scheme of the embodiment of the present application can effectively reduce the power consumption of the communication interface, realize power saving, and facilitate fast switching between power saving state and communication state by turning off the first clock gating in the first serial-to-parallel conversion interface of the sending module and performing link state protection processing in the first data link layer.

It will be appreciated by those skilled in the art that all or some of the steps and systems in the method disclosed above may be implemented The term "computer storage medium" refers to a physical component or a combination of physical components. The physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor or a microprocessor, or may be implemented as hardware, or may be implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or a non-transitory medium) and a communication medium (or a temporary medium). As known to those of ordinary skill in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cassette, magnetic tape, disk storage or other magnetic storage device, or any other medium that can be used to store desired information and can be accessed by a computer. In addition, it is known to those of ordinary skill in the art that communication media generally contain computer-readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transmission mechanism, and may include any information delivery medium.

Claims (16)

1. A power consumption optimization method, applied to a receiving module, comprising:

   receiving a power saving status indication signal;

   According to the power-saving status indication signal, the first data link layer of the receiving module is subjected to link establishment status protection processing, the first serial-to-parallel conversion interface of the receiving module is subjected to clock data recovery status locking processing, and the first clock gating related to data processing in the first serial-to-parallel conversion interface is turned off.
2. The power consumption optimization method according to claim 1, wherein the performing link establishment state protection processing on the first data link layer of the receiving module comprises:

   Perform frame header locking processing on multiple frames of data to lock the positions of multiple frame headers;

   Perform synchronization head locking processing on block data to lock the synchronization head position;

   Shield the check result obtained after the cyclic redundancy check processing.
3. The power consumption optimization method according to claim 1, wherein the performing clock data recovery state locking processing on the first serial-to-parallel conversion interface of the receiving module comprises:

   The phase check operation in the clock data recovery process of the first serial-to-parallel conversion interface is stopped.
4. The power consumption optimization method according to claim 1, wherein the first data link layer includes a first data processing unit group, and after receiving the power saving state indication signal, further comprising:

   The second clock of the first data processing unit group is gated off.
5. The power consumption optimization method according to claim 1, wherein the first data link layer includes a first data processing unit group, and the first data processing unit group includes a descrambling unit and a verification unit.
6. The power consumption optimization method according to claim 1, wherein after receiving the power saving state indication signal, the method further comprises:

   A third clock gate related to data processing in a random access memory in a first transmission layer of the receiving module is turned off.
7. The power consumption optimization method according to claim 1, further comprising:

   receiving a communication status indication signal;

   According to the communication status indication signal, the first clock gating related to data processing in the first serial-to-parallel conversion interface is enabled, and clock data recovery status tracking processing is performed on the first serial-to-parallel conversion interface of the receiving module;

   An enabling process is performed on the first data link layer of the receiving module.
8. The power consumption optimization method according to claim 1, wherein after receiving the power saving state indication signal, the method further comprises:

   In a case where the receiving module does not support clock gating shutdown, the first data link layer is controlled to output data 0 according to the power saving state indication signal.
9. A power consumption optimization method, applied to a sending module, comprising:

   receiving a power saving status indication signal;

   According to the power-saving state indication signal, a fourth clock gating related to data processing in the second serial-to-parallel conversion interface of the sending module is turned off.
10. The power consumption optimization method according to claim 9, wherein the second data link layer of the sending module includes a The second data processing unit group, after receiving the power saving state indication signal, further includes:

    The fifth clock gating of the second data processing unit group is turned off.
11. The power consumption optimization method according to claim 9, wherein the second data link layer of the sending module includes a second data processing unit group, and the second data processing unit group includes a scrambling unit and an encoding unit.
12. The power consumption optimization method according to claim 9, wherein after receiving the power saving state indication signal, the method further comprises:

    The sixth clock gating related to data processing in the random access memory in the second transmission layer of the sending module is turned off.
13. The power consumption optimization method according to claim 10, further comprising:

    receiving a communication status indication signal;

    According to the communication status indication signal, the fourth clock gating related to data processing in the second serial-to-parallel conversion interface is enabled, and the fifth clock gating of the second data processing unit group is enabled.
14. The power consumption optimization method according to claim 9, wherein after receiving the power saving state indication signal, the method further comprises:

    In the case that the sending module does not support clock gating shutdown, the second data link layer is controlled to transmit a custom sequence with a low flip rate according to the power saving state indication signal, and the scrambled data output is turned off.
15. A communication device, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the power consumption optimization method according to any one of claims 1 to 8 or the power consumption optimization method according to any one of claims 9 to 14 is implemented.
16. A computer-readable storage medium storing computer-executable instructions, wherein the computer-executable instructions are used to execute the power consumption optimization method described in any one of claims 1 to 8, or the power consumption optimization method described in any one of claims 9 to 14.