CN111371524B - Time synchronization precision detection system based on camera link protocol - Google Patents
Time synchronization precision detection system based on camera link protocol Download PDFInfo
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- CN111371524B CN111371524B CN202010171063.9A CN202010171063A CN111371524B CN 111371524 B CN111371524 B CN 111371524B CN 202010171063 A CN202010171063 A CN 202010171063A CN 111371524 B CN111371524 B CN 111371524B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0602—Systems characterised by the synchronising information used
- H04J3/0605—Special codes used as synchronising signal
- H04J3/0608—Detectors therefor, e.g. correlators, state machines
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0658—Clock or time synchronisation among packet nodes
- H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
Abstract
The system comprises a Schmitt interface circuit, a second pulse interface circuit, a 422 interface circuit, a camera alink interface circuit and a timestamp generation module, wherein the Schmitt interface circuit, the second pulse interface circuit, the 422 interface circuit, the camera alink interface circuit and the timestamp generation module are included; in the shooting state, n groups of row numbers and timestamp multiplexers receive the row numbers, second counting values and microsecond counting values output by corresponding n groups of row numbers and timestamp latches, in the non-shooting state, the row numbers and timestamps output by all paths are 0, an analog row synchronization generator in the module generates a row synchronization signal of a camera link at a typical row frequency, and a camera link output starting counter is set through a timestamp information output starting switcher of each row, so that the output operation of the timestamp is started. The multi-channel timestamp information can be acquired simultaneously, and the method can also be applied to application occasions with short line periods.
Description
Technical Field
The invention relates to a time synchronization precision detection system based on a camera link protocol, in particular to a time synchronization precision detection system based on a multi-channel short line period of the camera link protocol.
Background
The 422 interface is adopted to transmit the multi-channel timestamp information, and the information is limited by the baud rate, cannot be used for multi-channel transmission and cannot be used in the application occasions with short line periods; the traditional camera link protocol is adopted, collection is started after data output is started, and first-row timestamp information of starting shooting cannot be collected; and if the upper computer software is used for acquisition without starting to shoot, the upper computer is halted due to no data.
Disclosure of Invention
The invention aims to solve the problem that the prior camera link protocol cannot acquire the first row timestamp information of the beginning of shooting in the data acquisition process; and the problem that the upper computer crashes due to no data can occur when the upper computer software is used for collecting without starting shooting, and the time synchronization precision detection system based on the camera link protocol is provided.
The time synchronization precision detection system based on the camera link protocol comprises a Schmidt interface circuit, a pulse per second interface circuit, a 422 interface circuit, a camera link interface circuit and a timestamp generation module;
the timestamp generation module comprises a line synchronization detection module, an analog line synchronization generator, a timestamp information output starting switcher for each line, a camera link output starting counter, an OR gate circuit, n groups of line number counters, n groups of microsecond counters, n groups of second counters, n groups of line number and timestamp latches, n groups of line number and timestamp multiplexers, a 422 analysis module and a multiplexer;
the 422 serial port signal of external input, after carrying on the level conversion through 422 interface circuit, convey to 422 and analyze the module; the 422 analysis module receives an input second value, a microsecond value and a camera shooting state signal;
the externally input second pulse is subjected to level conversion through a second pulse interface circuit, and then each group of second counters and each group of microsecond counters are controlled; after detecting the falling edge of the pulse per second, each group of microsecond counters are cleared, or are cleared after being incremented to 1999999 microseconds; when receiving the valid microsecond value of the satellite platform input by the external 422 serial port, replacing the current microsecond count value with the microsecond value of the satellite platform;
each group of second counters adds 1 to the count value after detecting the falling edge of the second pulse, and after receiving the GNSS second value corresponding to the second pulse, the GNSS second value is adopted to replace the current second count value; when an effective satellite platform second value input by an external 422 serial port is received, replacing the current second counting value by the satellite platform second value; when the microsecond counting value is 1999999, the second pulse is invalid, and the current second counting value is added by 2;
the externally input global reset signal respectively carries out zero clearing reset on the line number counter, the microsecond counter and the second counter after passing through the Schmidt interface circuit;
each path of line synchronizing signal output by external input passes through a Schmidt interface circuit and then is subjected to rising edge extraction by a corresponding rising edge generator in a line synchronizing detection module, when each group of rising edge generators outputs a high-level pulse signal, each group of line number counters is added with 1, and the current count values of each group of line number counters, each group of microsecond counters and each group of second counters are latched into corresponding line number and timestamp latches;
meanwhile, each group of rising edge generators outputs high-level pulse signals to be subjected to OR operation through an OR gate circuit, and then each row of timestamp information output starting switcher is used for setting a camera link output starting counter, so that the output operation of starting a timestamp is realized;
after the line number and the timestamp information are latched, the line number, the second counting value and the microsecond counting value output by the n groups of line numbers and the timestamp latches are sent to corresponding n groups of line numbers and timestamp multiplexers, and then are sequentially output through the camera link interface circuit after passing through the multiplexers.
The invention has the beneficial effects that:
1. the invention adopts a camera link interface, can simultaneously transmit multi-channel timestamp information and can meet the application of short line period.
2. In the non-shooting stage, the line number and the timestamp are set to be 0, and meanwhile, a camera alink interface starting signal in a typical line period is generated, so that the condition that data can be acquired by a camera alink acquisition card in the non-shooting stage can be ensured, and the upper computer software cannot be blocked.
Drawings
Fig. 1 is a schematic block diagram of a time synchronization precision detection system based on a camera link protocol according to the present invention.
Detailed Description
First embodiment, the present embodiment is described with reference to fig. 1, and the time synchronization precision detection system based on the camera link protocol includes a schmitt interface circuit, a pulse-per-second interface circuit, a 422 interface circuit, a camera link interface circuit, and a timestamp generation module. The time stamp generating module comprises an analog line synchronization generator, rising edge generators 1-n, a time stamp information output starting switcher for each line, a camera link output starting counter, an OR gate circuit, a line number counter 1-n, a microsecond counter 1-n, a second counter 1-n, a line number and time stamp multiplexer 1-n and a time stamp multiplexer n, a line number and time stamp latch 1-n and a time stamp latch n, a 422 analyzing module and a multiplexer. The 422 serial port signal of external input carries on the level conversion through 422 interface circuit, send into the time stamp and produce the module, receive second value, microsecond value and shooting status signal input. The externally input pulse per second is subjected to level conversion by a pulse per second interface circuit, and then is sent to a timestamp generation module to control a second counter and a microsecond counter. The global reset signal input from outside and the line synchronizing signal output from each channel are sent to the time stamp generating module after passing through the Schmidt interface circuit, and are respectively subjected to global reset and time stamp information latching, and finally are output through the camera link interface circuit.
In this embodiment, the externally input pulse per second is subjected to level conversion by the pulse per second interface circuit, and then each set of second counters and each set of microsecond counters are controlled; after detecting the falling edge of the pulse per second, each group of microsecond counters are cleared, or are cleared after being incremented to 1999999 microseconds; when receiving the valid microsecond value of the satellite platform input by the external 422 serial port, replacing the current microsecond count value with the microsecond value of the satellite platform;
each group of second counters adds 1 to the count value after detecting the falling edge of the second pulse, and after receiving the GNSS second value corresponding to the second pulse, the GNSS second value is adopted to replace the current second count value; when an effective satellite platform second value input by an external 422 serial port is received, replacing the current second counting value by the satellite platform second value; when the microsecond counting value is 1999999, the second pulse is invalid, and the current second counting value is added by 2; the GNSS second values and the platform second values are distinguished by a frame identification in the 422 communication protocol.
The externally input global reset signal respectively carries out zero clearing reset on the line number counter, the microsecond counter and the second counter after passing through the Schmidt interface circuit;
each path of line synchronizing signal output by external input passes through a Schmidt interface circuit and then is subjected to rising edge extraction by a corresponding rising edge generator in a line synchronizing detection module, when each group of rising edge generators outputs a high-level pulse signal, each group of line number counters is added with 1, and the current count values of each group of line number counters, each group of microsecond counters and each group of second counters are latched into corresponding line number and timestamp latches;
meanwhile, each group of rising edge generators outputs high-level pulse signals to be subjected to OR operation through an OR gate circuit, and then each row of timestamp information output starting switcher is used for setting a camera link output starting counter, so that the output operation of starting a timestamp is realized; after the latch operation of the row number and the timestamp information, the row number, the second counting value and the microsecond counting value output by the n groups of row number and timestamp latches are sent to the corresponding n groups of row number and timestamp multiplexers, and the timestamp information of each channel is output in sequence.
Namely: and the multiplexer is controlled by a starting counter output through the camera alink, and the line number, the second counting value and the microsecond counting value which are latched by the first group of line numbers and the time stamp multiplexer are sequentially output to the line number, the second counting value and the microsecond counting value which are latched by the last group of line numbers and the time stamp multiplexer through a camera alink interface circuit according to the ascending sequence of the n groups of line numbers and the counting value of the time stamp multiplexer.
In the embodiment, in the shooting state, the n groups of row numbers and the timestamp multiplexers receive the row numbers, the second counting values and the microsecond counting values output by the corresponding n groups of row numbers and the timestamp latches, in the non-shooting state, no externally input row synchronization signals output by each path (the row numbers and the timestamps output by each path are 0) exist, the analog row synchronization generator in the module generates a row synchronization signal of a camera link under a typical row frequency, and the row synchronization signal is sent to each row of timestamp information output starting switcher to set the camera link output starting counter, so that the output operation of starting the timestamp is realized; the row number, microsecond count value and second count value of all zero values are sent to n groups of row numbers and time stamp multiplexers, then pass through the multiplexers, and finally are output through a camera link interface circuit.
In the present embodimentClock frequency f of the timestamp generation moduleclkBaud rate f for 422 communication422clkM, and is greater than or equal to the lowest frequency f of the operation of the camera link interface chipcameralink_low(ii) a While ensuring at a minimum line cycle time tperiod_minThe internal energy can finish outputting the n paths of time stamp information.
In the formula, nline_numNumber of clocks occupied for line number transmission, nsecondNumber of clocks occupied for value of seconds transmission, nmicorseondThe number of clocks occupied for the transmission of microsecond values, m being the clock frequency f of the timestamp generation moduleclkWith respect to baud rate f of 422 communication422clkMultiples of (a).
The setting operation of the cameralink output start counter described in this embodiment lags behind the latching operation of the time stamp by at least one clock cycle, i.e., 1/fclk。
In the present embodiment, the switching of the imaging state is controlled by the imaging state signal output by the 422 analysis module; when receiving a shooting start command, the shooting state signal is an effective high level; when the power-on reset or the camera shooting end command is received, the camera shooting state signal is in an invalid low level.
In this embodiment, the schmitt interface circuit mainly uses a 74AC14 chip; the pulse per second interface circuit and the 422 interface circuit adopt DS26LV32 chips suitable for a daisy chain structure; the camera link interface circuit adopts a DS90CR287 chip; the time stamp generation module adopts K7 series FPGA of the company Fudan Miao.
Claims (5)
1. The time synchronization precision detection system based on the camera link protocol comprises a Schmidt interface circuit, a pulse per second interface circuit, a 422 interface circuit, a camera link interface circuit and a timestamp generation module; the method is characterized in that:
the timestamp generation module comprises a line synchronization detection module, an analog line synchronization generator, a timestamp information output starting switcher for each line, a camera link output starting counter, an OR gate circuit, n groups of line number counters, n groups of microsecond counters, n groups of second counters, n groups of line number and timestamp latches, n groups of line number and timestamp multiplexers, a 422 analysis module and a multiplexer;
the 422 serial port signal of external input, after carrying on the level conversion through 422 interface circuit, convey to 422 and analyze the module; the 422 analysis module receives an input second value, a microsecond value and a camera shooting state signal;
the externally input second pulse is subjected to level conversion through a second pulse interface circuit, and then each group of second counters and each group of microsecond counters are controlled; after detecting the falling edge of the pulse per second, each group of microsecond counters are cleared, or are cleared after being incremented to 1999999 microseconds; when receiving the valid microsecond value of the satellite platform input by the external 422 serial port, replacing the current microsecond count value with the microsecond value of the satellite platform;
each group of second counters adds 1 to the count value after detecting the falling edge of the second pulse, and after receiving the GNSS second value corresponding to the second pulse, the GNSS second value is adopted to replace the current second count value; when an effective satellite platform second value input by an external 422 serial port is received, replacing the current second counting value by the satellite platform second value; when the microsecond counting value is 1999999, the second pulse is invalid, and the current second counting value is added by 2;
the externally input global reset signal respectively carries out zero clearing reset on the line number counter, the microsecond counter and the second counter after passing through the Schmidt interface circuit;
each path of line synchronizing signal output by external input passes through a Schmidt interface circuit and then is subjected to rising edge extraction by a corresponding rising edge generator in a line synchronizing detection module, when each group of rising edge generators outputs a high-level pulse signal, each group of line number counters is added with 1, and the current count values of each group of line number counters, each group of microsecond counters and each group of second counters are latched into corresponding line number and timestamp latches;
meanwhile, each group of rising edge generators outputs high-level pulse signals to be subjected to OR operation through an OR gate circuit, and then each row of timestamp information output starting switcher is used for setting a camera link output starting counter, so that the output operation of starting a timestamp is realized;
after the line number and the timestamp information are latched, the line numbers, the second counting values and the microsecond counting values output by the n groups of line numbers and timestamp latches are sent to corresponding n groups of line numbers and timestamp multiplexers, and then are sequentially output through a camera link interface circuit after passing through the multiplexers;
in the shooting state, n groups of row numbers and timestamp multiplexers receive row numbers, second counting values and microsecond counting values output by corresponding n groups of row numbers and timestamp latches, in the non-shooting state, the row numbers and timestamps output by each path are 0, the analog row synchronization generator generates a row synchronization signal of camera alink under row frequency, a time stamp information output starting switcher outputs and starts a setting of a camera alink output starting counter, and the output operation of starting a timestamp is realized; the row number, microsecond count value and second count value of all zero values are sent to n groups of row numbers and time stamp multiplexers, then pass through the multiplexers, and finally are output through a camera link interface circuit.
2. The system according to claim 1, wherein said system comprises:
the camera alink output starting counter controls the multiplexer, and outputs the row number, the second counting value and the microsecond counting value latched by the first group of row numbers and the time stamp multiplexer to the row number, the second counting value and the microsecond counting value latched by the last group of row numbers and the time stamp multiplexer through the camera alink interface circuit in sequence according to the ascending sequence of the n groups of row numbers and the counting value of the time stamp multiplexer.
3. The system according to claim 1, wherein said system comprises: clock frequency f of the timestamp generation moduleclkBaud rate f for 422 communication422clkIs greater than or equal to the lowest frequency f of the operation of the camera link interface chipcameralink_low(ii) a While ensuring at a minimum line cycle time tperiod_minInternal energyFinishing outputting the n paths of timestamp information; is formulated as:
in the formula, nline_numNumber of clocks occupied for line number transmission, nsecondNumber of clocks occupied for value of seconds transmission, nmicorseondThe number of clocks occupied for the microsecond value transfer.
4. The system according to claim 1, wherein said system comprises: the cameralink output starts a set operation of the counter at least one clock cycle after a latching operation of the timestamp, that is: 1/fclk。
5. The system according to claim 1, wherein said system comprises: the switching of the image pickup state is controlled by an image pickup state signal output by the 422 analysis module; when receiving a shooting start command, the shooting state signal is an effective high level; when the power-on reset or the camera shooting end command is received, the camera shooting state signal is in an invalid low level.
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