CN109818702A - A kind of IEEE802.1AS clock synchronizing function realizes system and implementation method - Google Patents
A kind of IEEE802.1AS clock synchronizing function realizes system and implementation method Download PDFInfo
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Abstract
The invention discloses a kind of IEEE802.1AS clock synchronizing functions to realize system and implementation method.It include: sending and receiving data memory module, MAC sends control module, and MAC receives control module, CRC check module, packet parsing module, timestamp generation module, First Input First Output timestamp fifo module, RTC clock module, CPU module and cpu i/f module.The method of the present invention step are as follows: initial configuration clock information identifies that message information, hardware generate timestamp, and timestamp saves, and calculates time deviation, clock correction according to timestamp.The method that the present invention uses Hardware/Software Collaborative Design, utilizes soft nuclear design CPU in fpga, and message sends and receives, the generation and preservation of timestamp, local clock are completed by hardware, the parsing of message, the reading of timestamp, the calculating of clock jitter have soft nucleus CPU to complete.
Description
Technical field
The present invention relates to data communication field more particularly to a kind of IEEE802.1AS clock synchronization system and its realize same
The method of step.
Background technique
With the fast development of automotive electronics, advanced DAS (Driver Assistant System) and unmanned technology based on high resolution audio and video
It gradually rises, a large amount of audio-videos and real time data need to transmit by Ethernet.Due to it is existing between web-transporting device when
The shake of clock and data transmission path delay have seriously affected the transmission quality of audio-video and real time data, therefore as data pass
The increase in demand of defeated bandwidth and real-time, to the time synchronization between web-transporting device, more stringent requirements are proposed.Time is same
Step technology in the time calibration of each transmission node to a lesser range by that will reduce clock jitter and transmission delay and bring
Influence to improve the transmission quality of network be the key technology for realizing high resolution audio and video and real-time data network transmission.Mesh
Before, the software and hardware that external many organizations and individuals are being dedicated to IEEE802.1AS agreement is realized and time synchronization performance
It improves.Research of the studies in China for time synchronization protocol is concentrated mainly on the research and realization of IEEE1588v2 agreement.It is domestic
The research of IEEE802.1AS is started it is later, it is seldom still in the relevant document of theoretical research stage at present, Huawei and in it is emerging
Equal companies are just in the realization of research agreement and testing scheme.
Summary of the invention
In view of this, the purpose of the present invention is to provide a kind of IEEE802.1AS clock synchronizing function realize system and
Implementation method.
To achieve the goals above, the present invention realizes IEEE802.1AS time synchronization on programmable logic chip FPGA
System, by way of software and hardware combining, hardware is responsible for specific work, and software is responsible for scheduling.Both it is slow software speed had been compensated for
The problem of, and reduce the complexity of design.Hardware directly beats timestamp, improves the accuracy of system.By delay measurements and
Two steps of time synchronization combine, and have directlyed adopt single step synchronous method, and master-salve clock respectively acquires two timestamps, from
Four timestamp informations that clock is acquired according to master-salve clock calculate master-salve clock deviation, according to master-salve clock deviation to from
Clock is calibrated, and the clock for completing the network equipment in communications network system is synchronous.
The technical scheme is that a kind of IEEE802.1AS clock synchronizing function realizes system, it is characterized in that including receiving
Data memory module is sent out, MAC sends control module, and MAC receives control module, CRC check module, packet parsing module, time
Stab generation module, First Input First Output timestamp fifo module, RTC clock module, CPU module and cpu i/f module；
The output end for sending data memory module is connected with the MAC input terminal for sending control module；MAC receives control module
Output end with receive data memory module input terminal be connected；MAC receives control module and is connected with external input terminals；MAC hair
Control module is sent to be connected with external output end；CRC check module sends control module with MAC and MAC receives control module and is connected；
The input terminal that MAC receives control module is connected with the input terminal for receiving packet parsing module；The output end of MAC transmission control module
It is connected with the input terminal for sending packet parsing module；The input terminal phase of the output end of packet parsing module and timestamp generation module
Even；The output end of timestamp generation module is connected with the input terminal of First Input First Output timestamp fifo module；RTC clock module
Output end be connected with the input terminal of timestamp generation module；CPU module is connected by cpu i/f module with bottom hardware；
Wherein, sending and receiving data memory module is the dual port RAM of memory capacity 2K byte, and sending and receiving respectively has one, point
The untreated data for not storing data to be sent and receiving；
MAC sends control module and reads the data sent in RAM, is packaged into UDP message, is sent to by RGMII format
External phy chip；
MAC receives control module, and the ethernet frame passed over for receiving PHY layer verifies whether the frame received goes out
The ethernet frame being properly received is submitted to upper layer by mistake；
CRC check module is used to verify whether the data sent to meet format and whether received data are correct；
Packet parsing module is for detecting whether the message sended and received is gPTP event message, if it is, the time
It stabs generation module and generates timestamp, be stored in FIFO, if it is not, then not handling the information；
Timestamp generation module beats timestamp for hardware, when sending and receiving gPTP message, timestamp generation module meeting
Automatically timestamp is stamped；
First Input First Output timestamp fifo module is written, the effective time being sent into for cache-time stamp generation module
Stamp, reads convenient for CPU and calculates time deviation；
Local clock module, for providing accurate nsec to timestamp generation module；
CPU module reads the timestamp cached in FIFO for reading the timestamp information carried in message, when calculating
Between deviation, RTC clock is adjusted；
Cpu i/f module is the interface of CPU module and bottom hardware, and CPU and hardware logic part is made to carry out information exchange.
The method of the present invention step are as follows: initial configuration clock information identifies that message information, hardware generate timestamp, time
Stamp saves, and calculates time deviation, clock correction according to timestamp.The method that the present invention uses Hardware/Software Collaborative Design, in fpga
Middle to utilize soft nuclear design CPU, message sends and receives, and the generation and preservation of timestamp, local clock are completed by hardware, report
The parsing of text, the reading of timestamp, the calculating of clock jitter have soft nucleus CPU to complete.
A kind of IEEE802.1AS clock synchronizing function implementation method, specifically includes the following steps:
(1) slave sends Pdelay_Req event message:
CPU module sends instruction and Pdelay_Req event message information is written in transmission RAM, is sent and is controlled by MAC
Module is sent, timestamp generation module logging timestamp t1, it is stored in First Input First Output timestamp fifo module；
(2) host receives Pdelay_Req event message, timestamp generation module logging timestamp t2, it is stored in first in, first out
Queue time stabs fifo module；
(3) host sends Pdelay_Resp message:
Timestamp information in step (2) in deposit FIFO is inserted into Pdelay_Resp message by host CPU module,
Pdelay_Resp time message information is written and is sent in RAM, control module is sent by MAC and is sent, timestamp generation module
Logging timestamp t3, it is stored in First Input First Output timestamp fifo module；
(4) slave receives Pdelay_Resp time message, timestamp generation module logging timestamp t4, it is stored in and first enters elder generation
Dequeue timestamp fifo module, and read timestamp information t included in Pdelay_Resp time message2；
(5) host sends Pdelay_Resp_Follow_Up message:
Timestamp information in step (3) in deposit FIFO is inserted into Pdelay_Resp_Follow_ by host CPU module
In Up message, Pdelay_Resp_Follow_Up time message information is written and is sent in RAM, control module is sent by MAC
It sends；
(6) slave receives Pdelay_Resp_Follow_Up time message, when reading Pdelay_Resp_Follow_Up
Between timestamp information t included in message3；
(7) time deviation formula is utilized, the time deviation of master-salve clock is calculated；
(8) it corrects from clock time:
Be added with being counted from the local clock of clock with the CPU time deviation calculated, by be worth as currently from clock
Local clock counts, and completes master-salve clock correction.
The invention has the following advantages that
First: apparatus of the present invention beat the mechanism of timestamp using hardware, can directly acquire sync message and reach data-link
At the time of between road floor MAC and physical layer PHY, the delay variation of upper-layer protocol stack is eliminated.
Second: hardware module of the present invention seldom calls relevant IP kernel, is write using general verilog language,
With good transplantability.
Third: the present invention uses soft core inside FPGA, using Hardware/Software Collaborative Design, the operation speed of very high system
Degree, reduces complexity, saves space.
4th: delay measurements and time synchronization are combined into one by the present invention using single step method for synchronizing time, reduce system
System complexity, improves efficiency, and it is synchronous to carry out clock every one second transmission Pdelay_Req event message for slave.
Detailed description of the invention
Fig. 1 is the block diagram of apparatus of the present invention.
Fig. 2 is the flow chart of the method for the present invention.
Fig. 3 is the schematic diagram that acquisition time stabs in the method for the present invention.
Specific embodiment
The present invention will be further described with reference to the accompanying drawing.
Referring to 1 device block diagram of attached drawing, apparatus of the present invention are further described.
Apparatus of the present invention include CPU module, and cpu i/f module sends data memory module, and MAC sends control module, connects
Data memory module is received, MAC receives control module, and CRC check module sends packet parsing module, receives packet parsing module,
Sending time stabs generation module, sends fifo module, and receiving time stabs generation module, receives fifo module, RTC local clock mould
Block；The output end for sending data memory module is connected with the MAC input terminal for sending control module；MAC receives control module
Output end with receive data memory module input terminal be connected；MAC receives control module and is connected with external input terminals；MAC hair
Control module is sent to be connected with external output end；CRC check module sends control module with MAC and MAC receives control module and is connected；
The input terminal that MAC receives control module is connected with the input terminal for receiving packet parsing module；The output end of MAC transmission control module
It is connected with the input terminal for sending packet parsing module；The output end and sending time for sending packet parsing module stab generation module
Input terminal is connected；The output end of sending time stamp generation module is connected with the input terminal for sending fifo module；Receive packet parsing
The output end of module is connected with the input terminal of receiving time stamp generation module；Receiving time stabs output end and the reception of generation module
The input terminal of fifo module is connected；Output end and sending time the stamp generation module and receiving time of RTC local clock module stab
The input terminal of generation module is connected；CPU module is connected by cpu i/f module with bottom hardware.
The CPU module is scheduled bottom hardware module for the process of compilation of software instruction, is responsible for obtaining thing
The timestamp information of part message calculates the time difference of master-salve clock, adjusts RTC clock.
The cpu i/f module carries out information exchange for CPU and bottom hardware, and CPU is sent out data by cpu i/f
It is sent in the register of hardware, realizes control of the software to hardware.
The transmission data memory module is the dual port RAM that memory capacity is 2K byte, stores the message to be sent letter
Breath.
The MAC sends control module, sends for the data sent in RAM to be packaged into UDP format data,
Interface with phy chip is RGMII interface.
The reception data memory module is the dual port RAM that memory capacity is 2K byte, stores the message letter received
Breath；
The MAC receives control module, for receiving the message information of UDP format, and information is stored in receive in RAM and is delayed
It deposits, the interface with phy chip is RGMII interface.
The CRC check module, for verifying, whether the data sent meet format and whether received data are correct；
Whether the transmission packet parsing module is gPTP event message for examining the message sent, if it is leads to
Know that sending time stamp generation module generates timestamp, otherwise ignores information.
It is described to receive packet parsing module, for examining whether received message is gPTP event message, if it is lead to
Know that receiving time stamp generation module generates timestamp, otherwise ignores information.
The sending time stabs generation module, for generating timestamp, when sending gPTP message information, generates the time
Stamp, is saved in transmission fifo queue.
The transmission fifo module, when sending gPTP event message for storing, the timestamp that hardware obtains automatically, CPU
The timestamp information of storage is read out by instructing.
The receiving time stabs generation module, and for generating timestamp, when receiving gPTP event message, hardware is automatic
Timestamp is beaten, and is stored in reception fifo queue.
The reception fifo module, when receiving gPTP event message for storing, the timestamp that hardware obtains automatically, CPU
The timestamp information of storage is read out by instructing.
The RTC local clock module provides accurate ns grades of temporal information for timing and to timestamp generation module.
Referring to attached drawing 2, method of the invention is further described.
Step 1, slave sends Pdelay_Req event message.
CPU sends Pdelay_Req message information by cpu i/f module, and write-in sends in RAM, refers to when receiving transmission
When enabling, MAC sends control module Information encapsulation to be sent and is sent to host at UDP format.
Step 2, slave logging timestamp t1。
When MAC, which sends control module, sends Pdelay_Req event message, sends packet parsing module and pass through parsing hair
It is now gPTP event message, sending time stamp generation module will be notified to generate timestamp t1, and be stored in FIFO.
Step 3, host receives Pdelay_Req event message.
Host MAC, which receives control module, can receive the Pdelay_Req event message that slave is sent, and by the effective of message
Information deposit receives data memory module, and CPU can read effective information by cpu i/f module；
Step 4, host record timestamp t2。
When MAC, which receives control module, receives Pdelay_Req event message, receives packet parsing module and pass through parsing hair
It is now gPTP event message, receiving time stamp generation module will be notified to generate timestamp t2, and be stored in FIFO.
Step 5, host is by t2It is inserted into Pdelay_Resp message.
CPU reads the timestamp t for receiving and storing in FIFO2, and by t2It is inserted into Pdelay_Resp message, passes through CPU
Interface module deposit sends data memory module.
Step 6, host sends Pdelay_Resp message.
After Pdelay_Resp message is stored in transmission RAM by CPU, being instructed by sending, scheduling MAC sends control module,
Send Pdelay_Resp message.
Step 7, host record timestamp t3。
When MAC, which sends control module, sends Pdelay_Resp message, sends packet parsing module and be the discovery that by parsing
GPTP event message will notify sending time stamp generation module to generate timestamp t3, and be stored in FIFO.
Step 8, host is by t3It is inserted into Pdelay_Resp_Follow_Up message.
CPU reads the timestamp t for sending and storing in FIFO3, and by t3It is inserted into Pdelay_Resp_Follow_Up message
In, it is stored in by cpu i/f module and sends data memory module.
Step 9, host sends Pdelay_Resp_Follow_Up message.
After Pdelay_Resp_Follow_Up message is stored in transmission RAM by CPU, passes through and send instruction, scheduling MAC hair
Control module is sent, Pdelay_Resp_Follow_Up message is sent.
Step 10, slave receives Pdelay_Resp message.
Slave MAC, which receives control module, can receive the Pdelay_Resp event message that host is sent, and by the effective of message
Information deposit receives data memory module, and CPU can read effective information by cpu i/f module.
Step 11, slave logging timestamp t4。
When MAC, which receives control module, receives Pdelay_Resp message, receives packet parsing module and be the discovery that by parsing
GPTP event message will notify receiving time stamp generation module to generate timestamp t4, and be stored in FIFO.
Step 12, timestamp t in slave parsing Pdelay_Resp message2。
CPU reads the Pdelay_Resp message information for receiving the storage in data memory module by cpu i/f module,
Parse timestamp t wherein included2。
Step 13, slave receives Pdelay_Resp_Follow_Up message.
Slave MAC, which receives control module, can receive the Pdelay_Resp_Follow_Up event message that host is sent, and will
The effective information deposit of message receives data memory module, and CPU can read effective information by cpu i/f module.
Step 14, timestamp t in slave parsing Pdelay_Resp_Follow_Up message3。
CPU reads the Pdelay_Resp_Follow_Up for receiving the storage in data memory module by cpu i/f module
Message information parses timestamp t wherein included3。
Step 15, slave calculates master-salve clock deviation.
CPU module calculates the deviation of master-salve clock according to the following formula:
Wherein, t indicates the time deviation of master-salve clock, t1Indicate sending time when slave sends Pdelay_Req message
Stamp, t2Indicate receiving time stamp when host receives Pdelay_Req message, t3When indicating that host sends Pdelay_Resp message
Sending time stamp, t4Indicate receiving time stamp when slave receives Pdelay_Resp message.
Step 16, slave clock is corrected.
Be added with being counted from the local clock of clock with the CPU time deviation calculated, by be worth as currently from clock
Local clock counts, and completes master-salve clock correction.
The above content is merely illustrative of the invention's technical idea, and this does not limit the scope of protection of the present invention, all to press
According to technical idea proposed by the present invention, any changes made on the basis of the technical scheme each falls within claims of the present invention
Protection scope within.
Claims (3)
1. a kind of IEEE802.1AS clock synchronizing function realizes system, which is characterized in that including sending and receiving data memory module, MAC
Control module is sent, MAC receives control module, CRC check module, packet parsing module, timestamp generation module, first in, first out
Queue time stabs fifo module, RTC clock module, CPU module and cpu i/f module；
The output end of sending and receiving data memory module is connected with the MAC input terminal for sending control module；MAC receives the defeated of control module
Outlet is connected with the input terminal for receiving data memory module；MAC receives control module and is connected with external input terminals；MAC sends control
Molding block is connected with external output end；CRC check module sends control module with MAC and MAC receives control module and is connected；MAC
The input terminal for receiving control module is connected with the input terminal for receiving packet parsing module；MAC send control module output end with
The input terminal for sending packet parsing module is connected；The input terminal phase of the output end of packet parsing module and timestamp generation module
Even；The output end of timestamp generation module is connected with the input terminal of First Input First Output timestamp fifo module；RTC clock module
Output end be connected with the input terminal of timestamp generation module；CPU module is connected by cpu i/f module with bottom hardware；
Wherein, sending and receiving data memory module is the dual port RAM of memory capacity 2K byte, and sending and receiving respectively has one, deposits respectively
The untreated data storing up data to be sent and receiving；
MAC sends control module and reads the data sent in RAM, is packaged into UDP message, is sent to outside by RGMII format
Phy chip；
MAC receives control module, and the ethernet frame passed over for receiving PHY layer verifies whether the frame received malfunctions, will
The ethernet frame being properly received submits to upper layer；
CRC check module is used to verify whether the data sent to meet format and whether the received data of verification are correct；
Packet parsing module is for detecting whether the message sended and received is gPTP event message, if it is, timestamp is raw
Timestamp is generated at module, is stored in FIFO, if it is not, then not handling the information；
Timestamp generation module beats timestamp for hardware, and when sending and receiving gPTP message, timestamp generation module can be automatic
Stamp timestamp；
First Input First Output timestamp fifo module is convenient for CPU for the effective time stamp that cache-time stamp generation module is sent into
It reads and calculates time deviation；
Local clock module, for providing accurate nsec to timestamp generation module；
CPU module reads the timestamp cached in FIFO for reading the timestamp information carried in message, and it is inclined to calculate the time
RTC clock is adjusted in difference；
Cpu i/f module is the interface of CPU module and bottom hardware, and CPU and hardware logic part is made to carry out information exchange.
2. a kind of IEEE802.1AS clock synchronizing function as described in claim 1 realizes system, which is characterized in that the system
The implementation method of system is: master-salve clock uses single step synchronous method on the platform of Hardware/Software Collaborative Design, by delay measurements
It is combined into one with two steps of time synchronization, simplifies the complexity of clock synchronization system, it is main during each synchronous interaction
Two timestamps are respectively acquired from clock, calculate master-salve clock deviation from clock according to four timestamp informations that master-salve clock acquires
Value, is calibrated according to master-salve clock deviation to from clock, and the clock for completing the network equipment in communications network system is synchronous；It should
Method comprising the following specific steps
(1) slave sends Pdelay_Req event message:
CPU module sends instruction and Pdelay_Req event message information is written in transmission RAM, sends control module by MAC
It sends, timestamp generation module logging timestamp t1, it is stored in First Input First Output timestamp fifo module；
(2) host receives Pdelay_Req event message, timestamp generation module logging timestamp t2, it is stored in First Input First Output
Timestamp fifo module；
(3) host sends Pdelay_Resp message:
Timestamp information in step (2) in deposit FIFO is inserted into Pdelay_Resp message by host CPU module, will
The write-in of Pdelay_Resp event message information is sent in RAM, is sent control module by MAC and is sent, timestamp generation module note
Record timestamp t3, it is stored in First Input First Output timestamp fifo module；
(4) slave receives Pdelay_Resp event message, timestamp generation module logging timestamp t4, it is stored in First Input First Output
Timestamp fifo module, and read timestamp information t included in Pdelay_Resp event message2；
(5) host sends Pdelay_Resp_Follow_Up message:
Timestamp information in step (3) in deposit FIFO is inserted into Pdelay_Resp_Follow_Up report by host CPU module
Pdelay_Resp_Follow_Up message information is written and is sent in RAM by Wen Zhong, is sent control module by MAC and is sent；
(6) slave receives Pdelay_Resp_Follow_Up message, reads in Pdelay_Resp_Follow_Up message and is wrapped
The timestamp information t contained3；
(7) time deviation formula is utilized, the time deviation of master-salve clock is calculated；
(8) it corrects from clock time:
With from the local clock of clock count with deviation computing module calculate time deviation be added, will with value be used as currently from when
The local clock of clock counts, and completes master-salve clock correction.
3. a kind of IEEE802.1AS clock synchronizing function as claimed in claim 2 realizes system, which is characterized in that step (7)
Described in time deviation formula it is as follows:
Wherein, t indicates the time deviation of master-salve clock, t1Indicate sending time stamp when slave sends Pdelay_Req message, t2
Indicate receiving time stamp when host receives Pdelay_Req message, t3Indicate hair when host sends Pdelay_Resp message
Send timestamp, t4Indicate receiving time stamp when slave receives Pdelay_Resp message.
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| CN110782709A (en) * | 2019-11-04 | 2020-02-11 | 四川九洲空管科技有限责任公司 | High-precision clock redundancy backup method for civil aviation ADS-B ground station system |
| CN111726188A (en) * | 2020-06-15 | 2020-09-29 | 哈工大机器人（合肥）国际创新研究院 | Method and device for synchronizing clocks of AIRT-ROS real-time system and non-real-time system |
| CN111726189A (en) * | 2020-06-15 | 2020-09-29 | 哈工大机器人（合肥）国际创新研究院 | Dual-core system clock synchronization method and device based on timestamp marking circuit |
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| CN112632642A (en) * | 2020-12-28 | 2021-04-09 | 北京深思数盾科技股份有限公司 | Clock checking method and device and electronic equipment |
| CN112838904A (en) * | 2021-01-08 | 2021-05-25 | 中国电子技术标准化研究院 | TSN network delay jitter measuring device and method |
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| CN114338032A (en) * | 2021-12-02 | 2022-04-12 | 上海健交科技服务有限责任公司 | Deep learning-oriented high-precision timestamp security verification acceleration method and device |
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| CN112632642A (en) * | 2020-12-28 | 2021-04-09 | 北京深思数盾科技股份有限公司 | Clock checking method and device and electronic equipment |
| CN112838904B (en) * | 2021-01-08 | 2023-09-08 | 中国电子技术标准化研究院 | TSN network delay jitter measuring device and method |
| CN112838904A (en) * | 2021-01-08 | 2021-05-25 | 中国电子技术标准化研究院 | TSN network delay jitter measuring device and method |
| CN112994824A (en) * | 2021-03-03 | 2021-06-18 | 山东山大电力技术股份有限公司 | Time synchronization method, device and system for IRIG-B code non-delay transmission |
| CN114138054A (en) * | 2021-10-14 | 2022-03-04 | 北京国科天迅科技有限公司 | Timestamp obtaining method and device, electronic equipment and storage medium |
| CN114338032A (en) * | 2021-12-02 | 2022-04-12 | 上海健交科技服务有限责任公司 | Deep learning-oriented high-precision timestamp security verification acceleration method and device |
| CN114338032B (en) * | 2021-12-02 | 2022-09-30 | 上海健交科技服务有限责任公司 | Deep learning-oriented high-precision timestamp security verification acceleration method and device |
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Application publication date: 20190528 |