CN112416051A - Timing method, timing device, electronic equipment and computer storage medium - Google Patents
Timing method, timing device, electronic equipment and computer storage medium Download PDFInfo
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Abstract
The invention relates to the technical field of communication, and provides a time adjusting method, a time adjusting device, electronic equipment and a computer storage medium, wherein the time adjusting method comprises the following steps: a process periodic synchronous communication mechanism is formed by a non-real-time process, a real-time process and a shared memory, the first actual period and the second actual period are used as combined parameters for measuring and calculating the delay error compensation amount through the real-time process, the delay error compensation amount is fed back to the non-real-time process from the real-time process by means of a process periodic synchronous communication mechanism, in case that the non-real-time process measures and calculates the delay error compensation amount by itself, because the timing precision of the real-time process is higher than that of the non-real-time process, therefore, the precision of calculating the delay error compensation quantity through the real-time process is higher, the delay error compensation quantity and the second actual period are used as combined parameters for adjusting the first actual period through the non-real-time process, the time adjustment precision is improved, the synchronization precision of the process periodic synchronous communication mechanism is improved, and the defect that the existing process communication mechanism has synchronization deviation is overcome.
Description
Technical Field
The invention relates to the technical field of communication, in particular to a time adjusting method, a time adjusting device, electronic equipment and a computer storage medium.
Background
At present, process communication mechanisms are generally divided into a TCP manner and an IPC manner, wherein the TCP manner can perform communication control on multiple processes based on a TCP/IP protocol, and the IPC manner can perform communication control on multiple processes based on a message queue or/and a semaphore or/and a shared memory, for example.
However, the synchronization deviation of the existing process communication mechanism is difficult to meet the real-time control requirements of some control systems, so that the control systems have high delay, for example, in a robot control system, a process communication mechanism is formed by a non-real-time process, a real-time process and a shared memory, and the synchronization precision of the process communication mechanism is influenced because the timing precision of the non-real-time process is different from that of the real-time process.
Disclosure of Invention
The invention provides a time-adjusting method, a time-adjusting device, electronic equipment and a computer storage medium, aiming at the defect that the existing process communication mechanism has synchronization deviation.
The first aspect of the present invention provides a timing method, including:
writing communication data into a shared memory through a non-real-time process, and synchronously reading the communication data in the shared memory through a real-time process, wherein the non-real-time process is suitable for being executed circularly according to a first actual period, and the real-time process is suitable for being executed circularly according to a second actual period;
detecting the first actual period according to the read communication data through the real-time process, determining a delay error compensation amount according to the first actual period and the second actual period, and writing the delay error compensation amount into the shared memory;
reading the delay error compensation amount in the shared memory through the non-real-time process, and adjusting the first actual period according to the read delay error compensation amount and the second actual period to make the first actual period approach or equal to the second actual period.
The beneficial effects of the above technical scheme are: the non-real-time process, the real-time process and the shared memory form a process periodic synchronous communication mechanism, the first actual period and the second actual period are used as combined parameters for measuring and calculating the delay error compensation quantity through the real-time process, the delay error compensation quantity is fed back to the non-real-time process from the real-time process by the process periodic synchronous communication mechanism so as to prevent the non-real-time process from measuring and calculating the delay error compensation quantity, because the timing precision of the real-time process is higher than that of the non-real-time process, namely the precision for measuring and calculating the delay error compensation quantity through the real-time process is higher, the delay error compensation quantity and the second actual period are used as combined parameters for adjusting the first actual period through the non-real-time process, the time adjusting mode is simplified, the time adjusting cost is reduced, the time adjusting precision is improved, and the synchronous precision of the process periodic synchronous communication mechanism, the method overcomes the defect that the existing process communication mechanism has synchronization deviation.
Optionally, the detecting the first actual period according to the read communication data includes: and performing difference calculation on a plurality of pieces of time information which are in one-to-one correspondence with the communication data read in the continuous second actual periods respectively to obtain the first actual periods, wherein each piece of time information is suitable for uniquely identifying the time at which the communication data are read in the corresponding second actual period.
The beneficial effects of the above technical scheme are: the method is not only beneficial to simplifying the measuring and calculating mode of the first actual period, but also beneficial to guaranteeing the accuracy and reliability of the first actual period.
Optionally, the determining a delay error compensation amount according to the first actual period and the second actual period includes: and calculating the difference value between the second actual period and the first actual period to obtain a period error, and performing proportion adjustment on the period error to obtain the delay error compensation quantity.
The beneficial effects of the above technical scheme are: the method is not only beneficial to simplifying the measuring and calculating mode of the delay error compensation amount, but also beneficial to guaranteeing the accuracy, reliability and stability of the delay error compensation amount.
Optionally, the adjusting the first actual period according to the read delay error compensation amount and the second actual period includes: and calculating the difference between the second actual period and the delay error compensation amount to obtain an expected period, and adjusting the first actual period according to the expected period.
The beneficial effects of the above technical scheme are: because the non-real-time process has a period error, namely the first actual period is adjusted along with the expected period, the first actual period is indirectly adjusted in the process of circularly executing the real-time process according to the expected period, the adjustment difficulty of the first actual period is reduced, and the first actual period is adjusted simply and quickly.
Optionally, the shared memory includes a circular queue, where the circular queue includes a storage area pointed to by the head pointer and a storage area pointed to by the tail pointer;
the synchronously reading the communication data in the shared memory through the real-time process comprises: in the second actual period, according to a third actual period smaller than the second actual period, circularly judging whether the storage area pointed by the head pointer is empty, if so, waiting for data writing in the storage area pointed by the head pointer, if not, reading the communication data from the storage area pointed by the head pointer, and when the communication data is read, adding one to the head pointer, wherein the head pointer is moved to the storage area pointed by the tail pointer after the adding one.
The beneficial effects of the above technical scheme are: compared with the second actual cycle, the time granularity of the third actual cycle is smaller, the precision of periodically checking the storage area pointed by the head pointer is higher, the method is favorable for preventing the real-time process from excessively executing the read operation on the shared memory, and is also favorable for preventing the real-time process from reading the communication data in the shared memory.
Optionally, the shared memory further includes a storage unit and a state machine that are independent from the outside of the circular queue, respectively;
the time adjusting method further comprises the following steps: and in the second practical period, when the delay error compensation quantity is written, switching the state machine from a first state suitable for disabling the boundary definition operation to a second state suitable for enabling the boundary definition operation, and switching the second state back to the first state after the boundary definition operation is performed on the delay error compensation quantity in the form of a byte stream in the storage unit according to the second state.
The beneficial effects of the above technical scheme are: the reliability of boundary limitation of byte stream data in the storage unit is guaranteed, and the process periodic synchronous communication mechanism is promoted to complete the real-time communication of the byte stream.
Optionally, the timing method further includes: in the first actual cycle, when the communication data is completely written, adding one to the tail pointer and switching the first state to the second state, and after the boundary limiting operation is performed on the communication data in the form of the byte stream in the storage area pointed by the head pointer according to the second state, switching the second state back to the first state, wherein the storage area pointed by the tail pointer after the adding one is adjacent to the storage area pointed by the head pointer.
The beneficial effects of the above technical scheme are: the method and the device are beneficial to guaranteeing the reliability of boundary definition of the byte stream data in the circular queue and promoting the real-time communication of the byte stream.
A second aspect of the present invention provides a timing device, including:
the communication data transmission module is suitable for writing communication data into a shared memory through a non-real-time process and synchronously reading the communication data in the shared memory through a real-time process, wherein the non-real-time process is suitable for being executed circularly according to a first actual period, and the real-time process is suitable for being executed circularly according to a second actual period;
the delay error control module is suitable for detecting the first actual period according to the read communication data through the real-time process, determining a delay error compensation amount according to the first actual period and the second actual period, and writing the delay error compensation amount into the shared memory;
and the actual period adjusting module is suitable for reading the delay error compensation quantity in the shared memory through the non-real-time process, and adjusting the first actual period according to the read delay error compensation quantity and the second actual period to enable the first actual period to approach or be equal to the second actual period.
A third aspect of the present invention provides an electronic device comprising: a non-volatile memory having stored thereon a computer program, the computer program being loadable and executable by the processor for implementing the timing method of the first aspect.
A fourth aspect of the present invention provides a computer storage medium configured to communicate with an electronic device and storing at least one instruction or at least one program or set of codes or set of instructions that is loaded and executed by the electronic device to implement the timing method of the first aspect.
The time adjusting device, the electronic equipment and the computer storage medium provided by the invention have the same beneficial effects as the time adjusting method respectively, and are not repeated herein.
Drawings
Fig. 1 is a schematic flow chart of a timing method according to an embodiment of the present invention;
FIG. 2 is a diagram illustrating a mechanism for periodically synchronizing communication of processes according to an embodiment of the present invention;
fig. 3 is a timing diagram illustrating one-to-one correspondence between three first actual periods and three second actual periods according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a time composition of a desired period and a second actual period according to an embodiment of the present invention;
fig. 5 is a schematic communication schematic diagram of a timing adjustment apparatus according to an embodiment of the present invention;
fig. 6 is a schematic view of a communication principle of an electronic device according to an embodiment of the present invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
In some control systems, a process provided by a non-real-time operating system is a non-real-time process, a process provided by a real-time operating system is a real-time process, and in the periodic operation processes of the non-real-time process and the real-time process respectively, because the timing precision of the non-real-time process is different from the timing precision of the real-time process, a first actual period of the non-real-time process is unequal to a second actual period of the real-time process, so that the precision of synchronous communication between the non-real-time process and the real-time process by using a shared memory is reduced, and the technical defect is faced.
Referring to fig. 1, a timing method is shown, comprising: writing the communication data into the shared memory through a non-real-time process, and synchronously reading the communication data in the shared memory through a real-time process, wherein the non-real-time process is suitable for being executed circularly according to a first actual period, and the real-time process is suitable for being executed circularly according to a second actual period; detecting the first actual period according to the read communication data through a real-time process, determining a delay error compensation amount according to the first actual period and the second actual period, and writing the delay error compensation amount into a shared memory; and reading the delay error compensation quantity in the shared memory through a non-real-time process, and adjusting the first actual period according to the read delay error compensation quantity and the second actual period to make the first actual period approach or equal to the second actual period.
Illustratively, within the robot control system, the non-real-time operating system is a Linux system, the real-time operating system is a Xenomai system, the computer program of the non-real-time process is a python language program, and the computer program of the real-time process is a C language program, for example, the non-real-time process includes a non-real-time thread adapted to control a robot arm demonstrator, a non-real-time thread adapted to control a client, and a non-real-time thread adapted to control a trajectory planner, and the real-time process includes a real-time thread adapted to control an ROS controller, by which the robot arm can be controlled for trajectory motion, see fig. 3.
Illustratively, expected periods are preset in both the non-real-time process and the real-time process, and both the non-real-time process and the real-time process are expected to be executed cyclically according to an expected period of 100ms, in fact, a first actual period of the cyclic execution of the non-real-time process may be 99ms or 102ms, and a second actual period of the cyclic execution of the real-time process is 100 ms.
Illustratively, referring to fig. 3, the non-real-time process loops through a plurality of first actual cycles, the plurality of first actual cycles including a first actual cycle and a second first actual cycle; writing the communication data corresponding to the first actual period into the shared memory in the first actual period, so that the communication data corresponding to the first actual period is the first communication data; in a second first actual period, writing the communication data corresponding to the second first actual period into the shared memory, so that the communication data corresponding to the second first actual period is second communication data, for example, the communication data is robot running track data.
Illustratively, referring to fig. 3, the real-time process loops executing a plurality of second actual cycles, the plurality of second actual cycles including a first second actual cycle and a second actual cycle; reading first communication data from a shared memory in a first and second actual period, and generating a first timestamp by using a clock function time () when the first communication data is read; reading second communication data from the shared memory in a second actual period, generating a second time stamp by using a clock function time () when the second communication data is read, and measuring and calculating the first actual period based on the first time stamp and the second time stamp; the first timestamp is time information suitable for uniquely identifying the time when the first communication data is completely read, and the second timestamp is time information suitable for uniquely identifying the time when the second communication data is completely read.
The non-real-time process, the real-time process and the shared memory form a process periodic synchronous communication mechanism, the first actual period and the second actual period are used as combined parameters for measuring and calculating the delay error compensation quantity through the real-time process, the delay error compensation quantity is fed back to the non-real-time process from the real-time process by the process periodic synchronous communication mechanism so as to prevent the non-real-time process from measuring and calculating the delay error compensation quantity, the timing precision of the real-time process is higher than that of the non-real-time process, namely the precision for measuring and calculating the delay error compensation quantity through the real-time process is higher, the delay error compensation quantity and the second actual period are used as combined parameters for adjusting the first actual period through the non-real-time process, the timing mode is facilitated to be simplified, the timing cost is reduced, the timing precision is enhanced, and the synchronization precision of the process periodic, the method overcomes the defect that the existing process communication mechanism has synchronization deviation.
Optionally, the detecting the first actual period according to the read communication data includes: and performing difference calculation on a plurality of pieces of time information which are in one-to-one correspondence with the communication data read in the continuous second actual periods respectively to obtain a first actual period, wherein each piece of time information is suitable for uniquely identifying the time at which the communication data are read in the corresponding second actual period, which is not only beneficial to simplifying the measuring and calculating mode of the first actual period, but also beneficial to ensuring the accuracy and reliability of the first actual period.
Illustratively, the relationship between the first actual period and the two time information is represented as: t isreal＝(tN-tN-i) I, wherein TrealDenotes the first actual period, tNIndicating time information corresponding to the time at which the communication data is read in the Nth second actual period by the real-time process, tN-iAnd indicating time information corresponding to the time for reading the communication data in the Nth-i-th second actual period through the real-time process, wherein i indicates the cycle times of the real-time process from the Nth-i-th second actual period to the Nth second actual period, N and i are positive integers respectively, and N is greater than i.
Taking N-2 and i-1 as an example, after the real-time process loops once, Treal＝t2-t1，t2Indicating a second time stamp, t1Representing a first time stamp, see fig. 3.
Optionally, the determining the delay error compensation amount according to the first actual period and the second actual period includes: and calculating the difference value between the second actual period and the first actual period to obtain a period error, and performing proportion adjustment on the period error to obtain a delay error compensation quantity, so that the method is not only beneficial to simplifying the measuring and calculating mode of the delay error compensation quantity, but also beneficial to guaranteeing the accuracy, reliability and stability of the delay error compensation quantity.
Illustratively, the relationship between the period error, the second actual period, and the first actual period is represented as: t iserror＝|Td-TrealL, where TerrorIndicating a periodic error, TdRepresenting a second actual period; the relationship between the delay error compensation amount and the period error is expressed as: t iscom＝K×TerrorWherein, TcomAnd K represents a preset proportion.
Optionally, adjusting the first actual period according to the read delay error compensation amount and the second actual period includes: and calculating the difference between the second actual period and the delay error compensation amount to obtain an expected period, and adjusting the first actual period according to the expected period.
Illustratively, the relationship between the desired period, the second actual period, and the delay error compensation amount is expressed as: t isd_e＝Td-TcomWherein, Td_eIndicating a desired period; the non-real-time process is in any expected period Td_eTime T consumed by running of internal programrunAnd program sleep time TsleepNamely: t isd_e＝Trun+TsleepSee, fig. 4; program sleep time TsleepA second actual period TdDelay error compensation quantity TcomAnd the time T consumed by program operationrunThe relationship between them is expressed as: t issleep＝Td-Tcom-TrunSee FIG. 4, by means of program sleep time TsleepThe first actual period is adjusted, which helps to guarantee the desired period and the second actual period.
Illustratively, the program runs time TrunExpressed as: t isrunTime _ end represents a third timestamp uniquely identifying the end time of the non-real-time process running in the expected period, time _ start represents a fourth timestamp uniquely identifying the start time of the non-real-time process running in the expected period, and the third timestamp and the fourth timestamp are respectively generated by adopting a clock function time ().
Because the non-real-time process has a period error, namely the first actual period is adjusted along with the expected period, the first actual period is indirectly adjusted in the process of circularly executing the real-time process according to the expected period, the adjustment difficulty of the first actual period is reduced, and the first actual period is adjusted simply and quickly.
Alternatively, referring to fig. 2, the shared memory includes a circular queue including a storage area pointed by a head pointer and a storage area pointed by a tail pointer, and a storage unit and a state machine independent from the circular queue, respectively, where the state machine includes at least one flag, for example, the circular queue is a circular queue, and the two flags are a first data reset flag and a second data reset flag, respectively.
Optionally, the step of synchronously reading the communication data in the shared memory through the real-time process includes: and in the second actual period, circularly judging whether the storage area pointed by the head pointer is empty or not according to a third actual period which is smaller than the second actual period, if so, waiting for writing data into the storage area pointed by the head pointer, otherwise, reading the communication data from the storage area pointed by the head pointer, and when the communication data is read, adding one to the head pointer, and moving the head pointer to the storage area pointed by the tail pointer after the adding one.
Illustratively, in the real-time process, the second actual period is set to 100ms, the third actual period is set to 1ms, and the cycle number of the third actual period is set to 50 times; in each third actual period, when the storage area pointed by the head pointer is empty, the storage area pointed by the communication data head pointer is not yet pointed by the non-real-time process, the real-time process is set to be in a blocking state, and in the blocking state, the non-real-time process is waited to write data into the storage area pointed by the head pointer; in each third actual period, when the storage area pointed by the head pointer is not empty, the storage area pointed by the head pointer of the communication data is indicated to be the storage area pointed by the non-real-time process, the storage area pointed by the head pointer is adjacent to the storage area pointed by the tail pointer when the storage area pointed by the head pointer is not empty, the communication data is completely read from the storage area pointed by the head pointer, and the head pointer is immediately moved to the storage area pointed by the tail pointer, so that the storage area pointed by the head pointer is the same as the storage area pointed by the tail pointer when the storage area pointed by the head pointer is empty, and the synchronism of the periodic synchronous communication of the process is improved.
Compared with the second actual cycle, the time granularity of the third actual cycle is smaller, the precision of periodically checking the storage area pointed by the head pointer is higher, the method is favorable for preventing the real-time process from excessively executing the read operation on the shared memory, and is also favorable for preventing the real-time process from reading the communication data in the shared memory.
Optionally, the timing method further includes: and in the second practical period, when the delay error compensation amount is written, the state machine is switched from the first state suitable for disabling the boundary limiting operation to the second state suitable for enabling the boundary limiting operation, and after the boundary limiting operation is carried out on the delay error compensation amount in the form of the byte stream in the storage unit according to the second state, the second state is switched back to the first state, so that the reliability of boundary limiting on the byte stream data in the storage unit is ensured, and the real-time communication of the byte stream is facilitated.
Illustratively, referring to FIG. 3, the delay error compensation is written to the memory in the form of a byte stream during the second actual cycle by the real-time threadIn the unit, when the delay error compensation amount is written, the second data reset flag is rewritten to 1, that is: the state machine is 01, under the condition that the state machine is 01, a boundary limiting operation is performed on the delay error compensation amount to limit the byte stream boundary of the delay error compensation amount, and when the boundary limiting operation is completed, the second data reset flag is reset to 0, that is: the state machine is 00, where t3Is time information suitable for uniquely identifying the time when the delay error compensation amount is written.
Optionally, the timing method further includes: in the first practical period, when the communication data is written, adding one to the tail pointer and switching the first state to the second state, and after boundary limiting operation is performed on the communication data in the form of byte streams in the storage area pointed by the head pointer according to the second state, switching the second state back to the first state, wherein the storage area pointed by the tail pointer after the adding one is adjacent to the storage area pointed by the head pointer, which is beneficial to ensuring the reliability of boundary limiting on the byte stream data in the circular queue and promoting the real-time communication of the byte streams.
Illustratively, referring to fig. 3, in the second first actual cycle, when the storage area pointed by the head pointer is the same as the storage area pointed by the tail pointer, the communication data is written into the storage area pointed by the tail pointer in a byte stream form, when the communication data is written, an adding process is performed on the tail pointer, and after the adding process is completed, the first data reset flag is rewritten to 1, that is: the state machine is 10, under the condition that the state machine is 10, a boundary defining operation is performed on the communication data in the storage area pointed by the head pointer to define the byte stream boundary of the communication data, and when the boundary defining operation is completed, the second data reset flag is reset to 0, that is: the state machine is 00, and for example, the tail pointer is rewritten from 1 to 2 to prevent interference caused by state switching of the state machines by multiple processes.
It should be noted that the first state refers to a state where the state machine is 0, and the second state refers to a state where the state machine is not 0, and for the sake of brief description, details are not repeated here.
Referring to fig. 5, the present invention also provides a timing device, comprising: the device comprises a communication data transmission module, a delay error control module and an actual period adjusting module.
And the communication data transmission module is suitable for writing the communication data into the shared memory through a non-real-time process and synchronously reading the communication data in the shared memory through a real-time process.
The non-real-time process is suitable for being executed circularly according to a first actual period, and the real-time process is suitable for being executed circularly according to a second actual period.
And the delay error control module is suitable for detecting the first actual period according to the read communication data through a real-time process, determining a delay error compensation amount according to the first actual period and the second actual period, and writing the delay error compensation amount into the shared memory.
And the actual period adjusting module is suitable for reading the delay error compensation quantity in the shared memory through a non-real-time process, and adjusting the first actual period according to the read delay error compensation quantity and the second actual period to enable the first actual period to approach or be equal to the second actual period.
Optionally, the communication data transmission module includes a first control sub-module and a second control sub-module.
And the first control submodule is suitable for writing the communication data into the storage area pointed by the tail pointer in a byte stream mode in each first actual period through a non-real-time process when the storage area pointed by the head pointer is the same as the storage area pointed by the tail pointer in the process of circularly executing N first actual periods, adding one to the tail pointer and switching the state machine from the first state to the second state when the communication data is written, and switching the second state back to the first state after performing boundary limiting operation on the communication data in the storage area pointed by the head pointer according to the second state, wherein N is a positive integer larger than 1, and the storage area pointed by the tail pointer after adding one to the storage area pointed by the head pointer is adjacent to the storage area pointed by the head pointer.
And the second control submodule is suitable for circularly judging whether the storage area pointed by the head pointer is not empty or not according to a third actual period smaller than the corresponding second actual period in each second actual period through a real-time process in the process of circularly executing the N second actual periods, if so, waiting for writing data into the storage area pointed by the head pointer, if not, reading the communication data from the storage area pointed by the head pointer, and when finishing reading the communication data, adding one to the head pointer and generating time information suitable for uniquely identifying the time when finishing reading the communication data, wherein the storage area pointed by the head pointer after adding one to the storage area pointed by the tail pointer is the same as the storage area pointed by the tail pointer.
Optionally, the delay error control module is specifically adapted to: detecting a first actual period according to N time information which corresponds to communication data read in the N second actual periods in a one-to-one mode in the Nth second actual period through a real-time process, determining a delay error compensation quantity according to the first actual period and the second actual period, writing the delay error compensation quantity into a storage unit in a byte stream mode, switching a state machine from a first state to a second state when the delay error compensation quantity is written, and switching the second state back to the first state after boundary limiting operation is performed on the delay error compensation quantity in the storage unit according to the second state.
Optionally, the actual period adjusting module is specifically adapted to: and reading the delay error compensation amount from the storage unit in the (N + 1) th first actual period through a non-real-time process, and adjusting the first actual period according to the delay error compensation amount and the second actual period.
The present invention also provides an electronic device comprising: a non-volatile memory storing a computer program and being couplable to the processor, the computer program being loaded and executed by the processor to implement the timing method.
Illustratively, referring to fig. 6, in the electronic device, the non-volatile memory is coupled to the processor through a universal serial bus, for example, the electronic device is an industrial personal computer in a robot control system.
The present invention also provides a computer storage medium configured to communicate with an electronic device and storing at least one instruction or at least one program or set of codes or set of instructions that is loaded and executed by the electronic device to implement the above-mentioned time-tuning method, such as a flash disk or removable hard disk or flash memory.
The terms "first", "second" and "third", etc., described herein, are used only for distinguishing devices/components/subassemblies/parts, etc., and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated, whereby the definition of features as "first", "second" and "third", etc., may explicitly or implicitly mean that at least one of such features is included, unless explicitly specifically defined otherwise, "a plurality" means at least two, e.g., two, three, etc., and those skilled in the art may specifically understand the specific meaning of the above terms in the present invention.
The terms "aspect," "optionally," and "exemplary" described herein mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or implementation is included in at least one embodiment or implementation of the invention, the term schematic representation does not necessarily refer to the same embodiment or implementation, and the described particular feature, structure, material, or characteristic may be combined in any suitable manner in any one or more embodiments or implementations.
Although the present disclosure has been described above, the scope of the present disclosure is not limited thereto. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present disclosure, and such changes and modifications will fall within the scope of the present invention.
Claims (10)
1. A time-adjusting method is characterized in that the time-adjusting method comprises the following steps:
writing communication data into a shared memory through a non-real-time process, and synchronously reading the communication data in the shared memory through a real-time process, wherein the non-real-time process is suitable for being executed circularly according to a first actual period, and the real-time process is suitable for being executed circularly according to a second actual period;
detecting the first actual period according to the read communication data through the real-time process, determining a delay error compensation amount according to the first actual period and the second actual period, and writing the delay error compensation amount into the shared memory;
reading the delay error compensation amount in the shared memory through the non-real-time process, and adjusting the first actual period according to the read delay error compensation amount and the second actual period to make the first actual period approach or equal to the second actual period.
2. The timing method according to claim 1, wherein the detecting the first actual period according to the read communication data comprises:
and performing difference calculation on a plurality of pieces of time information which are in one-to-one correspondence with the communication data read in the continuous second actual periods respectively to obtain the first actual periods, wherein each piece of time information is suitable for uniquely identifying the time at which the communication data are read in the corresponding second actual period.
3. The timing method of claim 1, wherein said determining a delay error compensation amount based on the first actual period and the second actual period comprises:
and calculating the difference value between the second actual period and the first actual period to obtain a period error, and performing proportion adjustment on the period error to obtain the delay error compensation quantity.
4. The timing method according to claim 1, wherein the adjusting the first actual period according to the read delay error compensation amount and the second actual period comprises:
and calculating the difference between the second actual period and the delay error compensation amount to obtain an expected period, and adjusting the first actual period according to the expected period.
5. The timing method according to claim 1, wherein the shared memory comprises a circular queue comprising a storage area pointed to by a head pointer and a storage area pointed to by a tail pointer;
the synchronously reading the communication data in the shared memory through the real-time process comprises: in the second actual period, according to a third actual period smaller than the second actual period, circularly judging whether the storage area pointed by the head pointer is empty, if so, waiting for data writing in the storage area pointed by the head pointer, if not, reading the communication data from the storage area pointed by the head pointer, and when the communication data is read, adding one to the head pointer, wherein the head pointer is moved to the storage area pointed by the tail pointer after the adding one.
6. The timing method according to claim 5, wherein the shared memory further comprises a storage unit and a state machine independent from the circular queue, respectively;
the time adjusting method further comprises the following steps: and in the second practical period, when the delay error compensation quantity is written, switching the state machine from a first state suitable for disabling the boundary definition operation to a second state suitable for enabling the boundary definition operation, and switching the second state back to the first state after the boundary definition operation is performed on the delay error compensation quantity in the form of a byte stream in the storage unit according to the second state.
7. The timing method of claim 6, further comprising: in the first actual cycle, when the communication data is completely written, adding one to the tail pointer and switching the first state to the second state, and after the boundary limiting operation is performed on the communication data in the form of the byte stream in the storage area pointed by the head pointer according to the second state, switching the second state back to the first state, wherein the storage area pointed by the tail pointer after the adding one is adjacent to the storage area pointed by the head pointer.
8. A timing device, comprising:
the communication data transmission module is suitable for writing communication data into a shared memory through a non-real-time process and synchronously reading the communication data in the shared memory through a real-time process, wherein the non-real-time process is suitable for being executed circularly according to a first actual period, and the real-time process is suitable for being executed circularly according to a second actual period;
the delay error control module is suitable for detecting the first actual period according to the read communication data through the real-time process, determining a delay error compensation amount according to the first actual period and the second actual period, and writing the delay error compensation amount into the shared memory;
and the actual period adjusting module is suitable for reading the delay error compensation quantity in the shared memory through the non-real-time process, and adjusting the first actual period according to the read delay error compensation quantity and the second actual period to enable the first actual period to approach or be equal to the second actual period.
9. An electronic device, comprising: non-volatile memory storing a computer program and couplable to a processor, the computer program being loaded and executed by the processor to implement the timing method as claimed in any one of claims 1 to 7.
10. A computer storage medium configured to communicate with an electronic device and storing at least one instruction or at least one program or set of codes or set of instructions that is loaded and executed by the electronic device to implement a time-shifting method as claimed in any one of claims 1 to 7.
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