CN111710756A - Novel PERC battery and manufacturing method thereof - Google Patents
Novel PERC battery and manufacturing method thereof Download PDFInfo
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- CN111710756A CN111710756A CN202010620151.2A CN202010620151A CN111710756A CN 111710756 A CN111710756 A CN 111710756A CN 202010620151 A CN202010620151 A CN 202010620151A CN 111710756 A CN111710756 A CN 111710756A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 28
- 101001073212 Arabidopsis thaliana Peroxidase 33 Proteins 0.000 title claims abstract 10
- 101001123325 Homo sapiens Peroxisome proliferator-activated receptor gamma coactivator 1-beta Proteins 0.000 title claims abstract 10
- 102100028961 Peroxisome proliferator-activated receptor gamma coactivator 1-beta Human genes 0.000 title claims abstract 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 97
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 97
- 239000010703 silicon Substances 0.000 claims abstract description 97
- 239000000758 substrate Substances 0.000 claims abstract description 75
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 58
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 57
- 238000009792 diffusion process Methods 0.000 claims abstract description 56
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 40
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 37
- 238000002161 passivation Methods 0.000 claims abstract description 26
- 238000005530 etching Methods 0.000 claims abstract description 12
- 238000001465 metallisation Methods 0.000 claims abstract description 12
- 230000001681 protective effect Effects 0.000 claims abstract description 7
- 238000002425 crystallisation Methods 0.000 claims abstract description 5
- 230000008025 crystallization Effects 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 60
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 12
- 229920005591 polysilicon Polymers 0.000 claims description 12
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 12
- 239000011521 glass Substances 0.000 claims description 11
- 230000003647 oxidation Effects 0.000 claims description 10
- 238000007254 oxidation reaction Methods 0.000 claims description 10
- 239000012670 alkaline solution Substances 0.000 claims description 9
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 8
- 239000003929 acidic solution Substances 0.000 claims description 6
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 5
- 238000007650 screen-printing Methods 0.000 claims description 4
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 claims description 3
- 238000004050 hot filament vapor deposition Methods 0.000 claims description 3
- 238000007641 inkjet printing Methods 0.000 claims description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 3
- 238000005498 polishing Methods 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 230000008569 process Effects 0.000 description 9
- 239000012535 impurity Substances 0.000 description 7
- 239000000243 solution Substances 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 239000007789 gas Substances 0.000 description 5
- 238000011065 in-situ storage Methods 0.000 description 4
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 3
- 239000003513 alkali Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 230000002411 adverse Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000008033 biological extinction Effects 0.000 description 2
- 230000002349 favourable effect Effects 0.000 description 2
- 238000005247 gettering Methods 0.000 description 2
- 235000008216 herbs Nutrition 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- XHXFXVLFKHQFAL-UHFFFAOYSA-N phosphoryl trichloride Chemical compound ClP(Cl)(Cl)=O XHXFXVLFKHQFAL-UHFFFAOYSA-N 0.000 description 2
- 238000005215 recombination Methods 0.000 description 2
- 230000006798 recombination Effects 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 210000002268 wool Anatomy 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000031700 light absorption Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000005360 phosphosilicate glass Substances 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- -1 silver-aluminum Chemical compound 0.000 description 1
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Abstract
The application discloses a novel PERC battery manufacturing method, which comprises the steps of obtaining a silicon substrate with an N-type doped layer on the front surface; forming a silicon oxide layer on the front surface of the silicon substrate; forming an amorphous silicon layer on the surface of the silicon oxide layer, which is far away from the silicon substrate; carrying out diffusion and crystallization treatment on the amorphous silicon layer to obtain a heavily doped polycrystalline silicon layer: placing the silicon substrate in diffusion equipment, firstly introducing a diffusion source to dope the amorphous silicon layer, then introducing protective gas to promote the doping, and introducing the diffusion source again to dope the amorphous silicon layer; forming a mask with a front-side metallization pattern on the surface of the polycrystalline silicon layer away from the silicon oxide layer, and carrying out back etching treatment on the polycrystalline silicon layer and the silicon oxide layer; forming a first passivation film on the back surface of the silicon substrate, and forming a second passivation film on the front surface of the silicon substrate; and (3) grooving the first passivation film, and respectively manufacturing a front electrode and a back electrode to obtain the novel PERC battery, so that the battery efficiency is improved. The present application also provides a battery having the above advantages.
Description
Technical Field
The application relates to the technical field of solar cells, in particular to a novel PERC cell and a manufacturing method thereof.
Background
PERC (passivated Emitter and Rear cell), namely passivating Emitter and Rear cell, and passivating back surface dielectric film, the local metal contact is adopted, so that the electron recombination of the back surface is obviously reduced, compared with the conventional photovoltaic cell, the efficiency of the PERC cell is higher, and the average efficiency of mass production at present reaches 22%.
To further increase the efficiency of a PERC cell, it is an effective way to reduce the electron recombination in the front side metallization region of the PERC cell. In the prior process of preparing the PERC battery, amorphous silicon is formed on the front surface and then polycrystalline silicon is formed in an in-situ diffusion mode, effective high-concentration doping is difficult to form by the in-situ diffusion method, and the in-situ diffusion method has no gettering effect on a silicon substrate and is not beneficial to the front electrode contact of the battery; meanwhile, the mask back-etching process is carried out before forming the PN junction, and the mask can generate adverse effects on texturing and diffusion, so that the open voltage and the current of the battery are influenced, and the efficiency of the PERC battery is improved to a limited extent.
Therefore, how to solve the above technical problems should be a great concern to those skilled in the art.
Disclosure of Invention
The purpose of the application is to provide a novel PERC battery and a manufacturing method thereof, so that the efficiency of the novel PERC battery is further improved.
In order to solve the above technical problem, the present application provides a method for manufacturing a novel PERC battery, including:
obtaining a silicon substrate with an N-type doped layer on the front surface;
forming a silicon oxide layer on the front surface of the silicon substrate;
forming an amorphous silicon layer on the surface of the silicon oxide layer, which is far away from the silicon substrate;
performing diffusion and crystallization treatment on the amorphous silicon layer to obtain a heavily doped polycrystalline silicon layer: placing the silicon substrate in diffusion equipment, firstly introducing a diffusion source to dope the amorphous silicon layer, then introducing protective gas to promote doping, and introducing the diffusion source again to dope the amorphous silicon layer;
forming a mask with a front metallization pattern on the surface of the polycrystalline silicon layer, which is far away from the silicon oxide layer, and carrying out back etching treatment on the polycrystalline silicon layer and the silicon oxide layer;
forming a first passivation film on the back surface of the silicon substrate, and forming a second passivation film on the front surface of the silicon substrate;
and carrying out slotting treatment on the first passivation film, and respectively manufacturing a front electrode and a back electrode to obtain the novel PERC battery.
Optionally, the etching back process performed on the polysilicon layer and the silicon oxide layer includes:
removing the phosphorosilicate glass which does not correspond to the mask by using an acidic solution, wherein the phosphorosilicate glass is generated when the polycrystalline silicon layer is formed;
removing the mask by using an alkaline solution;
removing the polysilicon layer which does not correspond to the mask by using an alkaline solution;
and removing the silicon oxide layer which does not correspond to the mask and the phosphorosilicate glass which corresponds to the mask by using an acidic solution.
Optionally, the forming a first passivation film on the back surface of the silicon substrate includes:
forming an aluminum oxide layer on the back of the silicon substrate;
and forming a silicon nitride layer on the surface of the aluminum oxide layer, which is far away from the silicon substrate.
Optionally, the forming a second passivation film on the front surface of the silicon substrate includes:
a silicon oxide layer is formed on the front surface of the silicon substrate;
and forming a silicon nitride layer on the surface of the silicon oxide layer, which is far away from the silicon substrate.
Optionally, forming a mask with a front metallization pattern on a surface of the polysilicon layer away from the silicon oxide layer includes:
the mask is formed using a screen printing method or an ink jet printing method.
Optionally, the forming a silicon oxide layer on the front surface of the silicon substrate includes:
forming the silicon oxide layer on the front surface of the silicon substrate by any one of a thermal oxidation method, an ozone oxidation method, and a wet chemical oxidation method.
Optionally, the forming of the amorphous silicon layer on the surface of the silicon oxide layer facing away from the silicon substrate includes:
and forming the amorphous silicon layer on the surface of the silicon oxide layer, which is far away from the silicon substrate, by using any one of a plasma enhanced chemical vapor deposition method, a low-pressure chemical vapor deposition method and a hot wire chemical vapor deposition method.
Optionally, obtaining the silicon substrate with the N-type doped layer on the front surface includes:
obtaining a clean and nondestructive silicon wafer;
texturing the silicon wafer;
diffusing the silicon wafer after texturing to form the N-type doping layer on the surface of the silicon wafer;
and polishing the back of the diffused silicon wafer to obtain the silicon substrate.
Optionally, the texturing the silicon wafer includes:
and texturing the silicon wafer by using an alkaline solution.
The application also provides a novel PERC battery, and the novel PERC battery is obtained by any one of the novel PERC battery manufacturing methods.
The novel PERC battery manufacturing method comprises the steps of obtaining a silicon substrate with an N-type doped layer on the front surface; forming a silicon oxide layer on the front surface of the silicon substrate; forming an amorphous silicon layer on the surface of the silicon oxide layer, which is far away from the silicon substrate; performing diffusion and crystallization treatment on the amorphous silicon layer to obtain a heavily doped polycrystalline silicon layer: placing the silicon substrate in diffusion equipment, firstly introducing a diffusion source to dope the amorphous silicon layer, then introducing protective gas to promote doping, and introducing the diffusion source again to dope the amorphous silicon layer; forming a mask with a front metallization pattern on the surface of the polycrystalline silicon layer, which is far away from the silicon oxide layer, and carrying out back etching treatment on the polycrystalline silicon layer and the silicon oxide layer; forming a first passivation film on the back surface of the silicon substrate, and forming a second passivation film on the front surface of the silicon substrate; and carrying out slotting treatment on the first passivation film, and respectively manufacturing a front electrode and a back electrode to obtain the novel PERC battery.
It can be seen that, the novel PERC cell manufacturing method in the application adopts the mode of forming a silicon oxide layer and an amorphous silicon layer firstly, and then carrying out diffusion doping, the diffusion adopts the mode of three-step diffusion, the diffusion time of a polycrystalline silicon layer at high temperature can be reduced, the doping concentration is improved, the contact of a front metalized region is facilitated, the cell efficiency is improved, furthermore, impurities in a silicon substrate can be absorbed in the diffusion process, the minority carrier lifetime is prolonged, the impurity defect in the silicon substrate is reduced, the cell efficiency is improved, in addition, the back etching treatment in the application is carried out after the silicon oxide layer and the amorphous silicon layer are formed and the diffusion doping is carried out, the influence of a mask on texturing and diffusion can be avoided, the light absorption effect of the polycrystalline silicon layer in a non-contact region is eliminated, the current of the cell is improved.
In addition, the application also provides a novel PERC battery with the advantages.
Drawings
For a clearer explanation of the embodiments or technical solutions of the prior art of the present application, the drawings needed for the description of the embodiments or prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a flowchart illustrating a method for manufacturing a novel PERC battery according to an embodiment of the present disclosure;
FIG. 2 is a flow chart of a back etching process for a polysilicon layer and a silicon oxide layer;
fig. 3 is a schematic structural diagram of a novel PERC battery according to an embodiment of the present application.
Detailed Description
In order that those skilled in the art will better understand the disclosure, the following detailed description will be given with reference to the accompanying drawings. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described and will be readily apparent to those of ordinary skill in the art without departing from the spirit of the present invention, and therefore the present invention is not limited to the specific embodiments disclosed below.
As described in the background section, in the existing manufacturing process, polysilicon is formed in an in-situ diffusion manner after amorphous silicon is formed on the front surface, high-concentration doping is difficult to form, gettering cannot be performed on a silicon substrate, and meanwhile, a mask etching process is performed before a PN junction is formed, so that the mask can adversely affect texturing and diffusion, and is not beneficial to improving the efficiency of a battery.
In view of this, the present application provides a method for manufacturing a novel PERC battery, please refer to fig. 1, where fig. 1 is a flowchart of a method for manufacturing a novel PERC battery according to an embodiment of the present application, and the method includes:
step S101: a silicon substrate with an N-doped layer on the front side is obtained.
Optionally, in an embodiment of the present application, obtaining a silicon substrate with an N-type doped layer on a front surface includes:
step S1011: and obtaining the clean and nondestructive silicon wafer.
Specifically, the silicon wafer is a P-type silicon wafer.
Step S1012: and texturing the silicon wafer.
Optionally, the silicon wafer is subjected to texturing by using an alkaline solution.
Step S1013: and diffusing the textured silicon wafer to form the N-type doped layer on the surface of the silicon wafer.
Step S1014: and polishing the back of the diffused silicon wafer to obtain the silicon substrate.
Step S102: and forming a silicon oxide layer on the front surface of the silicon substrate.
Note that the formation method of the silicon oxide layer is not limited in the present application and may be selected. For example, the silicon oxide layer is formed on the front surface of the silicon substrate by any one of a thermal oxidation method, an ozone oxidation method, and a wet chemical oxidation method.
Step S103: and forming an amorphous silicon layer on the surface of the silicon oxide layer, which is far away from the silicon substrate.
In the present application, the formation method of the amorphous silicon layer is not limited and can be selected. For example, the amorphous silicon layer is formed on the surface of the silicon oxide layer facing away from the silicon substrate by any one of a plasma enhanced chemical vapor deposition method, a low pressure chemical vapor deposition method, and a hot filament chemical vapor deposition method.
Step S104: performing diffusion and crystallization treatment on the amorphous silicon layer to obtain a heavily doped polycrystalline silicon layer: and placing the silicon substrate in diffusion equipment, firstly introducing a diffusion source to dope the amorphous silicon layer, then introducing protective gas to promote the doping, and introducing the diffusion source again to dope the amorphous silicon layer.
Specifically, when the amorphous silicon layer is doped by introducing a diffusion source, the diffusion doping temperature range is 750 ℃ to 850 ℃, the diffusion time is 30 minutes to 60 minutes, the temperature range for propelling by using protective gas is 800 ℃ to 900 ℃, the diffusion time is 20 minutes to 40 minutes, when the amorphous silicon layer is doped by introducing the diffusion source again, the diffusion doping temperature range is 750 ℃ to 800 ℃, the diffusion time is 10 minutes to 20 minutes, and the diffusion sources are all phosphorus oxychloride.
In step S104, impurities in the silicon substrate can be gettered at high temperature when the amorphous silicon layer is diffused and crystallized.
The silicon oxide layer and the heavily doped polysilicon layer bend the energy band and increase the barrier height to holes, thereby allowing electrons to pass freely and blocking holes to form a selectively passivated contact to the local metallization region.
It is noted that the protective gas includes, but is not limited to, nitrogen, argon, and the like.
Step S105: and forming a mask with a pattern of a front-side metallization pattern on the surface of the polycrystalline silicon layer, which is far away from the silicon oxide layer, and carrying out back etching treatment on the polycrystalline silicon layer and the silicon oxide layer.
It should be noted that the method for forming the mask in the present application includes, but is not limited to, a screen printing method or an ink jet printing method. The mask has the characteristics of acid resistance and alkali resistance, and the front-side metallization pattern is a pattern which is consistent with the front-side electrode grid line in shape.
Step S106: and forming a first passivation film on the back surface of the silicon substrate, and forming a second passivation film on the front surface of the silicon substrate.
Optionally, in an embodiment of the present application, the forming of the first passivation film on the back surface of the silicon substrate includes:
step S1061: and forming an aluminum oxide layer on the back surface of the silicon substrate.
Specifically, the aluminum oxide layer may be formed by an atomic layer deposition method.
Step S1062: and forming a silicon nitride layer on the surface of the aluminum oxide layer, which is far away from the silicon substrate.
Specifically, a silicon nitride layer may be formed by a plasma enhanced chemical vapor deposition method.
Optionally, in an embodiment of the present application, the forming a second passivation film on the front surface of the silicon substrate includes:
step S1063: the front surface of the silicon substrate forms a silicon oxide layer.
Note that the method of forming the silicon oxide layer in this step includes, but is not limited to, a chemical vapor deposition method, a thermal oxidation method.
Step S1064: and forming a silicon nitride layer on the surface of the silicon oxide layer, which is far away from the silicon substrate.
Specifically, the silicon nitride layer may be prepared by a plasma enhanced chemical vapor deposition method.
Optionally, in other embodiments of the present application, the second passivation film may also be a silicon nitride layer.
Step S107: and carrying out slotting treatment on the first passivation film, and respectively manufacturing a front electrode and a back electrode to obtain the novel PERC battery.
Specifically, a screen printing method is adopted to manufacture a front electrode and a back electrode, wherein the front electrode can be a silver electrode and forms ohmic contact with a polycrystalline silicon layer; the back electrode can be a silver electrode or a silver-aluminum alloy electrode and forms ohmic contact with the silicon substrate.
The process of performing the etch back process on the polysilicon layer and the silicon oxide layer will be described in detail below.
Referring to fig. 2, the etching back process includes:
step S201: and removing the phosphorosilicate glass which does not correspond to the mask by using an acidic solution, wherein the phosphorosilicate glass is generated when the polycrystalline silicon layer is formed.
Preferably, the phosphorosilicate glass not corresponding to the mask is removed with an HF solution having a volume fraction of 2% to 10% at a temperature of 25 ℃, the phosphorosilicate glass being located between the polycrystalline silicon layer and the mask.
Step S202: the mask is removed using an alkaline solution.
Preferably, the mask is removed using a sodium hydroxide solution or a potassium hydroxide solution with a volume fraction of 2% to 10% at a temperature of 25 ℃.
Step S203: and removing the polycrystalline silicon layer which does not correspond to the mask by using an alkaline solution.
Preferably, after heating the alkali solution to 60 to 80 ℃, the polysilicon layer not corresponding to the mask is removed by the heated alkali solution.
Step S204: and removing the silicon oxide layer which does not correspond to the mask and the phosphorosilicate glass which corresponds to the mask by using an acidic solution.
Preferably, the silicon oxide layer not corresponding to the mask and the phosphosilicate glass corresponding to the mask are removed with an HF solution having a volume fraction of 2% to 10% at a temperature of 25 ℃.
The novel PERC battery manufacturing method in this application adopts and forms silicon oxide layer and amorphous silicon layer earlier, then the mode of diffusion doping, the mode of diffusion three steps of diffusion is adopted in the diffusion, can reduce the diffusion time of polycrystalline silicon layer under the high temperature, improve doping concentration, be favorable to the contact in positive metallization region, promote battery efficiency, and, impurity in the silicon substrate can be absorbed and removed in the diffusion process, improve minority carrier lifetime, reduce the impurity defect in the silicon substrate, promote battery efficiency, in addition, the processing is carved back and is being formed silicon oxide layer and amorphous silicon layer in this application, diffusion doping back is gone on, can avoid the influence of mask to making herbs into wool and diffusion, eliminate the extinction effect of non-contact region polycrystalline silicon layer, promote the electric current of battery, and then improve battery efficiency.
Referring to fig. 3, the present application further provides a novel PERC battery obtained by the above method, the battery includes a silicon substrate 1 having an N-type doped layer 2 on a front surface thereof, a second passivation film 3, a silicon oxide layer 4, a polysilicon layer 5, a front electrode 6, a first passivation film 7, and a back electrode 8.
Optionally, the second passivation film 3 is a silicon nitride layer or a stacked layer of a silicon oxide layer and a silicon nitride layer.
Specifically, the first passivation film 7 includes an aluminum oxide layer 71 and a silicon nitride layer 72.
Novel PERC battery in this application adopts earlier formation silicon oxide layer and amorphous silicon layer in the manufacture process, then carry out the mode of diffusion doping, the mode of diffusion adoption three steps of diffusion, can reduce the diffusion time of polycrystalline silicon layer under high temperature, improve doping concentration, be favorable to the contact in positive metallization region, promote battery efficiency, and, impurity in the silicon substrate can be absorbed and removed in the diffusion process, improve minority carrier lifetime, reduce the impurity defect in the silicon substrate, promote battery efficiency, in addition, the processing of carving back in this application is forming silicon oxide layer and amorphous silicon layer, the diffusion carries out after doping, can avoid the influence of mask to making herbs into wool and diffusion, eliminate the extinction effect of non-contact region polycrystalline silicon layer, promote the electric current of battery, and then improve battery efficiency.
The embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same or similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
The detailed description of the novel PERC cell and the method for manufacturing the same are provided above. The principles and embodiments of the present application are explained herein using specific examples, which are provided only to help understand the method and the core idea of the present application. It should be noted that, for those skilled in the art, it is possible to make several improvements and modifications to the present application without departing from the principle of the present application, and such improvements and modifications also fall within the scope of the claims of the present application.
Claims (10)
1. A novel method for manufacturing a PERC battery is characterized by comprising the following steps:
obtaining a silicon substrate with an N-type doped layer on the front surface;
forming a silicon oxide layer on the front surface of the silicon substrate;
forming an amorphous silicon layer on the surface of the silicon oxide layer, which is far away from the silicon substrate;
performing diffusion and crystallization treatment on the amorphous silicon layer to obtain a heavily doped polycrystalline silicon layer: placing the silicon substrate in diffusion equipment, firstly introducing a diffusion source to dope the amorphous silicon layer, then introducing protective gas to promote doping, and introducing the diffusion source again to dope the amorphous silicon layer;
forming a mask with a front metallization pattern on the surface of the polycrystalline silicon layer, which is far away from the silicon oxide layer, and carrying out back etching treatment on the polycrystalline silicon layer and the silicon oxide layer;
forming a first passivation film on the back surface of the silicon substrate, and forming a second passivation film on the front surface of the silicon substrate;
and carrying out slotting treatment on the first passivation film, and respectively manufacturing a front electrode and a back electrode to obtain the novel PERC battery.
2. The method of claim 1, wherein said back etching said polysilicon layer and said silicon oxide layer comprises:
removing the phosphorosilicate glass which does not correspond to the mask by using an acidic solution, wherein the phosphorosilicate glass is generated when the polycrystalline silicon layer is formed;
removing the mask by using an alkaline solution;
removing the polysilicon layer which does not correspond to the mask by using an alkaline solution;
and removing the silicon oxide layer which does not correspond to the mask and the phosphorosilicate glass which corresponds to the mask by using an acidic solution.
3. The method of fabricating a novel PERC cell according to claim 1, wherein forming a first passivation film on the back side of said silicon substrate comprises:
forming an aluminum oxide layer on the back of the silicon substrate;
and forming a silicon nitride layer on the surface of the aluminum oxide layer, which is far away from the silicon substrate.
4. The method of fabricating a novel PERC cell according to claim 1, wherein forming a second passivation film on said front side of said silicon substrate comprises:
a silicon oxide layer is formed on the front surface of the silicon substrate;
and forming a silicon nitride layer on the surface of the silicon oxide layer, which is far away from the silicon substrate.
5. The method of claim 1, wherein forming a mask patterned as a front-side metallization pattern on a surface of said polysilicon layer facing away from said silicon oxide layer comprises:
the mask is formed using a screen printing method or an ink jet printing method.
6. The method of claim 1, wherein forming a silicon oxide layer on the front side of the silicon substrate comprises:
forming the silicon oxide layer on the front surface of the silicon substrate by any one of a thermal oxidation method, an ozone oxidation method, and a wet chemical oxidation method.
7. The method of claim 1, wherein forming an amorphous silicon layer on a surface of the silicon oxide layer facing away from the silicon substrate comprises:
and forming the amorphous silicon layer on the surface of the silicon oxide layer, which is far away from the silicon substrate, by using any one of a plasma enhanced chemical vapor deposition method, a low-pressure chemical vapor deposition method and a hot wire chemical vapor deposition method.
8. The method of any one of claims 1 to 7, wherein obtaining a silicon substrate with an N-doped layer on the front surface comprises:
obtaining a clean and nondestructive silicon wafer;
texturing the silicon wafer;
diffusing the silicon wafer after texturing to form the N-type doping layer on the surface of the silicon wafer;
and polishing the back of the diffused silicon wafer to obtain the silicon substrate.
9. The method of fabricating the novel PERC cell of claim 8, wherein texturing the silicon wafer comprises:
and texturing the silicon wafer by using an alkaline solution.
10. A novel PERC cell, characterized in that it is obtained by the method for manufacturing a novel PERC cell according to any one of claims 1 to 9.
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| CN116525717A (en) * | 2023-05-09 | 2023-08-01 | 安徽华晟新能源科技有限公司 | Method for forming semiconductor substrate layer and method for preparing heterojunction battery |
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