CN111679173A

CN111679173A - Structure is surveyd in real time to chip internal signal

Info

Publication number: CN111679173A
Application number: CN202010531368.6A
Authority: CN
Inventors: 符青; 倪暹
Original assignee: Jiangsu Huachuang Micro System Co ltd; CETC 14 Research Institute
Current assignee: Jiangsu Huachuang Micro System Co ltd; CETC 14 Research Institute
Priority date: 2020-06-11
Filing date: 2020-06-11
Publication date: 2020-09-18

Abstract

The invention discloses a chip internal signal real-time observation structure which comprises a chip, wherein a third sub-module is electrically connected with a first multiplexing selector, the first sub-module and a second sub-module are electrically connected with a second multiplexing selector, the second multiplexing selector is electrically connected with a third multiplexing selector, functional signals in the chip are electrically connected with the third multiplexing selector, and the third multiplexing selector is electrically connected with peripheral pins of the chip. The method has the advantages that as many key signals as possible in the chip can be observed, the state in the chip can be deduced in real time, the debugging of the chip is facilitated, the internal state of the chip is deduced by observing the observation signals aiming at scenes which are not met or considered in simulation verification, then the working mode of the chip is adjusted, the actual application scenes are responded, fewer chip peripheral pins are used, the observation of a large number of key signals in the chip is realized, and the debugging of the chip is facilitated.

Description

Structure is surveyd in real time to chip internal signal

Technical Field

The invention relates to the technical field of chip monitoring, in particular to a real-time observation structure for internal signals of a chip.

Background

There are a large number of signals in the ASIC chip, which need to be observed during the debugging process of the chip, and the current observation method is generally to connect these signals directly to the pins of the chip or to read them through the JTAG protocol. However, the number of peripheral pins of the chip is limited, which is not enough to meet the requirement that a large number of signals need to be observed, only single information can be observed each time in a JTAG protocol reading mode, the observability is not high, and the chip is not intuitive.

Disclosure of Invention

The present invention is directed to a real-time chip internal signal observation structure, so as to solve the problems mentioned in the background art.

In order to achieve the purpose, the invention provides the following technical scheme: a chip internal signal real-time observation structure comprises a chip, wherein a first sub-module and a second sub-module are arranged in the chip, a third sub-module is arranged in the first sub-module and is in electric signal connection with a first multiplexing selector, the first sub-module and the second sub-module are in electric signal connection with a second multiplexing selector, the second multiplexing selector is in electric signal connection with a third multiplexing selector, functional signals in the chip are electrically connected with the third multiplexing selector, and the third multiplexing selector is electrically connected with peripheral pins of the chip.

Preferably, the number of the third sub-modules is at least two.

Preferably, the electrical signals between the third sub-module and the first multiplexing selector, the electrical signals between the first sub-module and the second multiplexing selector, and the electrical signals between the second multiplexing selector and the third multiplexing selector are observation signals.

Preferably, the selection signals of the first multiplexing selector, the second multiplexing selector and the third multiplexing selector are all provided by registers inside the chip, and different values of the registers correspond to the selection signals of the first multiplexing selector, the second multiplexing selector and the third multiplexing selector respectively.

Preferably, the chip is an ASIC chip.

Compared with the prior art, the invention has the beneficial effects that: the utility model provides a chip internal signal observes structure in real time, this device all integrates each module in the inside of chip, make the observation to the signal become a function of chip, it is more convenient to use, can observe the chip inside as much as possible key signal, infer the state of chip inside in real time, the debugging of chip is very favorable to, to some scenes that do not meet or do not consider in the emulation verification, through observing these observation signals, infer the internal state of chip, then adjust the working method of chip, in order to deal with practical application scene, use less chip peripheral pin, realize the side of seeing to a large amount of key signal in the chip, make things convenient for the debugging of chip.

Drawings

FIG. 1 is a schematic structural diagram of the present invention.

In the figure: 1. the circuit comprises a chip, 2, a first submodule, 3, a second submodule, 4, a third submodule, 5, a first multiplexing selector, 6, a second multiplexing selector, 7, a third multiplexing selector, 8 and a register.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Referring to fig. 1, the present invention provides a technical solution: a chip internal signal real-time observation structure comprises a chip 1, wherein the chip 1 is an ASIC chip, a first sub-module 2 and a second sub-module 3 are arranged in the chip 1, a third sub-module 4 is arranged in the first sub-module 2, the number of the third sub-modules 4 is at least two, the number of the third sub-modules 4 can be set according to the number of observation signals to be observed, the third sub-modules 4 are in electric signal connection with a first multiplexing selector 5, signals to be observed of the third sub-modules 4 in the first sub-module 2 are multiplexed through the first multiplexing selector 5 and then output backwards, the first sub-modules 2 and the second sub-modules 3 are in electric signal connection with a second multiplexing selector 6, the observation signals output by the first sub-modules 2 and the observation signals output by the second sub-modules 3 are in time division multiplexing through the second multiplexing selector 6, the second multiplexing selector 6 is in electric signal connection with a third multiplexing selector 7, the functional signals in the chip 1 are electrically connected with a third multiplexing selector 7, the third multiplexing selector 7 is electrically connected with peripheral pins of the chip 1, observation signals multiplexed by the second multiplexing selector 6 and the functional signals in the chip 1 are subjected to time division multiplexing, and finally output through the peripheral pins of the chip 1.

The electrical signals between the third submodule 4 and the first multiplexer 5, the electrical signals between the first submodule 2 and the second submodule 3 and the second multiplexer 6, and the electrical signals between the second multiplexer 6 and the third multiplexer 7 are observation signals.

The selection signals of the first multiplexing selector 5, the second multiplexing selector 6 and the third multiplexing selector 7 are all provided by a register 8 in the chip 1, different values of the register 8 correspond to the selection signals of the first multiplexing selector 5, the second multiplexing selector 6 and the third multiplexing selector 7 respectively, and different values of the register 8 correspond to different selection signals, so that the first multiplexing selector 5, the second multiplexing selector 6 and the third multiplexing selector 7 can be selected, and the output of observation signals of different modules is realized.

Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.

Claims

1. A chip internal signal real-time observation structure comprises a chip (1), and is characterized in that: the chip is characterized in that a first submodule (2) and a second submodule (3) are arranged in the chip (1), a third submodule (4) is arranged in the first submodule (2), the third submodule (4) is electrically connected with a first multiplexing selector (5), the first submodule (2) and the second submodule (3) are electrically connected with a second multiplexing selector (6), the second multiplexing selector (6) is electrically connected with a third multiplexing selector (7), functional signals in the chip (1) are electrically connected with the third multiplexing selector (7), and the third multiplexing selector (7) is electrically connected with peripheral pins of the chip (1).

2. The structure of claim 1, wherein the chip internal signal real-time observation structure comprises: the number of the third sub-modules (4) is at least two.

3. The structure of claim 1, wherein the chip internal signal real-time observation structure comprises: and the electric signals between the third sub-module (4) and the first multiplexing selector (5), the electric signals between the first sub-module (2) and the second sub-module (3) and the second multiplexing selector (6), and the electric signals between the second multiplexing selector (6) and the third multiplexing selector (7) are observation signals.

4. The structure of claim 1, wherein the chip internal signal real-time observation structure comprises: the selection signals of the first multiplexing selector (5), the second multiplexing selector (6) and the third multiplexing selector (7) are all provided by a register (8) inside the chip (1), and different values of the register (8) respectively correspond to the selection signals of the first multiplexing selector (5), the second multiplexing selector (6) and the third multiplexing selector (7).

5. The structure of claim 1, wherein the chip internal signal real-time observation structure comprises: the chip (1) is an ASIC chip.