CN114184930A

CN114184930A - Multi-channel protection plate comprehensive test circuit

Info

Publication number: CN114184930A
Application number: CN202111284473.5A
Authority: CN
Inventors: 江学文; 郑楚滨; 巫伟升
Original assignee: Shenzhen Antuosen Instrument Co ltd
Current assignee: Shenzhen Antuosen Instrument Co ltd
Priority date: 2021-11-01
Filing date: 2021-11-01
Publication date: 2022-03-15
Anticipated expiration: 2041-11-01
Also published as: CN114184930B

Abstract

The invention discloses a multi-channel protection plate comprehensive test circuit, which has the parameter test functions of single-section overcharge point test, full-current protection point test, single-section overdischarge point test, bottom-current protection point test, high-temperature protection point test and the like, has the standby current test function, can measure microampere-level micro current by standby current, has more comprehensive test, simulates NTC resistance test by using a digital potentiometer way, greatly reduces the volume of a high-temperature test circuit, designs a multi-string battery cell circuit module and a main control circuit module 1 integrated on a circuit board by using a simplified circuit, reduces peripheral wiring and the whole volume, can realize the simultaneous measurement of multi-channel and multi-battery cells by using a mode of distinguishing the address of each module by using a dial switch, has simple and small circuit and low cost, and can send all test data to an upper computer, and the host computer produces a report and records the test result.

Description

Multi-channel protection plate comprehensive test circuit

Technical Field

The invention belongs to the technical field of circuits, and particularly relates to a comprehensive test circuit for a multi-channel protection board.

Background

At present, the comprehensive test mode for testing the battery cell protection plate is to use a DC power supply and a DC load to be matched with a simulation battery cell together to read battery cell data by utilizing the current and a voltmeter inside the DC power supply and the electronic load, and use a relay and a resistor to be matched and switched to complete the simulation NTC resistor test, and the test mode can effectively test the single-section over-charge point test of the battery cell protection plate, the full-power protection point test, the single-section over-discharge point test, the bottom-power protection point test, the high-temperature protection point test and other parameter tests, but the test mode has the following defects: the system of test is that the whole system volume of independent module is higher, and the cost is great, and this system can not test the standby current isoparametric of electricity core protection shield, and the error rate is higher when needing the more test of interconnecting link during the test.

Disclosure of Invention

In order to overcome the defects of the prior art, the invention provides a comprehensive test circuit of a multi-channel protection plate, which has complete test functions, small volume and low cost.

The technical scheme adopted by the invention for solving the technical problems is as follows: a multi-channel protection plate comprehensive test circuit comprises a main control circuit module and a plurality of battery cell circuit modules, wherein the main control circuit module is connected with the plurality of battery cell circuit modules;

the main control circuit module comprises a first single chip microcomputer control circuit, a standby current detection input interface, a standby current detection gear switching circuit, a battery detection input interface, a first ADC detection circuit, a first channel selection circuit and a first communication circuit;

the standby current detection input interface is connected with the battery cell protection board to be detected, and the standby current detection gear switching circuit is connected between the standby current detection input interface and the first single-chip microcomputer control circuit and is used for providing circuits with various resistance values;

the battery detection input interface is connected with a battery;

the first ADC detection circuit is connected between the battery detection input interface and the first single-chip microcomputer control circuit, is connected with the standby current detection gear switching circuit, is used for detecting and converting current signals of the battery detection input interface and the standby current detection gear switching circuit, and transmits the current signals to the first single-chip microcomputer control circuit;

the first channel selection circuit is connected with the first single-chip microcomputer control circuit and used for providing a plurality of detection channels;

the first communication circuit is connected with the first single-chip microcomputer control circuit and is used for transmitting signals between the first single-chip microcomputer control circuit and the upper computer;

the first singlechip control circuit is used for receiving signals of all the connecting circuits and sending signals to all the connecting circuits;

the battery cell circuit module is used for simulating a battery cell.

In the above technical solution, the single cell circuit module includes a discharge driving circuit, a charge driving circuit, a cell output interface, a charge and discharge control circuit, a second single-chip microcomputer control circuit, a second ADC detection circuit, a second channel selection circuit, a power supply, and a second communication circuit;

the discharge driving circuit is connected with the charge-discharge control circuit and is used for controlling the current output within a safe range;

the charging driving circuit is connected with the discharging driving circuit through the electric core output interface, is connected with the power supply and is used for receiving and storing electric quantity;

the charging and discharging control circuit is connected with the discharging drive circuit and the charging drive circuit and is used for controlling the discharging amount and the charging amount of the discharging drive circuit and the charging drive circuit;

the second ADC detection circuit is connected between the discharge drive circuit and the second singlechip control circuit and is used for sending the current information collected in the discharge drive circuit to the second singlechip control circuit;

the second communication circuit is connected between the first single-chip microcomputer control circuit and the second single-chip microcomputer control circuit and is used for carrying out signal transmission between the two single-chip microcomputer control circuits;

the second channel selection circuit is connected with the singlechip control circuit and is used for providing a plurality of detection channels;

the second singlechip control circuit is used for receiving signals of the connecting circuits and sending signals to the connecting circuits.

The master control circuit module also comprises an analog resistance circuit, an NTC resistance output interface, a low-resistance analog circuit and a resistance gear switching circuit;

the analog resistance circuit is connected with the first singlechip control circuit and is used for receiving signals of the singlechip and adjusting the signals into corresponding resistance values;

the NTC resistance output interface is connected with the analog resistance circuit and is used for being connected with a battery cell protection board to be tested;

the low-resistance analog circuit is connected with the resistance gear switching circuit and is used for providing a circuit with a low resistance value;

the resistance gear switching circuit is connected between the low-resistance analog circuit and the first single-chip microcomputer control circuit, is connected with the analog resistance circuit, and is used for switching between the analog resistance circuit and the low-resistance analog circuit according to an instruction of the first single-chip microcomputer control circuit.

In the technical scheme, the analog resistor circuit comprises a digital potentiometer U13, a digital potentiometer U15 and a digital potentiometer U16, two adjustable resistors are arranged in each digital potentiometer, CS pins and SCK pins of the three digital potentiometers are connected with a first single-chip microcomputer control circuit, a data overflow pin SHDN of the digital potentiometer U13 is connected with an input pin SI of the digital potentiometer U15 to form cascade connection, and a data overflow pin SHDN of the digital potentiometer U15 is connected with the input pin SI of the digital potentiometer U16 to form cascade connection; the SI pin of the digital potentiometer U13 is connected with the first singlechip control circuit; an FB1 pin and an FW1 pin of a digital potentiometer U13 are connected to form one end of an analog resistor, a PA1 pin and a PA2 pin of U13 are connected, a PW2 pin and a PB2 pin of U13 are connected with a PW2 pin and a PB2 pin of U15, a PA2 pin and a PA1 pin of U15 are connected, a PB1 pin and a PW1 pin of U15 are connected with a PB1 pin and a PW1 pin of U16, a PA1 pin and a PA2 pin of U16 are connected, and a PB2 pin and a PW2 pin of U16 are connected to form the other end of the analog resistor.

In the technical scheme, the low-resistance analog circuit and the resistance gear switching circuit comprise a digital potentiometer U17, a relay switch JK1, an optocoupler U17 and a triode Q9; the CS pin, the SCK pin and the SI pin of the U14 are connected with a first single-chip microcomputer control circuit, the JK1 is provided with two groups of switches, the PB pin of the U14 is connected with the first group of common end pins of the JK1, the PB pin and the PW pin of the U14 are connected with the second group of common end pins of the JK1, and the first group of normally open pins and the second group of normally open pins of the JK1 are connected to an NTC output interface; the optocoupler U17 is connected with the first singlechip control circuit and connected with the triode Q9, and the current flowing through the triode Q9 is induced with the coil of the JK 1.

In the above technical solution, the first channel selection circuit includes a dial switch S1 and a plurality of resistors, and the plurality of resistors are respectively connected to each pin of the dial switch S1.

The first communication circuit in the technical scheme uploads the digital signals to the upper computer by an RS485 protocol.

In the above technical solution, the discharge driving circuit includes a power interface, a fuse FU1_1, a diode D2_1, a diode D3_1, a capacitor CT4_1, a capacitor C5_1, a transistor Q1_1, a transistor Q2_1, a resistor RC1_1, a resistor R3_1, a resistor R4_1, and a resistor R6_ 1;

the power interface is connected with an emitter of a triode Q1_1, a fuse FU1_1 is connected between the power interface and the triode Q1_1, a diode D3_1 and a capacitor CT4_1 are connected between the fuse FU1_1 and the triode Q1_1 in parallel, a cathode of the diode D3_1 is connected with a positive level of the power interface, a positive level of the diode D3_1 is connected with a negative level of the power interface, a resistor R3_1 connects a base of the triode Q1_1 to the positive level of the power interface, a base of the triode Q1_1 is connected with a collector of the triode Q2_1 through the R4_1, an emitter of the triode Q2_1 is connected with the negative level of the power interface, a base of the triode Q2_1 is connected with a discharge control circuit through the resistor R6_1, and the diode D2_1, the resistor RC1_1 is connected in series with the triode Q1_1, the capacitor C5_1 is connected in parallel between the diode D2_1 and the resistor RC1_1, and the resistor RC1_1 is connected with the output interface.

The invention has the beneficial effects that: the multi-channel protection plate comprehensive test circuit provided by the invention not only has the functions of the existing test circuit, but also is added with a standby current test function, the standby current can measure microampere-level micro current, the test is more comprehensive, an NTC resistance test is simulated by using a digital potentiometer way, the volume size of a high-temperature test circuit is greatly reduced, a plurality of strings of cell circuit modules and a main control circuit module are designed by using a simplified circuit and integrated on a circuit board, the peripheral wiring is reduced, the whole volume is reduced, the multi-channel multi-cell simultaneous measurement can be realized by using a mode of distinguishing the address of each module by using a dial switch, a simple element circuit is simple and small, the cost is lower, all test data can be sent to an upper computer, the upper computer can produce reports and record test results, the test is more professional, and the over-current protection and over-voltage protection functions are designed in the invention, the test is safer, the invention has the characteristics of high reliability, high stability, high precision and the like, and the invention can test mobile power supplies, wearable equipment and various digital products with electric core protection plates.

Drawings

Fig. 1 is a schematic block diagram of a multi-channel protection board comprehensive test circuit according to the present invention.

Fig. 2 is a diagram of an embodiment of an NTC resistor output interface and a battery detection input interface circuit in a multi-channel protection board comprehensive test circuit according to the present invention.

Fig. 3 is a diagram of an embodiment of an analog resistor circuit in a multi-channel protection board comprehensive test circuit according to the present invention.

Fig. 4 is a diagram of an embodiment of a low-resistance analog circuit and a resistance step switching circuit in a multi-channel protection board integrated test circuit according to the present invention.

Fig. 5 is a diagram of an embodiment of a standby current input interface and a standby current detection shift switching circuit in a multi-channel protection board integrated test circuit according to the present invention.

Fig. 6 is a diagram of an embodiment of a first ADC detection circuit in a multi-channel protection board integrated test circuit according to the invention.

Fig. 7 is a diagram of an embodiment of a first single-chip microcomputer control circuit and a first channel selection circuit in a multi-channel protection board comprehensive test circuit according to the invention.

Fig. 8 is a diagram of an embodiment of a first communication circuit in a multi-channel protection board integrated test circuit according to the invention.

Fig. 9 is a diagram of an embodiment of a discharge driving circuit in a multi-channel protection board integrated test circuit according to the present invention.

Fig. 10 is a diagram of an embodiment of a charging driving circuit and a charging/discharging control circuit in a multi-channel protection board integrated test circuit according to the invention.

Fig. 11 is a diagram of an embodiment of a second ADC detecting circuit in the multi-channel protection board integrated test circuit according to the invention.

FIG. 12 is a diagram of an embodiment of a second single-chip microcomputer control circuit and a second channel selection circuit in the multi-channel protection board integrated test circuit according to the invention.

FIG. 13 is a diagram of an embodiment of a second communication circuit in the multi-channel protection board integrated test circuit according to the invention.

Detailed Description

The invention is further illustrated with reference to the following figures and examples.

The conception, the specific structure, and the technical effects produced by the present invention will be clearly and completely described below in conjunction with the embodiments and the accompanying drawings to fully understand the objects, the features, and the effects of the present invention. It is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments, and those skilled in the art can obtain other embodiments without inventive effort based on the embodiments of the present invention, and all embodiments are within the protection scope of the present invention. In addition, all the connection/connection relations referred to in the patent do not mean that the components are directly connected, but mean that a better connection structure can be formed by adding or reducing connection auxiliary components according to specific implementation conditions. All technical characteristics in the invention can be interactively combined on the premise of not conflicting with each other.

Referring to fig. 1, as shown in the figure, the invention provides a multi-channel protection board comprehensive test circuit, which includes a main

control circuit module

1 and 4 cell circuit modules 2, wherein the main control circuit module 1 is connected with the 4 cell circuit modules 2; the main control circuit module 1 comprises a first singlechip control circuit 3, an NTC resistance output interface 5, an analog resistance circuit 4, a low resistance analog circuit 7, a resistance gear switching circuit 6, a standby current detection input interface 9, a standby current detection gear switching circuit 8, a battery detection input interface 11, a first ADC detection circuit 10, a first channel selection circuit 13 and a first communication circuit 12; the single battery cell circuit module 2 comprises a second single chip microcomputer control circuit 15, a charge and discharge control circuit 19, a discharge driving circuit 20, a charge driving circuit 22, a battery cell output interface 21, a second ADC detection circuit 16, a second channel selection circuit 18 and a second communication circuit 17; the analog resistance circuit 4 is connected with the first singlechip control circuit 3 and is used for receiving signals of the singlechip and adjusting the signals into corresponding resistance values; the NTC resistance output interface 5 is connected with the analog resistance circuit 4 and is used for being connected with a battery core protection board to be tested; the low-resistance analog circuit 7 is connected with the resistance gear switching circuit 6 and is used for providing a circuit with a low resistance value;

the resistance gear switching circuit 6 is connected between the low-resistance analog circuit 7 and the first singlechip control circuit 3, is connected with the analog resistance circuit 4, and is used for switching between the analog resistance circuit 4 and the low-resistance analog circuit 7 according to an instruction of the first singlechip control circuit 3; the standby current detection input interface 9 is connected with the battery cell protection board to be detected, and the standby current detection gear switching circuit 8 is connected between the standby current detection input interface 9 and the first singlechip control circuit 3 and is used for providing circuits with various resistance values; the battery detection input interface 11 is connected with a battery; the first ADC detection circuit 10 is connected between the battery detection input interface 11 and the first single-chip microcomputer control circuit 3, connected with the standby current detection gear switching circuit 8, and configured to detect and convert current signals of the battery detection input interface 11 and the standby current detection gear switching circuit 8, and transmit the current signals to the first single-chip microcomputer control circuit 3; the first channel selection circuit 13 is connected with the first singlechip control circuit 3 and is used for providing 4 detection channels; the first communication circuit 12 is connected with the first singlechip control circuit 3 and is used for transmitting signals between the first singlechip control circuit 3 and an upper computer, and the first communication circuit 12 uploads digital signals to the upper computer by an RS485 protocol; the first singlechip control circuit 3 is used for receiving signals of each connecting circuit and sending signals to each connecting circuit; the single cell circuit module 2 comprises a discharge driving circuit 20, a charge driving circuit 22, a cell output interface 21, a charge and discharge control circuit 19, a second single-chip microcomputer control circuit 15, a second ADC detection circuit 16, a second channel selection circuit 18, a power supply 23 and a second communication circuit 17; the discharge driving circuit 20 is connected with the charge and discharge control circuit 19 and is used for controlling the current output within a safe range; the charging driving circuit 22 is connected with the discharging driving circuit 20 through the electric core output interface 21, and is connected with the power supply 23, and is used for receiving and storing electric quantity; the charge and discharge control circuit 19 is connected with the discharge drive circuit 20 and the charge drive circuit 22 and is used for controlling the discharge amount and the charge amount of the discharge drive circuit 20 and the charge drive circuit 22; the second ADC detection circuit 16 is connected between the discharge driving circuit 20 and the second single-chip microcomputer control circuit 15, and is configured to send the current information collected in the discharge driving circuit 20 to the second single-chip microcomputer control circuit 15; the second communication circuit 17 is connected between the first singlechip control circuit 3 and the second singlechip control circuit 15 and is used for carrying out signal transmission between the two singlechip control circuits; the second channel selection circuit 18 is connected with the second singlechip control circuit 15 and is used for providing 4 detection channels; the second single chip control circuit 15 is used for receiving signals of each connecting circuit and sending signals to each connecting circuit.

For the NTC resistor output interface 5 and the battery detection input interface 11, as shown in fig. 2, the present invention provides a specific embodiment, an internal analog resistor circuit 4 is connected to the NTC resistor interface of the battery protection board to be tested through an NTC pin and an ADC pin of P3 to simulate a change in NTC resistance value, so as to simulate a change in ambient temperature, a positive detection signal of the PACK battery is input from pin 1 of P3, and is sent to the first ADC detection circuit 10 for detection through a voltage division circuit with equal proportions of R50 and R54, and detection ends are two ends of R54.

As for the analog resistor circuit 4, as shown in fig. 3, the present invention provides a specific embodiment, the analog resistor circuit 4 includes a digital potentiometer U13, a digital potentiometer U15, and a digital potentiometer U16, each digital potentiometer has two adjustable resistors therein, CS pins and SCK pins of the three digital potentiometers are connected to the first monolithic computer control circuit 3, a data overflow pin SHDN of the digital potentiometer U13 is connected to an input pin SI of the digital potentiometer U15 to form a cascade, and the data overflow pin SHDN of the digital potentiometer U15 is connected to the input pin SI of the digital potentiometer U16 to form a cascade; the SI pin of the digital potentiometer U13 is connected with the first singlechip control circuit 3; an FB1 pin and an FW1 pin of a digital potentiometer U13 are connected to form one end of an analog resistor, a PA1 pin and a PA2 pin of U13 are connected, a PW2 pin and a PB2 pin of U13 are connected with a PW2 pin and a PB2 pin of U15, a PA2 pin and a PA1 pin of U15 are connected, a PB1 pin and a PW1 pin of U15 are connected with a PB1 pin and a PW1 pin of U16, a PA1 pin and a PA2 pin of U16 are connected, and a PB2 pin and a PW2 pin of U16 are connected to form the other end of the analog resistor. Specifically, U13, U15 and U16 are digital potentiometer chips, each chip has two adjustable resistors inside, the CS pins and SCK pins of three chips are directly controlled by the first singlechip control circuit 3, the SHDN pin of U13, i.e. the data overflow output pin, is connected to the SI pin input pin of U15 to form a cascade, the SHDN pin of U15 is connected to the SI pin of U16 to form a cascade, i.e. three ICs are connected in series, the total data input is connected to the first singlechip control circuit 3 directly at the SI pin of U13, the singlechip directly inputs data to the three chips, the singlechip directly controls the resistance values of six adjustable resistors inside the 3 chips in this way, the PB1 pin of U13 and the PW 38 pin of PW 6334 are connected together to serve as one end of an analog resistor, the PA1 pin is connected to the PA2 pin, the PA1 pin is connected to the 2 nd variable resistor inside the U13 chip in series, the PW 8 pin of U13, the PB2 pin and the PW 8 pin 2 of U15, The PB2 pin is connected in series with the 2 nd variable resistor of U15, the PA2 pin of U15 is connected in series with the PA1 pin of U15, namely, the 2 nd variable resistor in U15 and the 1 st variable resistor, the PB1 pin of U15 and the PW1 pin are connected with the PB1 pin of U16 and the PW1 pin, namely, the first variable resistor in U15 and the first variable resistor in U16 are connected in series, the 7 th pin of U16 is connected with the 8 th pin of U16, namely, the first variable resistor and the second variable resistor in U16 are connected in series, the PA1 pin of U16 and the PA2 pin are connected together to serve as the other end of the analog resistor, the above 6 analog resistors are connected in series, each resistor can be individually set by a single chip, R51, R58 and R55 are selected to be connected to the NTC 395 (namely, the NTC-pin of P3 and the NTC 1) to simulate the temperature change of the resistor.

As for the low-resistance analog circuit 7 and the resistance shift switching circuit 6, as shown in fig. 4, the present invention provides a specific embodiment, in which the low-resistance analog circuit 7 and the resistance shift switching circuit 6 include a digital potentiometer U17, a relay switch JK1, an optocoupler U17, and a triode Q9; the CS pin, the SCK pin and the SI pin of the U14 are connected with the first single-chip microcomputer control circuit 3, the JK1 is provided with two groups of switches, the PB pin of the U14 is connected with the first group of common end pins of the JK1, the PB pin and the PW pin of the U14 are connected with the second group of common end pins of the JK1, and the first group of normally open pins and the second group of normally open pins of the JK1 are connected with the NTC output interface; the optocoupler U17 is connected with the first singlechip control circuit 3 and the triode Q9, and the current flowing through the triode Q9 is induced with the coil of the JK 1.

Specifically, U14 is a digital potentiometer, the resistance of the internal variable resistor is small, and is suitable for simulating a low-resistance analog resistor, the 1 st pin and the 2 nd pin of U14 and the 3 rd pin are directly controlled by the first singlechip control circuit 3, the singlechip can set the resistance of the internal variable resistor of the chip through the three pins, the 7 th pin of U14 is connected with the first group of common terminal pins of JK1, the 5 th pin and the 6 th pin of U14 are connected with the second group of common terminal pins of JK1, the first group of normally open pins of JK1 and the second group of normally open pins of JK1 are connected in parallel to the NTC resistor output interface 5, when a low resistance is required, the singlechip can output a high level to the 2 nd pin of U17 optocoupler, the 3 rd pin and the 4 th pin of U17 are not connected, R61 pulls up the 3 rd pin potential of U17, Q9 is connected with the coil of JK1 through R64, a loop is formed by connecting the coil of JK1, the first group of pull-in turn-on switch and the second group of pull-on switch, the on-chip resistance of U14 is connected in parallel to the NTC resistive output interface 5,

3, 4 of P3, supra.

As for the standby current input interface and the standby current detection gear switching circuit 8, as shown in fig. 5, the present invention provides a specific embodiment, the standby current is input by the first pin of P2, and is output by the 2 nd pin of P2 after passing through the internal standby current detection gear switching circuit 8 and the sampling resistor, the standby current is output from the common terminal to the 2 nd pin of P2 through the normally closed contacts of P2 interface pins 1 to JK4 through the internal switch, and this state is a non-detection state, when the standby current needs to be detected, the mcu outputs a high level to U20 to make the output terminal of U20 not conductive, but the voltage of the output terminal is pulled up by R75, Q11 is turned on through R77, and forms a loop with the coil of JK4, the normally closed pin is turned off, the standby current flows to one end of R67 and C53 and R66 and C52 through F1 and is connected to the R52 of the first ADC detection circuit 10, and similarly, the microcontroller controls the pull-off of JK2, the switching through the JK2 can be selected to be that current sampling is carried out through one of R67 or R66 sampling resistors to realize the function of gear switching, a common pin of the JK2 is connected to one end of R56 of the first ADC detection circuit 10 for detection, then standby current passes through a normally open end of the JK3, a single chip microcomputer is needed to control U24 to pull in the JK3 when the standby current is measured, and therefore static current can return to a 2-pin interface of the P2 from the common pin of the JK3 through an internal switch of the JK 3.

For the first ADC detection circuit 10, as shown in fig. 6, the present invention provides a specific embodiment, standby current is input from R52 and R56, filtered by C43, C47 and C50, and input to the 6 th pin and 7 th pin channel 2 of the ADC chip for detection, and divided PACK battery input signal is input through R53 and R57, filtered by C44, C48 and C51, and input to the 7 th pin and 8 th pin of the ADC chip for detection.

As for the first single chip microcomputer control circuit 3 and the first channel selection circuit 13, as shown in fig. 7, the present invention provides a specific embodiment, the first channel selection circuit includes a dial switch S1 and 4 resistors, the 4 resistors are respectively connected with each pin of the dial switch S1, each module address is distinguished by dialing the dial switch S1, and the registers are matched with the resistors R88-R94 to send a level signal to the single chip microcomputer, so that the single chip microcomputer reads a channel number, the single chip microcomputer in the first single chip microcomputer control circuit 3 is used as a control core here, not only all the circuits described above are controlled, but also the circuits are communicated with 4 cell boards through a serial port 2, voltage and current data of the 4 cell circuits are read, and voltages and overcharge points of the 4 cell circuits are set, data are internally integrated, and the data are uniformly sent to an upper computer after the upper computer sends a request read command, after the upper computer sends a setting command, the main control board single chip microcomputer performs unified allocation.

For the first communication circuit 12, as shown in fig. 8, the invention provides a specific embodiment, the single chip microcomputer sends the input signal through the emitter of Q14 to the optocoupler U23 for isolation and sending to the 6-pin output of U23 to control the base of Q13, the output signal is then sent to the U21 through the collector of Q13 and the 2-pin and 3-pin of U21, and through level signal conversion, the output is converted into an AB differential signal and sent to the upper computer software at the PC end, when the upper computer software sends data, the AB differential signal is converted into a TTL signal through U7, and the 3-pin signal output from the 1-pin of U21 to U19 is sent to the 6-pin of U19 for isolation and sending to the single chip microcomputer for reception through U19.

As for the discharge driving circuit 20, as shown in fig. 9, the present invention provides a specific embodiment, where the discharge driving circuit includes a power interface, a fuse FU1_1, a diode D2_1, a diode D3_1, a capacitor CT4_1, a capacitor C5_1, a transistor Q1_1, a transistor Q2_1, a resistor RC1_1, a resistor R3_1, a resistor R4_1, and a resistor R6_ 1;

The direct current power supply is input from IN1_1, the direct current power supply is protected by FU1_1, D3_1 is connected with the negative pole of the power supply IN parallel and is used for reverse-connection prevention protection, the voltage after filtering is input from the emitter of Q1_1 through CT1_1, CT2_1 and CT4_1 capacitors, the voltage after filtering is input from the emitter of Q1_1, R3_1 connects the base of Q1_1 with the positive pole of the power supply, the base of Q1_1 is connected with the collector of Q2_1 through R4_1, the emitter of Q2_1 is connected with the negative pole of the power supply, the base of Q2_1 is connected with the charge-discharge control circuit 19 through R6_1, the charge-discharge control circuit 19 outputs and controls the base of Q2_1, the conduction quantity between the collector and the emitter of Q2_1 can be controlled, the conduction quantity between the collector and collector of Q1_1 is indirectly controlled, thereby the voltage output of the collector of Q5_1 is controlled 573, the reverse-current prevention loop through D2_1 and D2_1, and the current is output to an OUT1_1 interface after passing through an RC1_1 current sampling resistor, and two ends of an RC1_1 are connected with a second ADC detection circuit 16 to sample current parameters.

For the charging driving circuit 22 and the charging and discharging control circuit 19, as shown in fig. 10, the charging circuit is a battery cell protection board to be tested, which inputs voltage through an OUT1_1 interface, but the voltage is higher than the voltage output by the discharging driving circuit 20, so as to start the charging circuit, otherwise, the charging circuit is in a closed state, the charging current is sampled through an RC1_1, and then the charging current is connected to a collector of a Q5_1 through a D5_1, an emitter of the Q5_1 is connected to a negative electrode of a power supply, here, Q5_1 plays a role of absorbing the charging current, the emitter of the Q4_1 controls a base of the Q5_1, a base of the Q4_1 is connected to the R13_1 to be connected to the charging and discharging control circuit 19, here, the larger the output signal of the charging and discharging control circuit 19 is, the larger the conduction amount of the Q4_1 and the Q5_1 is, the absorbed current is absorbed, the PWM signal is output by the single chip microcomputer to set the output voltage of the discharging circuit, the PWM signal is passed through the R10_1, a pi-type filter circuit composed of R11_1, R12_1, C8_1, C9_1 and C12_1, which shapes the PWM rectangular wave signal into sine wave signal, the sine wave signal is input to the 3 rd pin of U2_1A, the 1 pin of the output pin of U2_1A is connected to the 2-pin inverting input end to form a voltage follower circuit, therefore, the signal input by the pin 3 directly follows the pin 1 to be output, the output signal is divided into two paths, one path is input to the inverting input end of the pin 6 of the U2_1B through the R9_1, the R21_1, the C16_1 and the R27_1 form an output voltage sampling circuit (the R25_1 is connected to the second ADC detection circuit 16 through a signal), the output sampling voltage is connected to the non-inverting input end of the pin 5 of the U2_1B through the R19_1 connected to one end of the R27_1, and comparing with the sine wave signal input by the 6-pin inverting input terminal, and outputting a control signal to control the charging driving circuit 22. The other path is subjected to amplitude limiting through R16_1 and R20_1, and then is input to a 3-pin non-inverting input end of U4_1A through R22_1, a 1-pin output pin of U4_1A forms a negative feed circuit through the discharge drive circuit 20, and then forms an output voltage sampling circuit through R21_1, C16_1 and R27_1, and the output voltage is fed back to a2 nd pin inverting input end of U4_1A to be modulated, and a modulated signal is output from the 1 pin, so that the discharge drive circuit 20 is controlled to output accurate voltage. The circuit forms a core circuit for simulating the battery cell, and the whole charging and discharging process of the battery cell can be simulated.

For the second ADC detection circuit 16, as shown in fig. 11, the invention provides a specific embodiment, R14_1 and R17_1 are connected to two ends of the current sampling resistor RC1_1, the sampling signal is filtered by C6_1, C10_1 and C14_1, and then is input to the channel 2 of the ADC chip for conversion, the output voltage sampling signal is connected to R15_1, and is filtered by C7_1, C11_1 and C15_1, and then is input to the channel 1 of the ADC chip for conversion, and the single chip may read the data converted by the ADC chip through the SPI interface protocol.

As for the second single chip microcomputer control circuit 15 and the second channel selection circuit 18, as shown in fig. 12, the present invention provides a specific embodiment, R33_1, R34_1, R37_1, R38_1, R40_1, and R41_1 form the second channel selection circuit 18, different level signals are output to a pin of the single chip microcomputer by matching different resistors therein to distinguish different channels, and the second channel selection circuit is connected to the pin of the single chip microcomputer, and U6_1 is a single chip microcomputer and mainly functions to set an analog cell voltage by outputting a PWM signal through a 20 th pin, detect a channel number, control the second communication circuit 17 to communicate with the main control circuit module 1, and read converted charge-discharge current and voltage data by reading an ADC chip to implement overcharge, an overdischarge test and record an overcharge point and an overdischarge point, overcurrent protection, and the like.

As for the second communication circuit 17, as shown in fig. 13, the present invention provides a specific embodiment, U7_1 and U8_1 are optical couplers, where the functions are to isolate communication, and increase the anti-interference performance of the circuit, when the cell circuit module 2 is to send data to the main control circuit module 1, a 16 th pin of the monolithic chip of the cell circuit module 2 outputs a signal through one pin of U8_1, forms a loop with R36_1 to turn on or off the 3 of U8_1 through optical signal transmission inside U8_1, after a 4 th pin signal is pulled up through R35, the signal is connected to a 4 th pin of the monolithic chip of the main control circuit module 1 to receive the signal, when the main control circuit module 1 is to send data to the cell circuit module 2, the 5 th pin of the monolithic chip of the main control circuit module 1 sends data to a2 nd pin of U7_1 through internal isolation, the 3 rd pin of the data transmitted to U7_1 is output to a 15 th pin of the monolithic chip of the cell circuit module 2, thereby receiving the data transmitted from the master circuit module 1.

While the preferred embodiments of the present invention have been illustrated and described, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. The utility model provides a multichannel protection shield integrated test circuit which characterized in that: the battery cell circuit comprises a main control circuit module and a plurality of battery cell circuit modules, wherein the main control circuit module is connected with the plurality of battery cell circuit modules;

the battery detection input interface is connected with a battery;

the battery cell circuit module is used for simulating a battery cell.

2. The multi-channel protection board comprehensive test circuit as claimed in claim 1, wherein: the single battery cell circuit module comprises a discharge driving circuit, a charge driving circuit, a battery cell output interface, a charge and discharge control circuit, a second single-chip microcomputer control circuit, a second ADC detection circuit, a second channel selection circuit, a power supply and a second communication circuit;

3. The multi-channel protection board comprehensive test circuit as claimed in claim 2, wherein: the master control circuit module also comprises an analog resistance circuit, an NTC resistance output interface, a low-resistance analog circuit and a resistance gear switching circuit;

4. The multi-channel protection board comprehensive test circuit as claimed in claim 3, wherein: the analog resistor circuit comprises a digital potentiometer U13, a digital potentiometer U15 and a digital potentiometer U16, wherein each digital potentiometer is internally provided with two adjustable resistors, CS pins and SCK pins of the three digital potentiometers are connected with a first single chip microcomputer control circuit, a data overflow pin SHDN of the digital potentiometer U13 is connected with an input pin S I of the digital potentiometer U15 to form cascade connection, and a data overflow pin SHDN of the digital potentiometer U15 is connected with an input pin SI of the digital potentiometer U16 to form cascade connection; the SI pin of the digital potentiometer U13 is connected with the first singlechip control circuit; an FB1 pin and an FW1 pin of a digital potentiometer U13 are connected to form one end of an analog resistor, a PA1 pin and a PA2 pin of U13 are connected, a PW2 pin and a PB2 pin of U13 are connected with a PW2 pin and a PB2 pin of U15, a PA2 pin and a PA1 pin of U15 are connected, a PB1 pin and a PW1 pin of U15 are connected with a PB1 pin and a PW1 pin of U16, a PA1 pin and a PA2 pin of U16 are connected, and a PB2 pin and a PW2 pin of U16 are connected to form the other end of the analog resistor.

5. The multi-channel protection board comprehensive test circuit as claimed in claim 3, wherein: the low-resistance analog circuit and the resistance gear switching circuit comprise a digital potentiometer U17, a relay switch JK1, an optocoupler U17 and a triode Q9;

the CS pin, the SCK pin and the S I pin of the U14 are connected with a first single-chip microcomputer control circuit, the JK1 is provided with two groups of switches, the PB pin of the U14 is connected with the first group of common end pins of the JK1, the PB pin and the PW pin of the U14 are connected with the second group of common end pins of the JK1, and the first group of normally open pins and the second group of normally open pins of the JK1 are connected to an NTC output interface; the optocoupler U17 is connected with the first singlechip control circuit and connected with the triode Q9, and the current flowing through the triode Q9 is induced with the coil of the JK 1.

6. The multi-channel protection board comprehensive test circuit as claimed in claim 1, wherein: the first channel selection circuit comprises a dial switch S1 and a plurality of resistors, and the plurality of resistors are respectively connected with each pin of the dial switch S1.

7. The multi-channel protection board comprehensive test circuit as claimed in claim 1, wherein: the first communication circuit uploads the digital signals to an upper computer by an RS485 protocol.

8. The multi-channel protection board comprehensive test circuit as claimed in claim 2, wherein: the discharging driving circuit comprises a power interface, a fuse FU1_1, a diode D2_1, a diode D3_1, a capacitor CT4_1, a capacitor C5_1, a triode Q1_1, a triode Q2_1, a resistor RC1_1, a resistor R3_1, a resistor R4_1 and a resistor R6_ 1;