CN111668366B - Top electrode contact of magnetic random access memory and preparation method thereof - Google Patents
Top electrode contact of magnetic random access memory and preparation method thereof Download PDFInfo
- Publication number
- CN111668366B CN111668366B CN201910172475.1A CN201910172475A CN111668366B CN 111668366 B CN111668366 B CN 111668366B CN 201910172475 A CN201910172475 A CN 201910172475A CN 111668366 B CN111668366 B CN 111668366B
- Authority
- CN
- China
- Prior art keywords
- top electrode
- tunnel junction
- magnetic tunnel
- electrode contact
- dielectric
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N50/00—Galvanomagnetic devices
- H10N50/10—Magnetoresistive devices
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/161—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N50/00—Galvanomagnetic devices
- H10N50/01—Manufacture or treatment
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N50/00—Galvanomagnetic devices
- H10N50/80—Constructional details
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Mram Or Spin Memory Techniques (AREA)
- Hall/Mr Elements (AREA)
Abstract
The invention discloses a method for forming a magnetic random access memory top electrode contact, which comprises the following steps: step 1: providing a surface-polished CMOS substrate with metal through holes Vx (x is more than or equal to 1); step 2: depositing a bottom electrode, a magnetic tunnel junction and a top electrode film layer on the substrate after planarization treatment, and then preparing a magnetic tunnel junction storage unit; step 3: depositing a top electrode contact dielectric, graphically defining a top electrode contact pattern, and etching and non-Cu filling it to form a top electrode contact; step 4: and manufacturing metal bit line connection. Compared with TEV, the TEC structure in the invention has the advantages that the height is reduced, the area is increased, and the ohmic contact resistance between BL of TE is reduced, so that the improvement of the device performance is facilitated.
Description
Technical Field
The invention relates to the technical field of MRAM (magnetic random access memory), in particular to a magnetic random access memory top electrode contact and a preparation method thereof.
Background
In recent years, magnetic random access memories using magnetic tunnel junctions are considered as future solid-state nonvolatile memories, and have the characteristics of high-speed reading and writing, large capacity and low energy consumption. Ferromagnetic MTJs are typically sandwich structures with a magnetic memory layer that can change the magnetization direction to record different data; an insulating tunnel barrier layer located in the middle; and the magnetic reference layer is positioned on the other side of the tunnel barrier layer, and the magnetization direction of the magnetic reference layer is unchanged.
In order to record information in such magnetoresistive elements, a writing method based on spin momentum transfer or spin transfer torque conversion technology is proposed, and such a magnetic random access memory is called a current driven type spin transfer torque. The current-driven spin transfer torque is classified into an in-plane current-driven spin transfer torque and a vertical current-driven spin transfer torque according to the magnetization direction, and the latter has better performance. In this way, as the volume of the magnetic memory layer is reduced, the spin-polarized current that needs to be injected for a write or switching operation is also smaller. Thus, this writing method can achieve both device miniaturization and current reduction.
Meanwhile, since the switching current required for reducing the MTJ element size is also reduced, the vertical current driven spin transfer torque can be well matched with the most advanced technology node in terms of scale. It is therefore desirable to make the vertical current driven spin-torque element very small in size and with very good uniformity and minimize the impact on MTJ magnetism, and the fabrication method employed can also achieve Gao Liang rate, high accuracy, high reliability, low power consumption, and maintain a temperature coefficient suitable for good data preservation. Meanwhile, the write operation in the nonvolatile memory is based on the resistance state change, so that it is necessary to control the damage and shortening of the life of the MTJ memory device caused thereby. However, the fabrication of a small MTJ element may increase the fluctuation of MTJ resistance, so that the write voltage or current of the vertical current-driven spin-transfer torque may also fluctuate greatly, which may impair the performance of the magnetic random access memory.
In the current MRAM fabrication process, in order to achieve an effective connection between a Top Electrode (TE) and a Bit Line (BL) of a magnetic tunnel junction, a Top Electrode via (Top Electrode Via, TEV) is typically fabricated between the Top Electrode (TE) and the Bit Line (BL). Since the photolithographic process control is not very accurate when the Top Electrode Via (TEV) is fabricated, misalignment of the top electrode via with the magnetic tunnel junction stack (Overlay) will occur, in which case, in order to achieve sufficient contact between the Top Electrode (TE) and the Top Electrode Via (TEV), a large amount of over-etching is usually performed during etching, and even the insulating cap (Encapsulation) covering around the Magnetic Tunnel Junction (MTJ) will be removed, which will directly cause shorting of the magnetic tunnel junction reference layer to the memory layer after subsequent Cu filling. The improvement of the electrical, magnetic and yield of the Magnetic Random Access Memory (MRAM) device is very disadvantageous, and the miniaturization of the magnetic memory cell is very disadvantageous.
Patent WO 2017/155508 A1 discloses a method for manufacturing a magnetic tunnel junction, in which a top electrode is directly connected to a Bit Line (BL), however, in this method, when the Bit Line (BL) is manufactured by etching, there is a high risk that an insulating layer covering around the magnetic tunnel junction will be removed, thereby causing a short circuit of the magnetic tunnel junction from a reference layer to a memory layer, which is very unfavorable for improvement of magnetic properties, electrical properties and yield of the magnetic random access memory.
Disclosure of Invention
According to the magnetic random access memory top electrode contact and the preparation method thereof, ohmic contact between a magnetic tunnel junction Top Electrode (TE) and a bit line is realized by manufacturing a layer of non-Cu Top Electrode Contact (TEC) between the TE and the BL. The method comprises the following steps: firstly, after etching a magnetic tunnel junction and a bottom electrode thereof and depositing an insulating cover layer (Encapsulation) and a dielectric between the magnetic tunnel junction layers, flattening the dielectric between the magnetic tunnel junction layers, and enabling the distance from an interface after flattening to the top of TE to be d (d can be greater than zero, equal to zero or less than zero according to actual conditions); then, using a reactive ion etching (Reactive Ion Etching, RIE) process, removing the dielectric, insulating coating on top of the Top Electrode (TE), and stopping at the top of the Top Electrode (TE) or maintaining partial overetching to increase the ohmic contact area of the Top Electrode (TE) and the Top Electrode Contact (TEC); finally, filling non-Cu Top Electrode Contact (TEC) and the like, and completing the manufacture of the Top Electrode Contact (TEC).
Compared with the structure of a top electrode through hole (TEV), the height of the non-Cu Top Electrode Contact (TEC) is greatly reduced through the adjustment of a planarization process, so that the etching difficulty is reduced.
Meanwhile, when the TEC is defined and manufactured, the TEC can be manufactured into a pattern similar to the subsequent BL or a pattern similar to the MTJ but larger than the MTJ, so that the area of the TEC is effectively increased.
The invention relates to a method for forming a top electrode contact of a magnetic random access memory, which comprises the following steps:
step 1: providing a surface-polished CMOS substrate with metal through holes Vx (x is more than or equal to 1);
step 2: depositing a bottom electrode, a magnetic tunnel junction and a top electrode film layer on the substrate after planarization treatment, and then preparing a magnetic tunnel junction storage unit;
step 3: depositing a top electrode contact dielectric, graphically defining a top electrode contact pattern, and etching and non-Cu filling it to form a top electrode contact;
step 4: and manufacturing metal bit line connection.
Further, the material of the metal via hole Vx (x.gtoreq.1) may be Cu, cuN, taN, ta, ti, tiN, co, W, al, WN, ru or any combination thereof.
Specifically, the step 2 includes the following steps:
step 2.1: depositing a bottom electrode, a magnetic tunnel junction and a top electrode multilayer film; wherein the top electrode has a thickness of 20nm-100nm, ta, taN, ti, tiN, W, WN or any combination thereof is selected to achieve a better profile in the halogen plasma;
preferably, a sacrificial mask may be deposited again after the top electrode deposition, which material may be SiO 2 SiON, siCN, siC or SiN;
step 2.2: patterning to define a magnetic tunnel junction pattern, etching the top electrode, the magnetic tunnel junction and the bottom electrode, and then depositing an insulating cover layer around the magnetic tunnel junction storage unit;
the material of the insulating coating is SiON, siC, siN or SiCN, and the forming method of the insulating coating is chemical vapor deposition, atomic layer deposition or ion beam deposition;
step 2.3: depositing a magnetic tunnel junction dielectric and carrying out planarization treatment on the magnetic tunnel junction dielectric;
the dielectric being SiO 2 SiCOH or SiON; the planarization treatment adopts a chemical mechanical planarization process for treatment;
adjusting parameters of the chemical mechanical planarization process to adjust the distance d between the polished interface and the top of the top electrode;
after the planarization process, an insulating capping layer and a small amount of magnetic tunnel junction dielectric are left on top of the top electrode;
the magnetic tunnel junction dielectric and insulating cap layer on top of the top electrode is planarized until a portion of the remaining top electrode is removed.
Further, the thickness of the deposited top electrode contact dielectric is 0nm-50nm, and the forming material is SiO 2 SiON, siC, siN, siCN or any combination thereof.
Further, the step 3 includes the following steps:
3.1: depositing a top electrode contact dielectric after the chemical mechanical planarization process of the magnetic tunnel junction dielectric;
3.2: patterning to define a top electrode contact pattern and etching the top electrode contact pattern;
wherein the top electrode contact pattern may resemble a subsequent bit line pattern; but also similar but larger than the magnetic tunnel junction pattern;
the etching process in the step 3.2 adopts a reactive ion etching process, and the etching gas is selected from SF 6 、NF 3 、CF 4 、CHF 3 、CH 2 F 2 、CHF 3 、C 4 F 8 、C 4 F 6 、C 3 F 6 、C 2 F 6 、CO、CO 2 、NH 3 、N 2 、O 2 Ar or He;
the etching process in step 3.2 adopts ion beam etching process, etching gas is selected from Ne, ar, kr or Xe, and small amount of O can be added 2 And/or N 2 ；
Controlling the etching depth d' to etch away part of the residual top electrode;
after etching, removing residual organic matters and an oxide layer on the surface of the top electrode by adopting a reactive ion etching process and/or a wet etching process so as to obtain good ohmic contact;
3.3: the top electrode contacts the metal or metal nitride fill, and the fill metal or metal nitride is polished flat until the top electrode contacts the top of the dielectric;
wherein the top electrode contact metal or metal nitride is Ti, tiN, W, WN, ta, taN or Ru, and the forming method is physical vapor deposition, chemical vapor deposition, atomic layer deposition or ion beam deposition.
Further, the step 2 may further be: and depositing a bottom electrode, a magnetic tunnel junction, a top electrode film layer and a sacrificial hard mask on the substrate after the planarization treatment, and then preparing the magnetic tunnel junction memory cell.
Specifically, the step 2 includes the following steps:
2.1: depositing a bottom electrode, a magnetic tunnel junction, a top electrode multilayer film and a sacrificial mask;
wherein the top electrode has a thickness of 20nm-100nm, ta, taN, ti, tiN, W, WN or any combination thereof is selected to obtain a better profile in the halogen plasma, and the total thickness of the sacrificial mask is 20nm-150nm, which may be SiO 2 Or SiON;
2.2: patterning to define a magnetic tunnel junction pattern, etching the top electrode, the magnetic tunnel junction and the bottom electrode, and then depositing an insulating cover layer around the magnetic tunnel junction storage unit;
the insulating coating layer is SiON, siC, siN or SiCN, and the forming method is chemical vapor deposition, atomic layer deposition or ion beam deposition;
2.3: depositing a magnetic tunnel junction dielectric and carrying out planarization treatment on the magnetic tunnel junction dielectric;
the dielectric being SiO 2 SiCOH or SiON; the planarization process is realized by adopting chemical mechanical planarization process;
adjusting chemical mechanical planarization process parameters to adjust the distance d between the planarizing interface and the top of the top electrode;
after the planarization process, retaining a portion of the remaining sacrificial mask, insulating cap layer and a small amount of magnetic tunnel street dielectric on the top electrode;
after the planarization process, retaining a portion of the remaining sacrificial mask and insulating cap layer on the top electrode;
the magnetic tunnel junction dielectric and insulating cap layer on top of the top electrode is planarized until the remaining sacrificial mask is completely removed.
Specifically, the step 3 may further be: depositing a top electrode contact dielectric, patterning the top electrode contact pattern, and etching and non-Cu filling it to form a top electrode contact,
wherein the thickness of the deposited top electrode contact dielectric is 0nm-50nm, and the forming material is SiO 2 SiON, siC, siN, siCN or any combination thereof.
Specifically, the step 3 includes the following steps:
3.1: depositing a top electrode contact dielectric after the chemical mechanical planarization process of the magnetic tunnel junction dielectric;
3.2: patterning to define a top electrode contact pattern and etching the top electrode contact pattern;
wherein the top electrode contact pattern may resemble a subsequent bit line pattern, or may resemble a magnetic tunnel junction pattern but be larger than the magnetic tunnel junction pattern,
the etching process is completed in two parts;
the main etching process adopts a reactive ion etching process or an ion beam etching process;
the reactive ion etching process is adopted, and the etching gas is selected from SF 6 、NF 3 、CF 4 、CHF 3 、CH 2 F 2 、CHF 3 、C 4 F 8 、C 4 F 6 、C 3 F 6 、C 2 F 6 、CO、CO 2 、NH 3 、N 2 、O 2 Ar or He;
an ion beam etching process is adopted, etching gas is selected from Ne, ar, kr or Xe, and small amount of O can be added 2 And/or N 2 ；
Controlling the etching process parameters so that there is a small amount of sacrificial mask remaining;
after the main etching, a high C/F or CxHy/F ratio reactive ion etching process is adopted to etch the residual small amount of sacrificial mask, and the etching is stopped at the top of the top electrode;
after etching, removing residual organic matters and an oxide layer on the surface of the top electrode by adopting a reactive ion etching process and/or a wet etching process so as to obtain good ohmic contact;
3.3: the top electrode contacts the metal or metal nitride fill, and the fill metal or metal nitride is polished flat until the top electrode contacts the top of the dielectric;
wherein the top electrode contact metal or metal nitride is Ti, tiN, W, WN, ta, taN or Ru, and the forming method is physical vapor deposition, chemical vapor deposition, atomic layer deposition or ion beam deposition.
Further, the bit line interlayer dielectric is SiO 2 SiON or low dielectric constant dielectric, and a layer of SiN, siCN or SiC may be selectively deposited between depositions.
Correspondingly, the invention also discloses a magnetic random access memory top electrode contact, which is prepared by the method for forming the magnetic random access memory top electrode contact.
The implementation of the invention has the following beneficial effects:
according to the method for forming the top electrode contact of the magnetic random access memory, the insulating cover layer covering the periphery of the reference layer and the memory layer is not etched, short circuit from the reference layer to the memory layer is not caused, and improvement of magnetism, electricity and yield of the device is facilitated; compared with TEV, the TEC structure in the invention has the advantages that the height is reduced and the area is increased, so that the ohmic contact resistance between BL of TE is reduced, and the improvement of the device performance is facilitated.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic illustration of a magnetic random access memory top electrode contact and method of making the same, a CMOS substrate with metal vias Vx (x.gtoreq.1) according to a preferred embodiment of the present invention;
FIG. 2 shows a first preferred embodiment of the present invention, where bottom electrode, magnetic tunnel junction and top electrode are deposited, and memory cell is fabricated: the method specifically comprises etching, insulating cover layer and dielectric deposition, planarization and other steps;
FIG. 3 is a schematic diagram showing steps of top electrode contact fabrication in a first preferred embodiment of the present invention;
FIG. 4 illustrates the deposition of a bottom electrode, a magnetic tunnel junction, a top electrode film and a sacrificial mask, and the preparation of a memory cell in accordance with a second preferred embodiment of the present invention: the method specifically comprises etching, insulating cover layer and dielectric deposition, planarization and other steps;
FIG. 5 is a schematic diagram showing steps of top electrode contact fabrication in a second preferred embodiment of the present invention;
FIG. 6 is a top view of a magnetic random access memory top electrode contact and method of making the same, after top electrode contact pattern fabrication, in accordance with a preferred embodiment of the present invention;
FIG. 7 is a cross-sectional view of a MRAM top electrode contact and method for fabricating the same, after the bit line fabrication is completed, in accordance with a preferred embodiment of the present invention;
fig. 8 is a top view of a mram top electrode contact and method of making the same, after bit line fabrication is completed, in accordance with a preferred embodiment of the present invention.
Wherein, the reference numerals in the figures are as follows: 200-CMOS substrate with surface polished metal via Vx (x.gtoreq.1), 210-metal via Vx (x.gtoreq.1) interlayer dielectric, 220-metal via Vx (x.gtoreq.1), 310-bottom electrode, 320-magnetic tunnel junction multilayer film, 330-top electrode, 340-sacrificial mask, 410-insulating cap layer, 420-magnetic tunnel junction interlayer dielectric, 510-top electrode contact dielectric, 511-top electrode contact mask, 520-top electrode contact, 530-bit line interlayer dielectric, 540-bit line.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It will be apparent that the described embodiments are only some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
MTJ (Magnetic Tunnel Junction): a magnetic tunnel junction; STT (Spin Transfer Torque): based on spin momentum transfer or spin transfer torque; STT-MRAM (Spin Transfer Torque-Magnetic random access memory): current driven spin transfer torque; iSTT-MRAM: an in-plane spin transfer torque magnetic random access memory; pSTT-MRAM (perpendicular Spin Transfer-Torque Magnetic Random Access Memory): a vertical spin transfer torque magnetic random access memory; TDDB (Time Dependent Dielectric Breakdown): time dependent dielectric breakdown; EM (Electron Mobility): electron mobility; m (Metal): connecting wires; CMOS (Complementary Metal-Oxide-Semiconductor): a complementary metal oxide semiconductor; ion Board: ion bombardment; RIE (Reactive Ion Etching): reactive ion etching; IBE (Ion Beam Etching): ion beam etching; shadow-effect: shadow effect; PUMP-DOWN: evacuating; BE (Bottom Electrode): a bottom electrode; BEV (Bottom Electrode VIA): a bottom electrode through hole; CVD (Chemical Vapor Deposition): chemical vapor deposition; PVD (Physical Vapor Deposition): physical vapor deposition; ALD (Atomic Layer Deposition): atomic layer deposition; IBD (Iron Beam Deposition): ion beam deposition; bottom Pinned: a bottom pinning structure; top Pinned: a top pinning structure; TE (Top Electrode): a top electrode; CMP (Chemical Mechanical Planarization): chemical mechanical polishing; low-k: a low dielectric constant; HSQ (Hydrogen Silsequioxane): a hydrogen-containing silicate; MSQ (Methylsilsesquioxane): methyl silicate-containing materials; HOSP (Hybrid Organic Siloxane Polymer): an organosiloxane polymer; porous Silicate: a porous silicate; PR (Photo Resist): a photoresist; ARC (Anti-reflective Coating): an anti-reflection layer.
According to the magnetic random access memory top electrode contact and the preparation method thereof, ohmic contact between a magnetic tunnel junction Top Electrode (TE) and a bit line is realized by manufacturing a layer of non-Cu Top Electrode Contact (TEC) between the TE and the BL. The method comprises the following steps: firstly, after etching a magnetic tunnel junction and a bottom electrode thereof and depositing an insulating cover layer (Encapsulation) and a dielectric between the magnetic tunnel junction layers, flattening the dielectric between the magnetic tunnel junction layers, and enabling the distance from an interface after flattening to the top of TE to be d (d can be greater than zero, equal to zero or less than zero according to actual conditions); then, using a reactive ion etching (Reactive Ion Etching, RIE) process, removing the dielectric, insulating coating on top of the Top Electrode (TE), and stopping at the top of the Top Electrode (TE) or maintaining partial overetching to increase the ohmic contact area of the Top Electrode (TE) and the Top Electrode Contact (TEC); finally, filling non-Cu Top Electrode Contact (TEC) and the like, and completing the manufacture of the Top Electrode Contact (TEC).
Compared with the structure of a top electrode through hole (TEV), the height of the non-Cu Top Electrode Contact (TEC) is greatly reduced through the adjustment of a planarization process, so that the etching difficulty is reduced.
Meanwhile, when the TEC is defined and manufactured, the TEC can be manufactured into a pattern similar to the subsequent BL or a pattern similar to the MTJ but larger than the MTJ, so that the area of the TEC is effectively increased.
The present invention includes, but is not limited to, the fabrication of Magnetic Random Access Memory (MRAM), nor is it limited to any process sequence or flow, provided that the resulting product or device is the same or similar to the following preferred process sequence or flow, comprising the following specific steps:
step 1: providing a surface-polished CMOS substrate 200 with metal vias Vx (x.gtoreq.1), as shown in FIG. 1; wherein, the material of the metal through hole Vx (x is more than or equal to 1) 220 can be Cu, cuN, taN, ta, ti, tiN, co, W, al, WN, ru or a combination thereof and the like.
Implementing the following steps:
step 2: on the substrate 200 after the planarization process, a bottom electrode 310, a magnetic tunnel junction 320, and a top electrode film 330 are deposited, and then a Magnetic Tunnel Junction (MTJ) memory cell is fabricated, as shown in fig. 2; further, the method can be divided into the following substeps:
step 2.1: deposition of the multilayer film of bottom electrode 310, magnetic tunnel junction 320 and top electrode 330 is performed as shown in fig. 2 (a);
among them, a Bottom Electrode (BE) 310 may BE Ta, taN, ru, ti, tiN, W, WN or any combination thereof, etc.; the thickness of the material is 5 nm-80 nm, and the material can be realized by adopting chemical vapor deposition (CVD, chemical Vapor Deposition), physical vapor deposition (PVD, physical Vapor Deposition), atomic layer deposition (ALD, atomic Layer Deposition) or ion beam deposition (IBD, ion Beam Deposition) and the like; preferably, the bottom electrode 310 may be planarized after deposition to obtain optimal surface flatness prior to deposition of the magnetic tunnel junction multilayer film.
The total thickness of the Magnetic Tunnel Junction (MTJ) multilayer film 320 is 5nm to 40nm, and may be a Bottom Pinned (Bottom Pinned) structure formed by sequentially stacking a reference layer, a barrier layer, and a memory layer, or a Top Pinned (Top Pinned) structure formed by sequentially stacking a memory layer, a barrier layer, and a reference layer.
Further, the reference layer has magnetic polarization invariance,depending on whether it is an in-plane (iSTT-MRAM) or perpendicular (pSTT-MRAM) structure. The reference layer of the in-plane type (iSTT-MRAM) generally has a structure of (IrMn or PtMn)/CoFe/Ru/CoFe/CoFeB, and the total thickness thereof is preferably 10-30 nm; the reference layer of the perpendicular (pSTT-MRAM) typically has TbCoFe or [ Co/Pt ]] n /Co/Ru/[CoPt] m A buffer/seed layer such as Ta/Pt, ta/Ru/Pt, coFeB/Ta/Pt, ta/CoFeB/Pt, coFeB/Ru/Pt or CoFeB/Ta/Ru/Pt is typically required below for the Co (Ta, W, mo)/CoFeB superlattice multilayer film structure, with a preferred total reference layer thickness of 3-20 nm.
Further, the barrier layer is a non-magnetic metal oxide, preferably MgO, mgBxOy, mgAlxOy or Al 2 O 3 And the like, and the thickness thereof is 0.5nm to 3nm.
Further, the memory layer has a variable magnetic polarization, which is different depending on whether it is an in-plane (iSTT-MRAM) or a perpendicular (pSTT-MRAM) structure. The memory layer of the in-plane iSTT-MRAM is typically CoFe/CoFeB or CoFe/NiFe, and preferably has a thickness of 2nm to 6nm, and the memory layer of the perpendicular pSTT-MRAM is typically CoFeB, coFe/CoFeB, fe/CoFeB, coFeB (Ta, W, mo)/CoFeB, and preferably has a thickness of 0.8nm to 2nm.
The Top Electrode (TE) 330 has a thickness of 20nm to 100nm, and Ta, taN, ti, tiN, W, WN or any combination thereof is selected to achieve a better profile in the halogen plasma.
Preferably, a sacrificial mask is deposited again after the top electrode deposition, which may be C, siO 2 SiON, siCN, siC, siN, etc.
Step 2.2: patterning the magnetic tunnel junction pattern and etching the top electrode 330, the Magnetic Tunnel Junction (MTJ) 320 and the bottom electrode 310, and then depositing an insulating cap layer (Encapsulation) 410 around the Magnetic Tunnel Junction (MTJ) memory cell, as shown in fig. 2 (b);
the Top Electrode (TE) 310 is etched using a RIE process. Wherein the gas for etching the top electrode is mainly Cl 2 Or CF (CF) 4 Etc. The etching is followed by RIE and/or a wet process to remove the remaining polymer to transfer the pattern to the top of the magnetic tunnel junction.
Etching the magnetic tunnel junction 320 and its bottom electrode 310 by Reactive Ion Etching (RIE) and/or Ion Beam Etching (IBE);
wherein IBE mainly adopts Ne, ar, kr or Xe as ion source, and small amount of O can be added 2 And/or N 2 Etc.; RIE mainly uses CH 3 OH,CH 4 /Ar，C 2 H 5 OH,CH 3 OH/Ar or CO/NH 3 Etc. as the main etching gas.
Further, the side wall of the top electrode/magnetic tunnel junction/bottom electrode after etching is trimmed by using an IBE process to remove the side wall damage/deposition layer, wherein the gas is Ne, ar, kr or Xe, and the process parameters are strictly controlled, such as: parameters such as ion incidence angle, power, gas species and temperature, etc., so that all sidewall damage/coating can be effectively removed.
The insulating cap layer 410 is SiON, siC, siN or SiCN, etc., and is formed by Chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), ion Beam Deposition (IBD), etc.
Step 2.3: a Magnetic Tunnel Junction (MTJ) dielectric 420 is deposited and planarized as shown in fig. 2 (c) and 2 (d);
dielectric 420 is typically SiO 2 SiCOH or SiON, etc.; planarization is typically accomplished using chemical mechanical planarization (Chemical Mechanical Planarization, CMP).
The CMP process parameters are adjusted to adjust the distance (d) of the polish plane interface to the top of the Top Electrode (TE) 330.
Still further, optionally after the planarization process, an insulating cap layer 410 and a small amount of magnetic tunnel street (MTJ) dielectric 420 remain on top of the Top Electrode (TE) 330, as shown in fig. 2 (c).
Still further, optionally, a Magnetic Tunnel Junction (MTJ) dielectric 420 and insulating cap 410 on top of the Top Electrode (TE) are planarized until a portion of the remaining Top Electrode (TE) 330 is removed, as shown in fig. 2 (d).
Step 3: a Top Electrode Contact (TEC) dielectric 510 is deposited, patterned to define a top electrode contact pattern, and etched and non-Cu filled to form a Top Electrode Contact (TEC) 520, as shown in fig. 3.
Wherein the thickness of the deposited Top Electrode Contact (TEC) dielectric 510 is 0nm to 50nm, and the forming material is SiO 2 SiON, siC, siN, siCN or any combination thereof, etc.
Step 3 may be further divided into the following sub-steps:
step 3.1: after the CMP process of the Magnetic Tunnel Junction (MTJ) dielectric, a Top Electrode Contact (TEC) dielectric 510 is deposited, as shown in fig. 3 (a) and 3 (d).
Step 3.2: a Top Electrode Contact (TEC) pattern is graphically defined and etched as shown in fig. 3 (b) and 3 (e).
Wherein the Top Electrode Contact (TEC) pattern may resemble a subsequent Bit Line (BL) pattern, as shown in fig. 6 (a); but may also be similar to but larger than the Magnetic Tunnel Junction (MTJ) pattern, as in fig. 6 (b) and 6 (c). The etching process employs RIE or IBE process, and if RIE process is employed, the etching gas is selected from SF 6 、NF 3 、CF4、CHF 3 、CH 2 F 2 、CHF 3 、C 4 F 8 、C 4 F 6 、C 3 F 6 、C 2 F 6 、CO、CO 2 、NH 3 、N 2 、O 2 Ar or He, etc.; if IBE process is used, the ion source is selected from Ne, ar, kr or Xe, etc., and small amount of O can be added 2 And/or N 2 Etc. The etch depth d' is controlled such that a portion of the remaining Top Electrode (TE) 330 is etched away.
After Etching, RIE and/or Wet Etching (Wet Etching) are used to remove residual organics and oxide layer on the Top Electrode (TE) surface to obtain good ohmic contact.
Step 3.3: the top electrode contact (BEC) metal or metal nitride is filled and the filled metal or metal nitride is planarized until the Top Electrode Contacts (TEC) dielectric 510 top, as shown in fig. 3 (c) and 3 (f).
Wherein the top electrode contact (BEC) metal or metal nitride is Ti, tiN, W, WN, ta, taN or Ru, etc., and the forming method is PVD, CVD, ALD or IBD, etc.
And II, implementation:
step 2: on the planarized substrate 200, a bottom electrode 310, a magnetic tunnel junction 320, a top electrode film 330, and a sacrificial hard mask 340 are deposited, and then a Magnetic Tunnel Junction (MTJ) memory cell is fabricated, as shown in fig. 4; further, the method can be divided into the following substeps:
step 2.1: deposition of the bottom electrode 310, magnetic tunnel junction 320, top electrode 330 multilayer film and sacrificial mask 340 is performed as shown in fig. 4 (a);
among them, a Bottom Electrode (BE) 310 may BE Ta, taN, ru, ti, tiN, W, WN or any combination thereof, etc.; the thickness of the material is 5 nm-80 nm, and the material can be realized by adopting chemical vapor deposition (CVD, chemical Vapor Deposition), physical vapor deposition (PVD, physical Vapor Deposition), atomic layer deposition (ALD, atomic Layer Deposition) or ion beam deposition (IBD, ion Beam Deposition) and the like; preferably, the bottom electrode 310 may be planarized after deposition to obtain optimal surface flatness prior to deposition of the magnetic tunnel junction multilayer film.
The total thickness of the Magnetic Tunnel Junction (MTJ) multilayer film 320 is 5nm to 40nm, and may be a Bottom Pinned (Bottom Pinned) structure formed by sequentially stacking a reference layer, a barrier layer, and a memory layer, or a Top Pinned (Top Pinned) structure formed by sequentially stacking a memory layer, a barrier layer, and a reference layer.
Further, the reference layer has magnetic polarization invariance, which varies depending on whether it is an in-plane (iSTT-MRAM) or perpendicular (pSTT-MRAM) structure. The reference layer of the in-plane type (iSTT-MRAM) generally has a structure of (IrMn or PtMn)/CoFe/Ru/CoFe/CoFeB, and the total thickness thereof is preferably 10-30 nm; the reference layer of the perpendicular (pSTT-MRAM) typically has TbCoFe or [ Co/Pt ]] n /Co/Ru/[CoPt] m For (Ta, W, mo)/CoFeB superlattice multilayer film structures, a buffer/seed layer such as Ta/Pt, ta/Ru/Pt, coFeB/Ta/Pt, ta/CoFeB/Pt, coFeB/Ru/Pt or CoFeB/Ta/Ru/Pt is generally required below, with a preferred total reference layer thickness of 3-20 nm.
Further, the barrier layer is a nonmagnetic metal oxideThe substance is preferably MgO, mgBxOy, mgAlxOy or Al 2 O 3 And the like, and the thickness thereof is 0.5nm to 3nm.
Further, the memory layer has a variable magnetic polarization, which is different depending on whether it is an in-plane (iSTT-MRAM) or a perpendicular (pSTT-MRAM) structure. The memory layer of the in-plane iSTT-MRAM is typically CoFe/CoFeB or CoFe/NiFe, and preferably has a thickness of 2nm to 6nm, and the memory layer of the perpendicular pSTT-MRAM is typically CoFeB, coFe/CoFeB, fe/CoFeB, coFeB (Ta, W, mo)/CoFeB, and preferably has a thickness of 0.8nm to 2nm.
The Top Electrode (TE) 330 has a thickness of 20nm to 100nm, and Ta, taN, ti, tiN, W, WN or any combination thereof is selected to achieve a better profile in the halogen plasma.
The total thickness of the sacrificial mask 340 is 20nm to 150nm, and the material thereof may be C, siC, siN, siCN, siO 2 Or SiON.
Step 2.2: patterning the magnetic tunnel junction pattern and etching the top electrode 330, the Magnetic Tunnel Junction (MTJ) 320 and the bottom electrode, and then depositing an insulating cap layer (Encapsulation) 410 around the Magnetic Tunnel Junction (MTJ) memory cell, as shown in fig. 4 (b);
the Top Electrode (TE) 310 is etched using a RIE process. Wherein the gas for etching the top electrode is mainly Cl 2 Or CF (CF) 4 Etc. The etching is followed by RIE and/or a wet process to remove the remaining polymer to transfer the pattern to the top of the magnetic tunnel junction.
Etching the magnetic tunnel junction 320 and its bottom electrode 310 by Reactive Ion Etching (RIE) and/or Ion Beam Etching (IBE);
wherein IBE mainly adopts Ne, ar, kr or Xe as ion source, and small amount of O can be added 2 And/or N 2 Etc.; RIE mainly uses CH 3 OH,CH 4 /Ar，C 2 H 5 OH,CH 3 OH/Ar or CO/NH 3 Etc. as the main etching gas.
Further, the side wall of the top electrode/magnetic tunnel junction/bottom electrode after etching is trimmed by using an IBE process to remove the side wall damage/deposition layer, wherein the gas is Ne, ar, kr or Xe, and the process parameters are strictly controlled, such as: parameters such as ion incidence angle, power, gas species and temperature, etc., so that all sidewall damage/coating can be effectively removed.
The insulating cap layer 410 is SiON, siC, siN or SiCN, etc., and is formed by Chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), ion Beam Deposition (IBD), etc.
Step 2.3: a Magnetic Tunnel Junction (MTJ) dielectric 420 is deposited and planarized as shown in fig. 4 (c), 4 (d) and 4 (e);
dielectric 420 is typically SiO 2 SiCOH or SiON, etc.; planarization is typically accomplished using chemical mechanical planarization (Chemical Mechanical Planarization, CMP).
The CMP process parameters are adjusted to adjust the distance (d) of the polish plane interface to the top of the Top Electrode (TE) 330.
Still further, optionally after the planarization process, a portion of the remaining sacrificial mask 340, insulating cap 410 and a small amount of Magnetic Tunnel Junction (MTJ) dielectric 420 remain over Top Electrode (TE) 330, as shown in fig. 4 (c).
Still further, optionally after the planarization process, a portion of the remaining sacrificial mask 340 and insulating cap layer 410 remains over the Top Electrode (TE) 330, as shown in fig. 4 (d).
Still further, optionally, a Magnetic Tunnel Junction (MTJ) dielectric 420 and insulating cap 410 on top of the Top Electrode (TE) are planarized until the remaining sacrificial mask 340 is completely removed, as shown in fig. 4 (e).
Step 3: a Top Electrode Contact (TEC) dielectric 510 is deposited, patterned to define a top electrode contact pattern, and etched and non-Cu filled to form a Top Electrode Contact (TEC) 520, as shown in fig. 5.
Wherein the thickness of the deposited Top Electrode Contact (TEC) dielectric 510 is 0nm to 50nm, and the forming material is SiO 2 SiON, siC, siN, siCN or any combination thereof, etc.
Step 3 may be further divided into the following sub-steps:
step 3.1: after the CMP process of the Magnetic Tunnel Junction (MTJ) dielectric, a Top Electrode Contact (TEC) dielectric 510 is deposited, as shown in fig. 5 (a) and 5 (d).
Step 3.2: a Top Electrode Contact (TEC) pattern is graphically defined and etched as shown in fig. 5 (b) and 5 (e).
Wherein the Top Electrode Contact (TEC) pattern may resemble a subsequent Bit Line (BL) pattern, as shown in fig. 6 (a); but may also be similar to but larger than the Magnetic Tunnel Junction (MTJ) pattern, as in fig. 6 (b) and 6 (c).
The etching process is completed in two parts. The main etching process adopts RIE or IBE process, if the RIE process is adopted, the etching gas is selected from SF 6 、NF 3 、CF4、CHF 3 、CH 2 F 2 、CHF 3 、C 4 F 8 、C 4 F 6 、C 3 F 6 、C 2 F 6 、CO、CO 2 、NH 3 、N 2 、O 2 Ar or He, etc.; if IBE process is used, the ion source is selected from Ne, ar, kr or Xe, etc., and small amount of O can be added 2 And/or N 2 Etc. The etching process parameters are tightly controlled so that there is a small amount of sacrificial mask 340 remaining. After the main etch, the remaining small amount of sacrificial mask is etched using a RIE process with a high C/F or CxHy/F ratio, stopping the etch on top of the Top Electrode (TE) 330.
After Etching, RIE and/or Wet Etching (Wet Etching) are used to remove residual organics and oxide layer on the Top Electrode (TE) surface to obtain good ohmic contact.
Step 3.3: the top electrode contact (BEC) metal or metal nitride is filled and the filled metal or metal nitride is planarized until the Top Electrode Contacts (TEC) dielectric 510 are on top, as shown in fig. 5 (c) and 5 (f).
Wherein the top electrode contact (BEC) metal or metal nitride is Ti, tiN, W, WN, ta, taN or Ru, etc., and the forming method is PVD, CVD, ALD or IBD, etc.
Step 4: a metal Bit Line (BL) 540 connection is made as shown in fig. 7 and 8.
Wherein, the material of the Bit Line (BL) 540 is metal Cu and is provided with a Ti/TiN or Ta/TiN anti-diffusion layer; bit Line (BL) interlayer dielectric 530 is typically SiO 2 SiON or a Low-K dielectric, and may be selectively deposited with a layer of SiN, siCN, siC, or the like between depositions.
Further, the Low-k dielectric means a material having a dielectric constant (k) lower than that of silicon dioxide (k=3.9), and in particular, the Low-k material may be a hydrogen Silicate (Hydrogen Silsequioxane, HSQ, k=2.8 to 3.0), a methyl Silicate (methyl Silicate) containing si—ch3 functional groups, MSQ, k=2.5 to 2.7, a mixed organosiloxane polymer (Hybrid Organic Siloxane Polymer, HOSP) film (k=2.5) synthesized by combining a hydrogen Silicate HSQ and a methyl Silicate MSQ, a Porous SiOCH film (k=2.3 to 2.7), or an organic polymer compound such as a Porous Silicate (Porous Silicate) having an ultra-Low dielectric constant (k < 2.0) and a Porous SiOCH film having a dielectric constant (k) of 1.9.
The implementation of the invention has the following beneficial effects:
according to the method for forming the top electrode contact of the magnetic random access memory, the insulating cover layer covering the periphery of the reference layer and the memory layer is not etched, short circuit from the reference layer to the memory layer is not caused, and improvement of magnetism, electricity and yield of the device is facilitated; compared with TEV, the TEC structure in the invention has the advantages that the height is reduced and the area is increased, so that the ohmic contact resistance between BL of TE is reduced, and the improvement of the device performance is facilitated.
The foregoing description of the preferred embodiments of the invention is not intended to limit the invention to the precise form disclosed, and any such modifications, equivalents, and alternatives falling within the spirit and scope of the invention are intended to be included within the scope of the invention.
Claims (10)
1. The method for forming the top electrode contact of the magnetic random access memory is characterized by comprising the following steps of:
step 1: providing a surface-polished CMOS substrate with a metal through hole Vx, wherein x is more than or equal to 1;
step 2: depositing a bottom electrode, a magnetic tunnel junction and a top electrode film layer on the substrate after planarization treatment, and then preparing a magnetic tunnel junction storage unit;
the step 2 comprises the following steps: depositing a bottom electrode, a magnetic tunnel junction and a top electrode multilayer film; patterning to define a magnetic tunnel junction pattern, etching the top electrode, the magnetic tunnel junction and the bottom electrode, and then depositing an insulating cover layer around the magnetic tunnel junction storage unit; depositing a magnetic tunnel junction dielectric and carrying out planarization treatment on the magnetic tunnel junction dielectric; adjusting parameters of the planarization process to adjust the distance d between the abrasive surface and the top of the top electrode; after the planarization process, retaining an insulating capping layer and a small amount of magnetic tunnel junction dielectric on top of the top electrode; planarizing the magnetic tunnel junction dielectric and the insulating cap layer on top of the top electrode until a portion of the remaining top electrode is removed;
step 3: depositing a top electrode contact dielectric, graphically defining a top electrode contact pattern, and etching and non-Cu filling it to form a top electrode contact; controlling the depth d' of the top electrode contact dielectric etching, stopping over etching at the top of the top electrode or maintaining part of the top electrode to etch away part of the residual top electrode so as to increase the ohmic contact area of the top electrode and the top electrode contact;
step 4: and manufacturing metal bit line connection, wherein the metal bit line is directly connected with the top electrode contact.
2. The method of claim 1, wherein the material of the metal via Vx is Cu, cuN, taN, ta, ti, tiN, co, W, al, WN, ru or any combination thereof.
3. The method of forming a top electrode contact for a magnetic random access memory of claim 2,
the thickness of the deposited top electrode is 20nm-100nm, ta, taN, ti, tiN, W, WN or any combination thereof is selected to obtain a better etch profile in the halogen plasma;
the insulating cover layer is made of SiON, siC, siN or SiCN, and the forming method of the insulating cover layer is chemical vapor deposition, atomic layer deposition or ion beam deposition;
the magnetic tunnel junction dielectric is SiO2, siCOH or SiON; the planarization process is performed using a chemical mechanical planarization process.
4. The method of claim 1, wherein the deposited top electrode contact dielectric has a thickness of 0nm to 50nm and the forming material is SiO2, siON, siC, siN, siCN, or any combination thereof.
5. The method of forming a top electrode contact of a mram of claim 1, wherein step 3 comprises the steps of:
3.1: depositing a top electrode contact dielectric after the planarization process of the magnetic tunnel junction dielectric;
3.2: patterning to define a top electrode contact pattern and etching the top electrode contact pattern;
wherein the top electrode contact pattern is larger than the magnetic tunnel junction pattern;
the etching process in the step 3.2 adopts a reactive ion etching process, and etching gas is selected from SF6, NF3, CF4, CHF3, CH2F2, CHF3, C4F8, C4F6, C3F6, C2F6, CO2, NH3, N2, O2, ar or He;
the etching process in the step 3.2 adopts an ion beam etching process, etching gas is selected from Ne, ar, kr or Xe, and a small amount of O2 and/or N2 is added;
after etching, removing residual organic matters and an oxide layer on the surface of the top electrode by adopting a reactive ion etching process and/or a wet etching process so as to obtain good ohmic contact;
3.3: the top electrode contacts the metal or metal nitride fill, and the fill metal or metal nitride is polished flat until the top electrode contacts the top of the dielectric;
wherein the top electrode contact metal or metal nitride is Ti, tiN, W, WN, ta, taN or Ru, and the forming method is physical vapor deposition, chemical vapor deposition, atomic layer deposition or ion beam deposition.
6. The method of forming a top electrode contact of a mram of claim 1, wherein step 2 further comprises: after depositing the bottom electrode, the magnetic tunnel junction and the top electrode film layer, a sacrificial mask is also deposited before preparing the magnetic tunnel junction memory cell.
7. The method of claim 6, wherein,
the total thickness of the sacrificial mask is 20nm-150nm, and the material is C, siC, siN, siCN, siO or SiON;
after the planarization process, a portion of the remaining sacrificial mask remains on the top electrode;
the magnetic tunnel junction dielectric and insulating cap layer on top of the top electrode is planarized until the remaining sacrificial mask is completely removed.
8. The method of forming a top electrode contact of a mram of claim 7, wherein step 3 comprises the steps of:
3.1: depositing a top electrode contact dielectric after the planarization of the magnetic tunnel junction dielectric;
3.2: patterning to define a top electrode contact pattern and etching the top electrode contact pattern;
the etching process is completed in two parts;
the main etching process adopts a reactive ion etching process or an ion beam etching process;
adopting a reactive ion etching process, wherein etching gas is selected from SF6, NF3, CF4, CHF3, CH2F2, CHF3, C4F8, C4F6, C3F6, C2F6, CO2, NH3, N2, O2, ar or He;
an ion beam etching process is adopted, etching gas is selected from Ne, ar, kr or Xe, and a small amount of O2 and/or N2 is added;
controlling the etching process parameters so that there is a small amount of sacrificial mask remaining;
after the main etching, a high C/F or CxHy/F ratio reactive ion etching process is adopted to etch the residual small amount of sacrificial mask, and the etching is stopped at the top of the top electrode;
after etching, removing residual organic matters and an oxide layer on the surface of the top electrode by adopting a reactive ion etching process and/or a wet etching process so as to obtain good ohmic contact;
3.3: the top electrode contacts the metal or metal nitride fill, and the fill metal or metal nitride is polished flat until the top electrode contacts the top of the dielectric;
wherein the top electrode contact metal or metal nitride is Ti, tiN, W, WN, ta, taN or Ru, and the forming method is physical vapor deposition, chemical vapor deposition, atomic layer deposition or ion beam deposition.
9. The method of claim 1, wherein the bit line interlayer dielectric is SiO2, siON or low dielectric constant dielectric, and a layer of SiN, siCN or SiC is selectively deposited between the depositions.
10. A magnetic random access memory top electrode contact made by the method of forming a magnetic random access memory top electrode contact of any one of claims 1-9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910172475.1A CN111668366B (en) | 2019-03-07 | 2019-03-07 | Top electrode contact of magnetic random access memory and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910172475.1A CN111668366B (en) | 2019-03-07 | 2019-03-07 | Top electrode contact of magnetic random access memory and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111668366A CN111668366A (en) | 2020-09-15 |
| CN111668366B true CN111668366B (en) | 2023-10-27 |
Family
ID=72382050
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910172475.1A Active CN111668366B (en) | 2019-03-07 | 2019-03-07 | Top electrode contact of magnetic random access memory and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111668366B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012204431A (en) * | 2011-03-24 | 2012-10-22 | Toshiba Corp | Magnetic random access memory and manufacturing method thereof |
| CN105280608A (en) * | 2014-07-25 | 2016-01-27 | 爱思开海力士有限公司 | Semiconductor device with air gaps and method for fabricating the same |
| CN107492518A (en) * | 2016-06-12 | 2017-12-19 | 上海磁宇信息科技有限公司 | A kind of forming method of MTJ top electrode connecting hole |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100399436B1 (en) * | 2001-03-28 | 2003-09-29 | 주식회사 하이닉스반도체 | A Magnetic random access memory and a method for manufacturing the same |
| JP2007273504A (en) * | 2006-03-30 | 2007-10-18 | Fujitsu Ltd | Magnetoresistive effect element, magnetic head, magnetic recorder, magnetic random access memory |
| US8138562B2 (en) * | 2009-10-20 | 2012-03-20 | Magic Technologies, Inc. | Bit line preparation method in MRAM fabrication |
| US11271034B2 (en) * | 2013-05-06 | 2022-03-08 | Yimin Guo | Method of manufacturing magnetic memory devices |
| CN104733607B (en) * | 2013-12-20 | 2017-08-01 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and its manufacture method |
| KR102456674B1 (en) * | 2017-06-09 | 2022-10-20 | 삼성전자주식회사 | Magnetic memory device and method of fabricating the same |
-
2019
- 2019-03-07 CN CN201910172475.1A patent/CN111668366B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012204431A (en) * | 2011-03-24 | 2012-10-22 | Toshiba Corp | Magnetic random access memory and manufacturing method thereof |
| CN105280608A (en) * | 2014-07-25 | 2016-01-27 | 爱思开海力士有限公司 | Semiconductor device with air gaps and method for fabricating the same |
| CN107492518A (en) * | 2016-06-12 | 2017-12-19 | 上海磁宇信息科技有限公司 | A kind of forming method of MTJ top electrode connecting hole |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111668366A (en) | 2020-09-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108232009B (en) | Method for manufacturing magnetic random access memory | |
| US10937956B2 (en) | Magnetoresistive random access memory structure and method of forming the same | |
| CN109994602B (en) | Method for preparing magnetic random access memory storage unit and logic unit | |
| US11849645B2 (en) | Integrated circuit | |
| CN110112288B (en) | Method for preparing magnetic tunnel junction unit array | |
| CN108232008B (en) | Bottom electrode contact of magnetic random access memory and preparation method thereof | |
| CN109713006B (en) | Method for manufacturing magnetic random access memory cell array and peripheral circuit thereof | |
| US11723282B2 (en) | Magneto-resistive random-access memory (MRAM) devices with self-aligned top electrode via | |
| CN109713121B (en) | Method for manufacturing magnetic random access memory cell array and peripheral circuit thereof | |
| CN111613719B (en) | Method for manufacturing magnetic random access memory cell array | |
| CN109545744B (en) | Method for manufacturing magnetic random access memory unit array and peripheral circuit connecting line | |
| CN111613572A (en) | Method for preparing magnetic random access memory storage unit and peripheral circuit thereof | |
| CN108735895B (en) | Magnetic random access memory bottom electrode contact and method of forming the same | |
| US20230301197A1 (en) | Structure and method for mram devices having spacer element | |
| CN109994601B (en) | Method for manufacturing magnetic random access memory circuit connection | |
| CN109994600B (en) | Method for manufacturing magnetic random access memory | |
| CN111613571B (en) | Method for manufacturing magnetic random access memory cell array | |
| CN111384237A (en) | Semiconductor element and manufacturing method thereof | |
| CN111668366B (en) | Top electrode contact of magnetic random access memory and preparation method thereof | |
| CN111668368B (en) | Preparation method of pseudo-magnetic tunnel junction unit structure | |
| JP2023554267A (en) | Double magnetic tunnel junction device | |
| CN108735893B (en) | Bottom electrode contact of magnetic random access memory and forming method thereof | |
| CN111490151B (en) | Method for manufacturing microminiature magnetic random access memory array | |
| CN111816764B (en) | Method for preparing magnetic tunnel junction cell array | |
| CN111816763B (en) | Preparation method of magnetic tunnel junction memory array unit and peripheral circuit thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |