CN111668366A - Top electrode contact of magnetic random access memory and preparation method thereof - Google Patents

Top electrode contact of magnetic random access memory and preparation method thereof Download PDF

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CN111668366A
CN111668366A CN201910172475.1A CN201910172475A CN111668366A CN 111668366 A CN111668366 A CN 111668366A CN 201910172475 A CN201910172475 A CN 201910172475A CN 111668366 A CN111668366 A CN 111668366A
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top electrode
tunnel junction
magnetic tunnel
dielectric
electrode contact
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CN111668366B (en
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张云森
郭一民
肖荣福
陈峻
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Shanghai Ciyu Information Technologies Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/10—Magnetoresistive devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/161—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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    • H10N50/00—Galvanomagnetic devices
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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Abstract

The invention discloses a method for forming a top electrode contact of a magnetic random access memory, which comprises the following steps: step 1: providing a surface-polished CMOS substrate with a metal through hole Vx (x is more than or equal to 1); step 2: depositing a bottom electrode, a magnetic tunnel junction and a top electrode film layer on the substrate after the planarization treatment, and then preparing a magnetic tunnel junction storage unit; and step 3: depositing a top electrode contact dielectric, defining a top electrode contact pattern in a patterning mode, and etching and filling the top electrode contact pattern with non-Cu to form a top electrode contact; and 4, step 4: and manufacturing metal bit line connection. Compared with TEV, the area of the TEC structure is increased while the height is reduced, ohmic contact resistance between BL of TE is reduced, and the improvement of device performance is facilitated.

Description

Top electrode contact of magnetic random access memory and preparation method thereof
Technical Field
The invention relates to the technical field of MRAM (magnetic random Access memory), in particular to a top electrode contact of a magnetic random access memory and a preparation method thereof.
Background
In recent years, a magnetic random access memory using a magnetic tunnel junction is considered as a solid-state nonvolatile memory in the future, and has characteristics of high speed reading and writing, large capacity, and low power consumption. Ferromagnetic MTJs are typically sandwich structures with a magnetic memory layer that can change the magnetization direction to record different data; an insulating tunnel barrier layer in between; and the magnetic reference layer is positioned on the other side of the tunnel barrier layer, and the magnetization direction of the magnetic reference layer is unchanged.
In order to be able to record information in such magnetoresistive elements, it is proposed to use a writing method based on spin momentum transfer or spin transfer torque conversion technology, and such a magnetic random access memory is called a current-driven type spin transfer torque. The current-driven spin transfer torque is further classified into an in-plane current-driven spin transfer torque and a perpendicular current-driven spin transfer torque, which have better performance according to the difference in magnetization direction. In this way, as the volume of the magnetic memory layer is reduced, the smaller the spin-polarized current that needs to be injected for a write or switching operation. Therefore, this writing method can achieve both device miniaturization and current reduction.
At the same time, the perpendicular current-driven spin-transfer torque can be well matched with the most advanced technology node in terms of scale, considering that the switching current required when the size of the MTJ element is reduced is also reduced. Therefore, it is desirable to make the perpendicular current-driven spin-transfer torque element extremely small in size and excellent in uniformity and minimize the influence on the MTJ magnetic properties, and to use a manufacturing method that can achieve high yield, high accuracy, high reliability, low power consumption, and maintain a temperature coefficient suitable for good data storage. Meanwhile, the writing operation in the nonvolatile memory is based on the resistance state change, so that it is necessary to control the damage and shortening of the life of the MTJ memory device caused thereby. However, the fabrication of a small MTJ element may increase the fluctuation of the MTJ resistance, so that the write voltage or current of the perpendicular current-driven spin transfer torque may also fluctuate greatly, which may impair the performance of the magnetic random access memory.
In the current MRAM manufacturing process, in order to achieve an effective connection between a Top Electrode (Top Electrode, TE) and a Bit Line (Bit Line, BL), a Top Electrode Via (Top Electrode Via, TEV) is usually formed between the Top Electrode (TE) and the Bit Line (BL). Since the Top Electrode Via (TEV) is not precisely controlled during the fabrication of the Top Electrode Via (TEV), the top electrode via and the magnetic tunnel junction stack (Overlay) may be misaligned, in this case, in order to achieve sufficient contact between the Top Electrode (TE) and the Top Electrode Via (TEV), a large amount of over-etching is usually performed during etching, even the insulating capping layer (Encapsulation) covering around the Magnetic Tunnel Junction (MTJ) is removed, and after the subsequent Cu filling, a short circuit from the magnetic tunnel junction reference layer to the memory layer may be directly caused. It is very unfavorable for the improvement of the electricity, magnetism and yield of the Magnetic Random Access Memory (MRAM) device, and is very unfavorable for the miniaturization of the magnetic memory unit.
Patent WO 2017/155508 a1 discloses a method for fabricating a magnetic tunnel junction, in which a top electrode is directly connected to a Bit Line (BL), however, in this method, when the Bit Line (BL) is fabricated by etching, there is a high risk that an insulating layer covering the periphery of the magnetic tunnel junction will be removed, thereby causing a short circuit from a reference layer to a memory layer of the magnetic tunnel junction, which is very disadvantageous to the magnetic, electrical and yield enhancement of the magnetic random access memory.
Disclosure of Invention
According to the top electrode contact of the magnetic random access memory and the preparation method thereof, ohmic contact between a magnetic tunnel junction (TE) and a Bit Line (BL) is realized by making a layer of non-Cu Top Electrode Contact (TEC) between the TE and the BL. The method specifically comprises the following steps: firstly, after etching a magnetic tunnel junction and a bottom electrode thereof, and depositing an insulating covering layer (Encapsulation) and a magnetic tunnel junction interlayer dielectric, carrying out planarization treatment on the magnetic tunnel junction interlayer dielectric, and enabling the distance from an interface after planarization to the top of TE to be d (d can be larger than zero, equal to zero, or smaller than zero according to actual conditions); then, using Reactive Ion Etching (RIE) process to remove the dielectric on top of the Top Electrode (TE), insulating the capping layer, and stopping on top of the Top Electrode (TE) or maintaining a portion of the over-Etching to increase the ohmic contact area of the Top Electrode (TE) and the Top Electrode Contact (TEC); and finally, filling non-Cu Top Electrode Contact (TEC) and the like, and finishing the manufacture of the Top Electrode Contact (TEC).
Compared with the structure of a top electrode through hole (TEV), the height of a non-Cu Top Electrode Contact (TEC) is greatly reduced through the adjustment of a planarization process, so that the etching difficulty is reduced, and by adopting the process, an insulating covering layer (Encapsulation) covering the periphery of a reference layer and a memory layer cannot be etched, so that short circuit from the reference layer to the memory layer cannot be caused, and the improvement of the magnetism, the electricity and the yield of a device is facilitated.
Meanwhile, when the TEC is defined and manufactured, the TEC can be made into a pattern similar to the subsequent BL or a pattern similar to the MTJ but larger than the MTJ, so that the area of the TEC is effectively increased.
The invention discloses a method for forming a top electrode contact of a magnetic random access memory, which comprises the following steps:
step 1: providing a surface-polished CMOS substrate with a metal through hole Vx (x is more than or equal to 1);
step 2: depositing a bottom electrode, a magnetic tunnel junction and a top electrode film layer on the substrate after the planarization treatment, and then preparing a magnetic tunnel junction storage unit;
and step 3: depositing a top electrode contact dielectric, defining a top electrode contact pattern in a patterning mode, and etching and filling the top electrode contact pattern with non-Cu to form a top electrode contact;
and 4, step 4: and manufacturing metal bit line connection.
Further, the material of the metal via Vx (x ≧ 1) can be Cu, CuN, TaN, Ta, Ti, TiN, Co, W, Al, WN, Ru, or any combination thereof.
Specifically, the step 2 includes the following steps:
step 2.1: depositing multilayer films of the bottom electrode, the magnetic tunnel junction and the top electrode; wherein, the thickness of the top electrode is 20nm-100nm, Ta, TaN, Ti, TiN, W, WN or any combination thereof is selected to obtain a better profile in halogen plasma;
preferably, a sacrificial mask, which may be SiO as the material, may be deposited again after the top electrode deposition2SiON, SiCN, SiC or SiN;
step 2.2: the magnetic tunnel junction pattern is defined in a graphical mode, the top electrode, the magnetic tunnel junction and the bottom electrode are etched, and then an insulating covering layer is deposited on the periphery of the magnetic tunnel junction storage unit;
the insulating covering layer is made of SiON, SiC, SiN or SiCN, and the forming method of the insulating covering layer is chemical vapor deposition, atomic layer deposition or ion beam deposition;
step 2.3: depositing a magnetic tunnel junction dielectric and carrying out planarization treatment on the magnetic tunnel junction dielectric;
the dielectric is SiO2SiCOH or SiON; the planarization treatment adopts a chemical mechanical planarization process for treatment;
adjusting the parameters of the chemical mechanical planarization process to adjust the distance d between the polished interface and the top of the top electrode;
after the planarization process, an insulating cover layer and a small amount of magnetic tunnel junction dielectric are reserved on the top of the top electrode;
the magnetic tunnel junction dielectric and the insulating capping layer atop the top electrode are planarized until a portion of the remaining top electrode is removed.
Further, the top electrode contact dielectric is deposited to a thickness of 0nm to 50nm and is formed of SiO2SiON, SiC, SiN, SiCN, or any combination thereof.
Further, the step 3 comprises the following steps:
3.1: depositing a top electrode contact dielectric after a chemical mechanical planarization process of the magnetic tunnel junction dielectric;
3.2: defining a top electrode contact pattern in a graphical mode, and etching the top electrode contact pattern;
wherein the top electrode contact pattern may resemble a subsequent bit line pattern; or may be similar to but larger than the magnetic tunnel junction pattern;
the etching process in step 3.2 adopts a reactive ion etching process, and the etching gas is selected from SF6、NF3、CF4、CHF3、CH2F2、CHF3、C4F8、C4F6、C3F6、C2F6、CO、CO2、NH3、N2、O2Ar or He;
the etching process in step 3.2 adopts ion beam etching process, the etching gas is selected from Ne, Ar, Kr or Xe, and small amount of O can be added2And/or N2；
Controlling the etching depth d' to etch away part of the remaining forehead electrode;
after etching, removing residual organic matters and an oxide layer on the surface of the top electrode by adopting a reactive ion etching process and/or wet etching to obtain good ohmic contact;
3.3: the top electrode is filled with contact metal or metal nitride, and the filled metal or metal nitride is ground flat until the top electrode is contacted with the top of the dielectric;
the top electrode contact metal or metal nitride is Ti, TiN, W, WN, Ta, TaN or Ru, and the forming method is physical vapor deposition, chemical vapor deposition, atomic layer deposition or ion beam deposition.
Further, the step 2 may also be: and depositing a bottom electrode, a magnetic tunnel junction, a top electrode film layer and a sacrificial hard mask on the substrate after the planarization treatment, and then preparing the magnetic tunnel junction memory unit.
Specifically, the step 2 includes the following steps:
2.1: depositing a bottom electrode, a magnetic tunnel junction, a top electrode multilayer film and a sacrificial mask;
wherein the top electrode has a thickness of 20nm-100nm, Ta, TaN, Ti, TiN, W, WN or their arbitrary combination is selected to obtain better profile in halogen plasma, and sacrificial masking is usedThe total thickness of the mold is 20nm-150nm, and the material may be SiO2Or SiON;
2.2: the magnetic tunnel junction pattern is defined in a graphical mode, the top electrode, the magnetic tunnel junction and the bottom electrode are etched, and then an insulating covering layer is deposited around the magnetic tunnel junction storage unit;
the insulating covering layer is made of SiON, SiC, SiN or SiCN, and the forming method is chemical vapor deposition, atomic layer deposition or ion beam deposition;
2.3: depositing a magnetic tunnel junction dielectric and carrying out planarization treatment on the magnetic tunnel junction dielectric;
the dielectric is SiO2SiCOH or SiON; the planarization process is realized by adopting a chemical mechanical planarization process;
adjusting the chemical mechanical planarization process parameters to adjust the distance d between the polished interface and the top of the top electrode;
after the planarization process, a part of the remaining sacrificial mask, the insulating cover layer and a small amount of magnetic tunnel street dielectric are remained on the top electrode;
after the planarization process treatment, retaining part of the remaining sacrificial mask and the insulating cover layer on the top electrode;
the magnetic tunnel junction dielectric and insulating capping layer on top of the top electrode are planarized until the remaining sacrificial mask is completely removed.
Specifically, the step 3 may further be: depositing a top electrode contact dielectric, patterning to define a top electrode contact pattern, and etching and non-Cu filling to form a top electrode contact,
wherein the thickness of the deposited top electrode contact dielectric is 0nm-50nm, and the material for forming the top electrode contact dielectric is SiO2SiON, SiC, SiN, SiCN, or any combination thereof.
Specifically, the step 3 includes the following steps:
3.1: depositing a top electrode contact dielectric after a chemical mechanical planarization process of the magnetic tunnel junction dielectric;
3.2: defining a top electrode contact pattern in a graphical mode, and etching the top electrode contact pattern;
wherein the top electrode contact pattern may be similar to the subsequent bit line pattern, or similar to but larger than the magnetic tunnel junction pattern,
the etching process is completed by two parts;
the main etching process adopts a reactive ion etching process or an ion beam etching process;
by using reactive ion etching process, the etching gas is selected from SF6、NF3、CF4、CHF3、CH2F2、CHF3、C4F8、C4F6、C3F6、C2F6、CO、CO2、NH3、N2、O2Ar or He;
using ion beam etching process, the etching gas is selected from Ne, Ar, Kr or Xe, and small amount of O can be added2And/or N2；
Controlling the etching process parameters so that a small amount of sacrificial mask remains;
after the main etching, adopting a reactive ion etching process with a high C/F or CxHy/F ratio to etch the remaining small amount of sacrificial mask and stopping the etching at the top of the top electrode;
after etching, removing residual organic matters and an oxide layer on the surface of the top electrode by adopting a reactive ion etching process and/or a wet etching process to obtain good ohmic contact;
3.3: the top electrode is filled with contact metal or metal nitride, and the filled metal or metal nitride is ground flat until the top electrode is contacted with the top of the dielectric;
the top electrode contact metal or metal nitride is Ti, TiN, W, WN, Ta, TaN or Ru, and the forming method is physical vapor deposition, chemical vapor deposition, atomic layer deposition or ion beam deposition.
Further, the bit line interlayer dielectric is SiO2SiON or a low dielectric constant dielectric, and a layer of SiN, SiCN or SiC may be selectively deposited between depositions.
Correspondingly, the invention also discloses a top electrode contact of the magnetic random access memory, and the top electrode contact of the magnetic random access memory is prepared by the forming method of the top electrode contact of the magnetic random access memory.
The implementation of the invention has the following beneficial effects:
according to the forming method of the top electrode contact of the magnetic random access memory, the insulating covering layers covering the periphery of the reference layer and the memory layer cannot be etched, short circuit from the reference layer to the memory layer cannot be caused, and the magnetic property, the electricity property and the yield of a device can be improved; compared with TEV, the area of the TEC structure is increased while the height is reduced, so that ohmic contact resistance between TE and BL is reduced, and the improvement of device performance is facilitated.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic diagram of a top electrode contact of a magnetic random access memory and a method for making the same, a CMOS substrate with a metal via Vx (x ≧ 1) according to a preferred embodiment of the present invention;
FIG. 2 is a first preferred embodiment of the present invention, wherein the bottom electrode, the magnetic tunnel junction and the top electrode film are deposited, and the memory cell is prepared by: the method specifically comprises the steps of etching, insulating covering layer and dielectric deposition, flattening and the like;
FIG. 3 is a schematic diagram illustrating steps of top electrode contact fabrication in accordance with a first preferred embodiment of the present invention;
FIG. 4A second preferred embodiment of the present invention, bottom electrode, magnetic tunnel junction, top electrode film and sacrificial mask deposition, memory cell preparation: the method specifically comprises the steps of etching, insulating covering layer and dielectric deposition, flattening and the like;
FIG. 5 is a schematic diagram illustrating steps in the fabrication of a top electrode contact in accordance with a second preferred embodiment of the present invention;
FIG. 6 is a top view of a top electrode contact pattern for a magnetic random access memory and method for making the same, in accordance with a preferred embodiment of the present invention;
FIG. 7 is a cross-sectional view of a top electrode contact of a magnetic random access memory and a method for fabricating the same, after fabrication of a bit line, in accordance with a preferred embodiment of the present invention;
FIG. 8 is a top view of a top electrode contact of a magnetic random access memory and a method for fabricating the same, after fabrication of bit lines is completed, according to a preferred embodiment of the present invention.
Wherein, the reference numbers in the figures are: 200-CMOS substrate with polished metal via Vx (x ≧ 1), 210-interlayer dielectric of metal via Vx (x ≧ 1), 220-metal via Vx (x ≧ 1), 310-bottom electrode, 320-magnetic tunnel junction multilayer film, 330-top electrode, 340-sacrificial mask, 410-insulating capping layer, 420-interlayer dielectric of magnetic tunnel junction, 510-top electrode contact dielectric, 511-top electrode contact mask, 520-top electrode contact, 530-interlayer dielectric of bit line, 540-bit line.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
Mtj (magnetic Tunnel junction): a magnetic tunnel junction; STT (spin Transfer Torque): based on spin momentum transfer or spin transfer torque; STT-MRAM (Spin Transfer Torque-Magnetic random Access memory): a current-driven spin transfer torque; iSTT-MRAM: an in-plane spin transfer torque magnetic random access memory; pSTT-MRAM (persistent Spin Transfer-Torque Magnetic Random Access memory): a vertical spin transfer torque magnetic random access memory; tddb (time Dependent dielectric break down): a time dependent dielectric breakdown; EM (Electron mobility): electron mobility; m (Metal): connecting wires; CMOS (Complementary Metal-Oxide-Semiconductor): a complementary metal oxide semiconductor; IonBombardent: ion bombardment; rie (reactive Ion etching): etching by reactive ions; ibe (ion beametching): etching by ion beams; shadow-effect: shadow effects; PUMP-DOWN: evacuating; BE (BottomElectode): a bottom electrode; BEV (bottom Electrode VIA): a bottom electrode via; cvd (chemical vapordeposion): chemical vapor deposition; PVD (physical Vapor deposition): physical vapor deposition; ald (atomic Layer deposition): atomic layer deposition; ibd (iron Beam deposition): ion beam deposition; bottom Pinned: a bottom pinning structure; top Pinned: a top pinning structure; te (top electrode): a top electrode; CMP (chemical Mechanical planarization): chemical mechanical polishing; low-k: a low dielectric constant; hsq (hydrogen silsequioxane): a hydrogen-containing silicate; msq (methylsilsesquioxane): containing methyl silicate; HOSP (hybrid Organic Siloxane Polymer): an organosiloxane polymer; port Silicate: a porous silicate; pr (photo resist): photoresist; ARC (Anti-reflective Coating): an anti-reflective layer.
According to the top electrode contact of the magnetic random access memory and the preparation method thereof, ohmic contact between a magnetic tunnel junction (TE) and a Bit Line (BL) is realized by making a layer of non-Cu Top Electrode Contact (TEC) between the TE and the BL. The method specifically comprises the following steps: firstly, after etching a magnetic tunnel junction and a bottom electrode thereof, and depositing an insulating covering layer (Encapsulation) and a magnetic tunnel junction interlayer dielectric, carrying out planarization treatment on the magnetic tunnel junction interlayer dielectric, and enabling the distance from an interface after planarization to the top of TE to be d (d can be larger than zero, equal to zero, or smaller than zero according to actual conditions); then, using Reactive Ion Etching (RIE) process to remove the dielectric on top of the Top Electrode (TE), insulating the capping layer, and stopping on top of the Top Electrode (TE) or maintaining a portion of the over-Etching to increase the ohmic contact area of the Top Electrode (TE) and the Top Electrode Contact (TEC); and finally, filling non-Cu Top Electrode Contact (TEC) and the like, and finishing the manufacture of the Top Electrode Contact (TEC).
Compared with the structure of a top electrode through hole (TEV), the height of a non-Cu Top Electrode Contact (TEC) is greatly reduced through the adjustment of a planarization process, so that the etching difficulty is reduced, and by adopting the process, an insulating covering layer (Encapsulation) covering the periphery of a reference layer and a memory layer cannot be etched, so that short circuit from the reference layer to the memory layer cannot be caused, and the improvement of the magnetism, the electricity and the yield of a device is facilitated.
Meanwhile, when the TEC is defined and manufactured, the TEC can be made into a pattern similar to the subsequent BL or a pattern similar to the MTJ but larger than the MTJ, so that the area of the TEC is effectively increased.
The present invention includes, but is not limited to, the fabrication of Magnetic Random Access Memories (MRAMs), and is not limited to any process sequence or flow, as long as the resulting product or device is prepared by the same or similar method as that prepared by the following preferred process sequence or flow, with the following specific steps:
step 1: providing a surface-polished CMOS substrate 200 with a metal via Vx (x ≧ 1), as shown in FIG. 1; wherein, the material of the metal through hole Vx (x is more than or equal to 1)220 can be Cu, CuN, TaN, Ta, Ti, TiN, Co, W, Al, WN, Ru or the combination thereof and the like.
Implementing one step:
step 2: depositing a bottom electrode 310, a magnetic tunnel junction 320 and a top electrode film layer 330 on the substrate 200 after the planarization process, and then performing a preparation of a Magnetic Tunnel Junction (MTJ) memory cell, as shown in fig. 2; further can be divided into the following sub-steps:
step 2.1: performing the deposition of the multilayer film of the bottom electrode 310, the magnetic tunnel junction 320 and the top electrode 330, as shown in fig. 2 (a);
wherein, the Bottom Electrode metal (BE) 310 can BE Ta, TaN, Ru, Ti, TiN, W, WN, or any combination thereof; the thickness of the film is 5 nm-80 nm, and the film can be realized by Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD) or Ion Beam Deposition (IBD); preferably, the bottom electrode 310 may be planarized after its deposition to obtain optimal surface planarity prior to magnetic tunnel junction multilayer film deposition.
The total thickness of the Magnetic Tunnel Junction (MTJ) multilayer film 320 is 5nm to 40nm, and may be a Bottom Pinned (Bottom Pinned) structure in which a reference layer, a barrier layer, and a memory layer are sequentially stacked upward or a Top Pinned (Top Pinned) structure in which a memory layer, a barrier layer, and a reference layer are sequentially stacked upward.
Further, the reference layer has a magnetic polarization invariance that differs depending on whether it is an in-plane (iST-MRAM) or perpendicular (pSTT-MRAM) structure. The reference layer of in-plane (iSTT-MRAM) typically has a (IrMn or PtMn)/CoFe/Ru/CoFe/CoFeB structure with a preferred total thickness of 10-30 nm; the reference layer of the vertical type (pSTT-MRAM) typically has TbCoFe or [ Co/Pt ]]n/Co/Ru/[CoPt]mthe/Co (Ta, W, Mo)/CoFeB superlattice multilayer film structure usually needs a buffer/seed layer below, such as Ta/Pt, Ta/Ru/Pt, CoFeB/Ta/Pt, Ta/CoFeB/Pt, CoFeB/Ru/Pt or CoFeB/Ta/Ru/Pt, etc., and the total thickness of the reference layer is preferably 3-20 nm.
Further, the barrier layer is a non-magnetic metal oxide, preferably MgO, MgBxOy, MgAlxOy or Al2O3And the thickness thereof is 0.5nm to 3 nm.
Further, the memory layer has a variable magnetic polarization, which differs depending on whether it is an in-plane (iST-MRAM) or perpendicular (pSTT-MRAM) structure. The memory layer of the in-plane iSTT-MRAM is generally CoFe/CoFeB or CoFe/NiFe, and the thickness is preferably 2nm to 6nm, and the memory layer of the vertical pSTT-MRAM is generally CoFeB, CoFe/CoFeB, Fe/CoFeB, CoFeB (Ta, W, Mo)/CoFeB, and the thickness is preferably 0.8nm to 2 nm.
The Top Electrode (TE)330 has a thickness of 20nm to 100nm, and Ta, TaN, Ti, TiN, W, WN or any combination thereof is selected to obtain a better profile in the halogen plasma.
Preferably, a sacrificial mask, which may be C, SiO, is deposited again after the top electrode is deposited2SiON, SiCN, SiC or SiN.
Step 2.2: patterning the Magnetic Tunnel Junction (MTJ) pattern, etching the top electrode 330, the Magnetic Tunnel Junction (MTJ)320, and the bottom electrode 310, and then depositing an insulating capping layer (Encapsulation)410 around the Magnetic Tunnel Junction (MTJ) memory cell, as shown in fig. 2 (b);
the Top Electrode (TE)310 is etched using an RIE process. Wherein the gas for etching the top electrode is mainly Cl2Or CF4And the like. The etching is followed by RIE and/or a wet process to remove the remaining polymer to transfer the pattern to the top of the magnetic tunnel junction.
The Etching of the magnetic tunnel junction 320 and the bottom electrode 310 thereof is completed by a Reactive Ion Etching (RIE) method and/or an Ion Beam Etching (IBE) method;
wherein IBE mainly uses Ne, Ar, Kr or Xe as ion source, and small amount of O can be added2And/or N2Etc.; RIE mainly uses CH3OH,CH4/Ar，C2H5OH,CH3OH/Ar or CO/NH3Etc. as the main etching gas.
Furthermore, the IBE process is used to trim the sidewalls of the top electrode/magnetic tunnel junction/bottom electrode after etching to remove the sidewall damage/deposition layer, wherein the gas is Ne, Ar, Kr or Xe, etc., and the process parameters are strictly controlled, such as: ion incidence angle, power, gas species and temperature, so that all sidewall damage/coating can be effectively removed.
The insulating cap layer 410 is made of SiON, SiC, SiN, or SiCN, and is formed by Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), or Ion Beam Deposition (IBD).
Step 2.3: depositing a Magnetic Tunnel Junction (MTJ) dielectric 420 and planarizing it as shown in fig. 2(c) and 2 (d);
dielectric 420 is typically SiO2SiCOH or SiON, etc.; the planarization process generally employs chemical mechanical planarization (Chemical Mechanical Planarization, CMP).
The CMP process parameters are adjusted to adjust the distance (d) of the planarized interface to the top of the Top Electrode (TE) 330.
Further, optionally after the planarization process, an insulating cap layer 410 and a small amount of Magnetic Tunnel Junction (MTJ) dielectric 420 may remain on top of the Top Electrode (TE)330, as shown in fig. 2 (c).
Still further, optionally, the Magnetic Tunnel Junction (MTJ) dielectric 420 and the insulating cap layer 410 on top of the Top Electrode (TE) may be planarized until a portion of the remaining Top Electrode (TE)330 is removed, as shown in fig. 2 (d).
And step 3: a Top Electrode Contact (TEC) dielectric 510 is deposited, patterned to define a top electrode contact pattern, and etched and non-Cu filled to form a Top Electrode Contact (TEC)520 as shown in fig. 3.
Wherein the deposited Top Electrode Contact (TEC) dielectric 510 has a thickness of 0nm to 50nm and is formed of SiO2SiON, SiC, SiN, SiCN, or any combination thereof.
Step 3 can be further divided into the following sub-steps:
step 3.1: after the CMP process of the Magnetic Tunnel Junction (MTJ) dielectric, a Top Electrode Contact (TEC) dielectric 510 is deposited as shown in fig. 3(a) and 3 (d).
Step 3.2: the Top Electrode Contact (TEC) pattern is defined graphically and etched as shown in fig. 3(b) and 3 (e).
Wherein the Top Electrode Contact (TEC) pattern may resemble the subsequent Bit Line (BL) pattern, as shown in fig. 6 (a); or may be similar to but larger than the Magnetic Tunnel Junction (MTJ) pattern, as shown in fig. 6(b) and 6 (c). The etching process adopts RIE or IBE process, if RIE process is adopted, the etching gas is selected from SF6、NF3、CF4、CHF3、CH2F2、CHF3、C4F8、C4F6、C3F6、C2F6、CO、CO2、NH3、N2、O2Ar or He, etc.; such asIf IBE process is adopted, the ion source is selected from Ne, Ar, Kr or Xe, etc., and small amount of O can be added2And/or N2And the like. The etch depth d' is controlled such that a portion of the remaining top-of-the-forehead electrode (TE)330 is etched away.
After Etching, RIE and/or Wet Etching (Wet Etching) is used to remove residual organics and oxide layer on the Top Electrode (TE) surface to obtain good ohmic contact.
Step 3.3: top electrode contact (BEC) metal or metal nitride fill, and the fill metal or metal nitride is ground flat to the top of Top Electrode Contact (TEC) dielectric 510 as shown in fig. 3(c) and 3 (f).
The top electrode contact (BEC) metal or metal nitride is Ti, TiN, W, WN, Ta, TaN or Ru, etc., and the forming method is PVD, CVD, ALD or IBD, etc.
The second implementation:
step 2: depositing a bottom electrode 310, a magnetic tunnel junction 320, a top electrode film layer 330 and a sacrificial hard mask 340 on the substrate 200 after the planarization process, and then performing the preparation of a Magnetic Tunnel Junction (MTJ) memory cell, as shown in fig. 4; further can be divided into the following sub-steps:
step 2.1: performing the deposition of the bottom electrode 310, the magnetic tunnel junction 320, the top electrode 330, the multilayer film and the sacrificial mask 340, as shown in fig. 4 (a);
wherein, the Bottom Electrode metal (BE) 310 can BE Ta, TaN, Ru, Ti, TiN, W, WN, or any combination thereof; the thickness of the film is 5 nm-80 nm, and the film can be realized by Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD) or Ion Beam Deposition (IBD); preferably, the bottom electrode 310 may be planarized after its deposition to obtain optimal surface planarity prior to magnetic tunnel junction multilayer film deposition.
The total thickness of the Magnetic Tunnel Junction (MTJ) multilayer film 320 is 5nm to 40nm, and may be a Bottom Pinned (Bottom Pinned) structure in which a reference layer, a barrier layer, and a memory layer are sequentially stacked upward or a Top Pinned (Top Pinned) structure in which a memory layer, a barrier layer, and a reference layer are sequentially stacked upward.
Further, the reference layer has a magnetic polarization invariance that differs depending on whether it is an in-plane (iST-MRAM) or perpendicular (pSTT-MRAM) structure. The reference layer of in-plane (iSTT-MRAM) typically has a (IrMn or PtMn)/CoFe/Ru/CoFe/CoFeB structure with a preferred total thickness of 10-30 nm; the reference layer of the vertical type (pSTT-MRAM) typically has TbCoFe or [ Co/Pt ]]n/Co/Ru/[CoPt]mThe multilayer film structure of (Ta, W, Mo)/CoFeB superlattice usually needs a buffer/seed layer below, such as Ta/Pt, Ta/Ru/Pt, CoFeB/Ta/Pt, Ta/CoFeB/Pt, CoFeB/Ru/Pt or CoFeB/Ta/Ru/Pt, etc., and the total thickness of the reference layer is preferably 3-20 nm.
Further, the barrier layer is a non-magnetic metal oxide, preferably MgO, MgBxOy, MgAlxOy or Al2O3And the thickness thereof is 0.5nm to 3 nm.
Further, the memory layer has a variable magnetic polarization, which differs depending on whether it is an in-plane (iST-MRAM) or perpendicular (pSTT-MRAM) structure. The memory layer of the in-plane iSTT-MRAM is generally CoFe/CoFeB or CoFe/NiFe, and the thickness is preferably 2nm to 6nm, and the memory layer of the vertical pSTT-MRAM is generally CoFeB, CoFe/CoFeB, Fe/CoFeB, CoFeB (Ta, W, Mo)/CoFeB, and the thickness is preferably 0.8nm to 2 nm.
The Top Electrode (TE)330 has a thickness of 20nm to 100nm, and Ta, TaN, Ti, TiN, W, WN or any combination thereof is selected to obtain a better profile in the halogen plasma.
The sacrificial mask 340 has a total thickness of 20nm-150nm, and may be made of C, SiC, SiN, SiCN, or SiO2Or SiON.
Step 2.2: patterning the magnetic tunnel junction pattern, etching the top electrode 330, the Magnetic Tunnel Junction (MTJ)320 and the bottom electrode, and then depositing an insulating capping layer (Encapsulation)410 around the Magnetic Tunnel Junction (MTJ) memory cell, as shown in fig. 4 (b);
the Top Electrode (TE)310 is etched using an RIE process. Wherein the gas for etching the top electrode is mainly Cl2Or CF4And the like. RIE and/or wet process is used to remove after etchingThe remaining polymer is removed to allow the pattern to be transferred to the top of the magnetic tunnel junction.
The Etching of the magnetic tunnel junction 320 and the bottom electrode 310 thereof is completed by a Reactive Ion Etching (RIE) method and/or an Ion Beam Etching (IBE) method;
wherein IBE mainly uses Ne, Ar, Kr or Xe as ion source, and small amount of O can be added2And/or N2Etc.; RIE mainly uses CH3OH,CH4/Ar，C2H5OH,CH3OH/Ar or CO/NH3Etc. as the main etching gas.
Furthermore, the IBE process is used to trim the sidewalls of the top electrode/magnetic tunnel junction/bottom electrode after etching to remove the sidewall damage/deposition layer, wherein the gas is Ne, Ar, Kr or Xe, etc., and the process parameters are strictly controlled, such as: ion incidence angle, power, gas species and temperature, so that all sidewall damage/coating can be effectively removed.
The insulating cap layer 410 is made of SiON, SiC, SiN, or SiCN, and is formed by Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), or Ion Beam Deposition (IBD).
Step 2.3: depositing a Magnetic Tunnel Junction (MTJ) dielectric 420 and planarizing it as shown in fig. 4(c), 4(d), and 4 (e);
dielectric 420 is typically SiO2SiCOH or SiON, etc.; the Planarization process is generally implemented by Chemical Mechanical Planarization (CMP).
The CMP process parameters are adjusted to adjust the distance (d) of the planarized interface to the top of the Top Electrode (TE) 330.
Further, optionally after the planarization process, a portion of the remaining sacrificial mask 340, the insulating cap layer 410 and a small amount of Magnetic Tunnel Junction (MTJ) dielectric 420 remain on the Top Electrode (TE)330, as shown in fig. 4 (c).
Further, optionally after the planarization process, a portion of the remaining sacrificial mask 340 and the insulating cap layer may remain on the Top Electrode (TE)330, as shown in fig. 4(d) 410.
Further, optionally, the Magnetic Tunnel Junction (MTJ) dielectric 420 and the insulating cap layer 410 on top of the Top Electrode (TE) may be planarized until the remaining sacrificial mask 340 is completely removed, as shown in FIG. 4 (e).
And step 3: a Top Electrode Contact (TEC) dielectric 510 is deposited, patterned to define a top electrode contact pattern, and etched and non-Cu filled to form a Top Electrode Contact (TEC)520 as shown in fig. 5.
Wherein the deposited Top Electrode Contact (TEC) dielectric 510 has a thickness of 0nm to 50nm and is formed of SiO2SiON, SiC, SiN, SiCN, or any combination thereof, and the like.
Step 3 can be further divided into the following sub-steps:
step 3.1: after the CMP process of the Magnetic Tunnel Junction (MTJ) dielectric, a Top Electrode Contact (TEC) dielectric 510 is deposited as shown in fig. 5(a) and 5 (d).
Step 3.2: the Top Electrode Contact (TEC) pattern is defined graphically and etched as shown in fig. 5(b) and 5 (e).
Wherein the Top Electrode Contact (TEC) pattern may resemble the subsequent Bit Line (BL) pattern, as shown in fig. 6 (a); or may be similar to but larger than the Magnetic Tunnel Junction (MTJ) pattern, as shown in fig. 6(b) and 6 (c).
The etching process is completed in two parts. The main etching process adopts RIE or IBE process, if RIE process is adopted, the etching gas is selected from SF6、NF3、CF4、CHF3、CH2F2、CHF3、C4F8、C4F6、C3F6、C2F6、CO、CO2、NH3、N2、O2Ar or He, etc.; if IBE process is used, the ion source is selected from Ne, Ar, Kr or Xe, etc., and small amount of O may be added2And/or N2And the like. The etch process parameters are tightly controlled so that a small amount of sacrificial mask 340 remains. After the main etch, a high C/F or CxHy/F ratio RIE process is used to etch the remaining small amount of sacrificial maskThe line etch stops on top of the Top Electrode (TE) 330.
After Etching, RIE and/or Wet Etching (Wet Etching) is used to remove residual organics and oxide layer on the Top Electrode (TE) surface to obtain good ohmic contact.
Step 3.3: top electrode contact (BEC) metal or metal nitride fill, and the fill metal or metal nitride is ground flat to the top of Top Electrode Contact (TEC) dielectric 510 as shown in fig. 5(c) and 5 (f).
The top electrode contact (BEC) metal or metal nitride is Ti, TiN, W, WN, Ta, TaN or Ru, etc., and the forming method is PVD, CVD, ALD or IBD, etc.
And 4, step 4: metal Bit Line (BL)540 connections are made as shown in fig. 7 and 8.
Wherein, the Bit Line (BL)540 is made of metal Cu and is provided with a Ti/TiN or Ta/TiN anti-diffusion layer; the Bit Line (BL) interlayer dielectric 530 is typically SiO2SiON or a second dielectric constant (Low-K) dielectric, and a layer of SiN, SiCN or SiC, etc. may be selectively deposited between depositions.
Further, the Low dielectric constant (Low-k) dielectric refers to a material having a dielectric constant (k) lower than that of silicon dioxide (k ═ 3.9), and in the specific implementation, the Low-k material may be a Hydrogen Silicate (HSQ, k ═ 2.8 to 3.0), a mixed organosilicone Polymer (HOSP) film (k ═ 2.5) synthesized by using a Hydrogen Silicate (HSQ) containing a Si-CH3 functional group and a methyl Silicate (MSQ, k ═ 2.5 to 2.7), a Porous SiOCH film (k ═ 2.3 to 2.7), or even a Porous Polymer (CH) film (k ═ 1.9) and an Organic high molecular compound such as a Porous Silicate having an ultra-Low dielectric constant (k < 2.0).
The implementation of the invention has the following beneficial effects:
according to the forming method of the top electrode contact of the magnetic random access memory, the insulating covering layers covering the periphery of the reference layer and the memory layer cannot be etched, short circuit from the reference layer to the memory layer cannot be caused, and the magnetic property, the electricity property and the yield of a device can be improved; compared with TEV, the area of the TEC structure is increased while the height is reduced, so that ohmic contact resistance between TE and BL is reduced, and the improvement of device performance is facilitated.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.

Claims (11)

1. A method for forming a top electrode contact of a magnetic random access memory is characterized by comprising the following steps:
step 1: providing a surface-polished CMOS substrate with a metal through hole Vx (x is more than or equal to 1);
step 2: depositing a bottom electrode, a magnetic tunnel junction and a top electrode film layer on the substrate after the planarization treatment, and then preparing a magnetic tunnel junction storage unit;
and step 3: depositing a top electrode contact dielectric, defining a top electrode contact pattern in a patterning mode, and etching and filling the top electrode contact pattern with non-Cu to form a top electrode contact;
and 4, step 4: and manufacturing metal bit line connection.
2. The method of claim 1, wherein the material of the metal via Vx (x ≧ 1) is Cu, CuN, TaN, Ta, Ti, TiN, Co, W, Al, WN, Ru, or any combination thereof.
3. The method of claim 2, wherein the step 2 comprises the steps of:
step 2.1: depositing multilayer films of the bottom electrode, the magnetic tunnel junction and the top electrode; wherein, the thickness of the top electrode is 20nm-100nm, Ta, TaN, Ti, TiN, W, WN or any combination thereof is selected to obtain a better profile in halogen plasma;
preferably, a sacrificial mask, which may be C, SiO, may be deposited again after the top electrode is deposited2SiON, SiCN, SiC or SiN;
step 2.2: the magnetic tunnel junction pattern is defined in a graphical mode, the top electrode, the magnetic tunnel junction and the bottom electrode are etched, and then an insulating covering layer is deposited on the periphery of the magnetic tunnel junction storage unit;
the insulating covering layer is made of SiON, SiC, SiN or SiCN, and the forming method of the insulating covering layer is chemical vapor deposition, atomic layer deposition or ion beam deposition;
step 2.3: depositing a magnetic tunnel junction dielectric and carrying out planarization treatment on the magnetic tunnel junction dielectric;
the dielectric is SiO2SiCOH or SiON; the planarization treatment adopts a chemical mechanical planarization process for treatment;
adjusting the parameters of the chemical mechanical planarization process to adjust the distance d between the polished interface and the top of the top electrode;
after the planarization process, an insulating cover layer and a small amount of magnetic tunnel junction dielectric are reserved on the top of the top electrode;
the magnetic tunnel junction dielectric and the insulating capping layer atop the top electrode are planarized until a portion of the remaining top electrode is removed.
4. The method of claim 1, wherein the top electrode contact dielectric is deposited to a thickness of 0nm to 50nm and is formed of SiO2SiON, SiC, SiN, SiCN, or any combination thereof.
5. The method of claim 1, wherein the step 3 comprises the steps of:
3.1: depositing a top electrode contact dielectric after a chemical mechanical planarization process of the magnetic tunnel junction dielectric;
3.2: defining a top electrode contact pattern in a graphical mode, and etching the top electrode contact pattern;
wherein the top electrode contact pattern may resemble a subsequent bit line pattern; or may be similar to but larger than the magnetic tunnel junction pattern;
the etching process in step 3.2 adopts a reactive ion etching process, and the etching gas is selected from SF6、NF3、CF4、CHF3、CH2F2、CHF3、C4F8、C4F6、C3F6、C2F6、CO、CO2、NH3、N2、O2Ar or He;
the etching process in step 3.2 adopts ion beam etching process, the etching gas is selected from Ne, Ar, Kr or Xe, and small amount of O can be added2And/or N2；
Controlling the etching depth d' to etch away part of the remaining forehead electrode;
after etching, removing residual organic matters and an oxide layer on the surface of the top electrode by adopting a reactive ion etching process and/or wet etching to obtain good ohmic contact;
3.3: the top electrode is filled with contact metal or metal nitride, and the filled metal or metal nitride is ground flat until the top electrode is contacted with the top of the dielectric;
the top electrode contact metal or metal nitride is Ti, TiN, W, WN, Ta, TaN or Ru, and the forming method is physical vapor deposition, chemical vapor deposition, atomic layer deposition or ion beam deposition.
6. The method of claim 1, wherein the step 2 further comprises: and depositing a bottom electrode, a magnetic tunnel junction, a top electrode film layer and a sacrificial hard mask on the substrate after the planarization treatment, and then preparing the magnetic tunnel junction memory unit.
7. The method of claim 6, wherein the step 2 comprises the steps of:
2.1: depositing a bottom electrode, a magnetic tunnel junction, a top electrode multilayer film and a sacrificial mask;
wherein the top electrode has a thickness of 20nm-100nm, Ta, TaN, Ti, TiN, W, WN or their arbitrary combination is selected to obtain better etching profile in halogen plasma, the total thickness of the sacrificial mask is 20nm-150nm, and the sacrificial mask can be C, SiC, SiN, SiCN, SiO2Or SiON;
2.2: the magnetic tunnel junction pattern is defined in a graphical mode, the top electrode, the magnetic tunnel junction and the bottom electrode are etched, and then an insulating covering layer is deposited around the magnetic tunnel junction storage unit;
the insulating covering layer is made of SiON, SiC, SiN or SiCN, and the forming method is chemical vapor deposition, atomic layer deposition or ion beam deposition;
2.3: depositing a magnetic tunnel junction dielectric and carrying out planarization treatment on the magnetic tunnel junction dielectric;
the dielectric is SiO2SiCOH or SiON; the planarization process is realized by adopting a chemical mechanical planarization process;
adjusting the chemical mechanical planarization process parameters to adjust the distance d between the polished interface and the top of the top electrode;
after the planarization process, a part of the remaining sacrificial mask, the insulating cover layer and a small amount of magnetic tunnel street dielectric are remained on the top electrode;
after the planarization process treatment, retaining part of the remaining sacrificial mask and the insulating cover layer on the top electrode;
the magnetic tunnel junction dielectric and insulating capping layer on top of the top electrode are planarized until the remaining sacrificial mask is completely removed.
8. The method of claim 7, wherein the step 3 is further performed by: depositing a top electrode contact dielectric, patterning to define a top electrode contact pattern, and etching and non-Cu filling to form a top electrode contact,
wherein a top electrode contact dielectric is depositedThe thickness of the material is 0nm-50nm, and the material for forming the material is SiO2SiON, SiC, SiN, SiCN, or any combination thereof.
9. The method of claim 8, wherein the step 3 comprises the steps of:
3.1: depositing a top electrode contact dielectric after a chemical mechanical planarization process of the magnetic tunnel junction dielectric;
3.2: defining a top electrode contact pattern in a graphical mode, and etching the top electrode contact pattern;
wherein the top electrode contact pattern may be similar to the subsequent bit line pattern, or similar to but larger than the magnetic tunnel junction pattern,
the etching process is completed by two parts;
the main etching process adopts a reactive ion etching process or an ion beam etching process;
by using reactive ion etching process, the etching gas is selected from SF6、NF3、CF4、CHF3、CH2F2、CHF3、C4F8、C4F6、C3F6、C2F6、CO、CO2、NH3、N2、O2Ar or He;
using ion beam etching process, the etching gas is selected from Ne, Ar, Kr or Xe, and small amount of O can be added2And/or N2；
Controlling the etching process parameters so that a small amount of sacrificial mask remains;
after the main etching, adopting a reactive ion etching process with a high C/F or CxHy/F ratio to etch the remaining small amount of sacrificial mask and stopping the etching at the top of the top electrode;
after etching, removing residual organic matters and an oxide layer on the surface of the top electrode by adopting a reactive ion etching process and/or a wet etching process to obtain good ohmic contact;
3.3: the top electrode is filled with contact metal or metal nitride, and the filled metal or metal nitride is ground flat until the top electrode is contacted with the top of the dielectric;
the top electrode contact metal or metal nitride is Ti, TiN, W, WN, Ta, TaN or Ru, and the forming method is physical vapor deposition, chemical vapor deposition, atomic layer deposition or ion beam deposition.
10. The method of claim 1, wherein the bit line interlayer dielectric is SiO2SiON or a low dielectric constant dielectric, and a layer of SiN, SiCN or SiC may be selectively deposited between depositions.
11. A mram top electrode contact, wherein the mram top electrode contact is made by the method of forming a mram top electrode contact of any of claims 1-10.
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