CN111653565A - 一种高阻抗半导体电阻器结构及其制备方法 - Google Patents

一种高阻抗半导体电阻器结构及其制备方法 Download PDF

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CN111653565A
CN111653565A CN202010165357.0A CN202010165357A CN111653565A CN 111653565 A CN111653565 A CN 111653565A CN 202010165357 A CN202010165357 A CN 202010165357A CN 111653565 A CN111653565 A CN 111653565A
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CN111653565B (zh
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林志东
魏鸿基
王勇
王浩
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Xiamen Sanan Integrated Circuit Co Ltd
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Abstract

本发明公开了一种高阻抗半导体电阻器结构及其制作方法，包括GaAs外延层以及设于所述GaAs外延层上的PIN结构，所述GaAs外延层包括盖层，所述PIN结构包括依次设于所述盖层之上的N型半导体层、I型半导体层和P型半导体层；所述PIN结构和所述盖层的至少部分深度注入有绝缘离子。本发明采用基于PIN结构的半导体电阻器，通过注入适量的绝缘离子对PIN结构轻微绝缘，获得高阻抗的半导体电阻器，拓宽了产品在高阻抗特性上的应用。

Description

一种高阻抗半导体电阻器结构及其制备方法
技术领域
本发明涉及半导体技术领域，尤其涉及一种高阻抗半导体电阻器结构及其制备方法。
背景技术
随着半导体器件微型化和集成化的需求，在小面积的半导体芯片中形成多个半导体功能元器件的集成电路工业经历了快速的发展。可以在半导体晶片上制造各种类型的无源电路部件，例如电阻器。半导体产品通常使用ER(EPI Resistor)、RER(Recessed EPIResistor)、TFR(Thin Film Resistor)等作为电阻器。例如，隔离pHEMT器件制作中的一部分外延区域可以用于形成电阻器。然而，单纯采用pHEMT外延结构作为半导体电阻，其阻值较低，例如由GaAs基pHEMT外延结构形成的半导体电阻，阻值仅有200Ω/sq左右，限制了部分产品在高阻抗特性上的应用。
发明内容
本发明的目的在于克服现有技术存在的不足，提供一种高阻抗半导体电阻器结构及其制备方法。
为了实现以上目的，本发明的技术方案为：
一种高阻抗半导体电阻器结构，包括GaAs外延层以及设于所述GaAs外延层上的PIN结构，所述GaAs外延层包括盖层，所述PIN结构包括依次设于所述盖层之上的N型半导体层、I型半导体层和P型半导体层；所述PIN结构和所述盖层的至少部分深度注入有绝缘离子。
可选的，所述绝缘离子的注入量为4×1011～8×1011ion/cm2。
可选的，所述GaAs外延层是GaAs基HEMT外延层，所述P型半导体层、I型半导体层和N型半导体层的材料分别为p+GaAs、i-GaAs和n+GaAs。
可选的，所述盖层包括由下至上依次设置的i-GaAs盖层和n+GaAs盖层，所述绝缘离子的注入深度为注入至n+GaAs盖层或i-GaAs盖层。
可选的，所述i-GaAs层的厚度为25-35nm，所述n+GaAs层的厚度为40-50nm。
可选的，还包括设于所述N型半导体层和所述盖层之间的蚀刻停止层，所述蚀刻停止层的材料是n+InGaP。
可选的，所述P型半导体层的厚度为40-80nm，所述I型半导体层的厚度为150-200nm，所述N型半导体层的厚度为10-50nm。
可选的，所述GaAs外延层还包括由下至上依次设置的沟道层、势垒层和阻挡层，所述盖层设于所述阻挡层之上。
可选的，所述绝缘离子包括Ar2+和He+。
上述高阻抗半导体电阻器结构的制作方法包括以下步骤：
1)提供一GaAs外延层，所述GaAs外延层包括盖层，于所述盖层上形成PIN外延层；
2)向所述PIN外延层的预设电阻器区域注入绝缘离子至所述盖层的至少部分深度；
3)蚀刻掉所述预设电阻器区域之外的PIN外延层，形成基于PIN结构的电阻器。
可选的，采用能量为15～35ekv的含能绝缘离子束对所述预设电阻器区域内的PIN外延层及盖层进行离子注入处理。
可选的，步骤2)中，于所述PIN外延层上涂布光阻，通过曝光和显影形成预设电阻器区域的遮蔽层，然后蚀刻去除所述遮蔽层之外的PIN外延层并剥离遮蔽层。
本发明的有益效果为：
采用PIN结构作为半导体电阻器，通过注入适量的绝缘离子对PIN结构以及GaAs外延层的盖层轻微绝缘，解决了传统GaAs基HEMT外延电阻阻抗低的应用限制问题，获得高阻抗的半导体电阻，拓宽了产品在高阻抗特性上的应用，同时增大了pHEMT外延的PIN结构的利用率。
附图说明
图1为实施例1的结构示意图；
图2为实施例1的工艺流程图，图中所示为各步骤形成的结构示意图；
图3为实施例2的结构示意图。
具体实施方式
以下结合附图及实施例对本发明作进一步详细说明。本发明的附图仅为示意以更容易了解本发明，其具体比例可依照设计需求进行调整。文中所描述的图形中相对元件的上下关系，在本领域技术人员应能理解是指构件的相对位置而言，因此皆可以翻转而呈现相同的构件，此皆应同属本说明书所揭露的范围。此外，图中所示的元件及结构的个数，均仅为示例，并不以此对数目进行限制，实际可依照设计需求进行调整。
实施例1
参考图1，本实施例的高阻抗半导体电阻器结构100包括GaAs基pHEMT外延层1以及设于GaAs基pHEMT外延层1上的PIN结构2。GaAs基pHEMT外延层1由下至上包括衬底11、其他例如缓冲层、成核层、沟道层等常规功能层结构(图中以省略号代替)、由AlGaAs材料形成的势垒层12、由InGaP材料形成的阻挡层13和盖层14，其中盖层14包括i-GaAs盖层141和n+GaAs盖层142。PIN结构2由下至上包括由n+InGaP材料形成的蚀刻停止层21、由n+GaAs材料形成的N型半导体层22、由i-GaAs材料形成的I型半导体层23和由p+GaAs材料形成的P型半导体层层24。
其中，势垒层12的厚度范围为7.5-10nm，阻挡层13的厚度范围为26-36nm，i-GaAs盖层141的厚度范围为25-35nm，n+GaAs盖层142的厚度范围为40-50nm；蚀刻停止层21厚度约为3.5nm，N型半导体层22厚度为10-50nm(例如30nm)，I型半导体层23厚度为150-200nm(例如185nm)，P型半导体层24厚度为40-80nm(例如60nm)。PIN结构2以及n+GaAs盖层142注入有绝缘离子Ar2+进行轻微绝缘，绝缘离子(图中以A表示)的注入量为6×1011ion/cm2。GaAs基PIN结构2与GaAs基pHEMT外延层1共同形成电阻器结构。
参考图2，上述高阻抗半导体电阻器结构的制作方法包括以下步骤：
步骤1：于GaAs基pHEMT外延层1上依次形成蚀刻停止层外延层21’、N型半导体层外延层22’、I型半导体层外延层23’和P型半导体层外延层24’形成PIN外延层2’；作为常规设置，PIN外延层2’的一部分可以规划用于静电保护；
步骤2：于PIN外延层2’上涂布IS光阻3，通过曝光、显影形成显开窗口31，显开窗口31区域作为预设电阻器区域；
步骤3：采用能量为25ekv的含能Ar2+离子束对显开窗口31内的外延层进行离子注入处理，离子注入深度包括PIN外延层2’和n+GaAs盖层142，注入量为6×1011ion/cm2，通过控制注入量实现轻微绝缘以增大电阻，然后去除IS光阻3；
步骤4：于PIN外延层2’上涂布AM光阻，并进行曝光和显影于离子注入区之上形成遮蔽层4，之外为待蚀刻区域；
步骤5：蚀刻去除遮蔽层4之外的PIN外延层2’，具体，通过干法或湿法蚀刻去除遮蔽层4之外的N型半导体层外延层22’、I型半导体层外延层23’和P型半导体层外延层24’至蚀刻停止层外延层21’，然后去除遮蔽层4之外的蚀刻停止层外延层21’，形成基于PIN结构2的pHEMT EPI电阻器。
本实施例得到的电阻器结构，其阻值范围为1000Ω/sq～2000Ω/sq范围内。
实施例2
参考图3，本实施例的高阻抗半导体电阻器结构200与实施例1的差别在于，绝缘离子(图中以A表示)的注入深度包括PIN结构2以及i-GaAs盖层141和n+GaAs盖层142，即PIN结构2和盖层14均注入绝缘离子进行轻微绝缘以获得高阻抗半导体电阻。
本实施例得到的电阻器结构，其阻值范围为1000Ω/sq～2000Ω/sq范围内。
上述实施例仅用来进一步说明本发明的一种高阻抗半导体电阻器结构及其制作方法，但本发明并不局限于实施例，凡是依据本发明的技术实质对以上实施例所作的任何简单修改、等同变化与修饰，均落入本发明技术方案的保护范围内。

Claims (12)

1.一种高阻抗半导体电阻器结构，其特征在于：包括GaAs外延层以及设于所述GaAs外延层上的PIN结构，所述GaAs外延层包括盖层，所述PIN结构包括依次设于所述盖层之上的N型半导体层、I型半导体层和P型半导体层；所述PIN结构和所述盖层的至少部分深度注入有绝缘离子。
2.根据权利要求1所述的高阻抗半导体电阻器结构，其特征在于：所述绝缘离子的注入量为4×1011～8×1011ion/cm2。
3.根据权利要求1所述的高阻抗半导体电阻器结构，其特征在于：所述GaAs外延层是GaAs基HEMT外延层，所述P型半导体层、I型半导体层和N型半导体层的材料分别为p+GaAs、i-GaAs和n+GaAs。
4.根据权利要求3所述的高阻抗半导体电阻器结构，其特征在于：所述盖层包括由下至上依次设置的i-GaAs盖层和n+GaAs盖层，所述绝缘离子的注入深度为注入至n+GaAs盖层或i-GaAs盖层。
5.根据权利要求4所述的高阻抗半导体电阻器结构，其特征在于：所述i-GaAs层的厚度为25-35nm，所述n+GaAs层的厚度为40-50nm。
6.根据权利要求4所述的高阻抗半导体电阻器结构，其特征在于：还包括设于所述N型半导体层和所述盖层之间的蚀刻停止层，所述蚀刻停止层的材料是n+InGaP。
7.根据权利要求1所述的高阻抗半导体电阻器结构，其特征在于：所述P型半导体层的厚度为40-80nm，所述I型半导体层的厚度为150-200nm，所述N型半导体层的厚度为10-50nm。
8.根据权利要求1所述的高阻抗半导体电阻器结构，其特征在于：所述GaAs外延层还包括由下至上依次设置的沟道层、势垒层和阻挡层，所述盖层设于所述阻挡层之上。
9.根据权利要求1所述的高阻抗半导体电阻器结构，其特征在于：所述绝缘离子包括Ar2 +和He+。
10.一种权利要求1～9任一项所述高阻抗半导体电阻器结构的制作方法，其特征在于包括以下步骤：
1)提供一GaAs外延层，所述GaAs外延层包括盖层，于所述盖层上形成PIN外延层；
2)向所述PIN外延层的预设电阻器区域注入绝缘离子至所述盖层的至少部分深度；
3)蚀刻掉所述预设电阻器区域之外的PIN外延层，形成基于PIN结构的电阻器。
11.根据权利要求10所述的制作方法，其特征在于：采用能量为15～35ekv的含能绝缘离子束对所述预设电阻器区域内的PIN外延层及盖层进行离子注入处理。
12.根据权利要求10所述的制作方法，其特征在于：步骤2)中，于所述PIN外延层上涂布光阻，通过曝光和显影形成预设电阻器区域的遮蔽层，然后蚀刻去除所述遮蔽层之外的PIN外延层并剥离遮蔽层。
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