CN111640670A - Method for manufacturing small-capacitance guiding rectifying tube - Google Patents
Method for manufacturing small-capacitance guiding rectifying tube Download PDFInfo
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- CN111640670A CN111640670A CN202010489856.5A CN202010489856A CN111640670A CN 111640670 A CN111640670 A CN 111640670A CN 202010489856 A CN202010489856 A CN 202010489856A CN 111640670 A CN111640670 A CN 111640670A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 238000000034 method Methods 0.000 title claims description 34
- 229910001385 heavy metal Inorganic materials 0.000 claims abstract description 4
- 239000000463 material Substances 0.000 claims abstract description 4
- 238000001259 photo etching Methods 0.000 claims description 25
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 23
- 229910052710 silicon Inorganic materials 0.000 claims description 23
- 239000010703 silicon Substances 0.000 claims description 23
- 239000010408 film Substances 0.000 claims description 21
- 230000007797 corrosion Effects 0.000 claims description 18
- 238000005260 corrosion Methods 0.000 claims description 18
- 230000000873 masking effect Effects 0.000 claims description 15
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 12
- 229910052751 metal Inorganic materials 0.000 claims description 12
- 239000002184 metal Substances 0.000 claims description 12
- 229910052760 oxygen Inorganic materials 0.000 claims description 12
- 239000001301 oxygen Substances 0.000 claims description 12
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 12
- 238000009792 diffusion process Methods 0.000 claims description 11
- 238000002955 isolation Methods 0.000 claims description 10
- 238000001465 metallisation Methods 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 9
- 239000012535 impurity Substances 0.000 claims description 9
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 8
- 229910052782 aluminium Inorganic materials 0.000 claims description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 8
- 238000003860 storage Methods 0.000 claims description 8
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 7
- 229910052698 phosphorus Inorganic materials 0.000 claims description 7
- 239000011574 phosphorus Substances 0.000 claims description 7
- 239000000126 substance Substances 0.000 claims description 7
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052796 boron Inorganic materials 0.000 claims description 6
- 238000006243 chemical reaction Methods 0.000 claims description 6
- 238000004140 cleaning Methods 0.000 claims description 6
- 238000010894 electron beam technology Methods 0.000 claims description 6
- 239000007789 gas Substances 0.000 claims description 6
- 238000002513 implantation Methods 0.000 claims description 6
- 238000005468 ion implantation Methods 0.000 claims description 6
- 229910052697 platinum Inorganic materials 0.000 claims description 6
- 239000010409 thin film Substances 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 5
- 230000008021 deposition Effects 0.000 claims description 5
- 150000002500 ions Chemical class 0.000 claims description 5
- 238000001020 plasma etching Methods 0.000 claims description 5
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 5
- 230000002441 reversible effect Effects 0.000 claims description 5
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 230000003749 cleanliness Effects 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 claims description 3
- 230000000694 effects Effects 0.000 claims description 3
- 230000007774 longterm Effects 0.000 claims description 3
- 239000002245 particle Substances 0.000 claims description 3
- 238000002161 passivation Methods 0.000 claims description 3
- 239000012495 reaction gas Substances 0.000 claims description 3
- 230000009467 reduction Effects 0.000 claims description 3
- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 239000003082 abrasive agent Substances 0.000 claims 1
- 238000001459 lithography Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- -1 PECVD deposit Chemical compound 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000001012 protector Effects 0.000 description 1
- 238000005086 pumping Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a manufacturing method of a small-capacitance guide rectifier tube, which further reduces junction capacitance by using a high-resistance epitaxial material, reducing the area of an active area of a chip and doping heavy metals. The manufacturing method of the small-capacitance guiding rectifying tube has the advantages of small area, small capacitance, strong surge current resistance, high reliability and the like, and can be widely applied to various environments and quality grade requirements.
Description
Technical Field
The invention relates to the technical field of design and manufacture of electronic element chips, in particular to a method for manufacturing a small-capacitance guide rectifying tube.
Background
At present, in the field of electronic component chips, most of ESD protection devices have the characteristic of low capacitance, and the low capacitance mainly reduces the capacitance by connecting a TVS tube and a low capacitance guide rectifier diode in series.
The purpose of reducing the capacitance is achieved by reducing the area of an active area in the manufacturing of a common low-capacitance guide diode chip, but the reduction of the area of the active area can cause the reduction of the surge current resistance, so that a guide rectifier chip which has small capacitance and can resist surge current impact is needed to improve the overall performance of an ESD protection device, and therefore, a manufacturing method of a small-capacitance guide rectifier tube is provided.
Disclosure of Invention
The present invention is directed to a method for manufacturing a small-capacitance directional rectifier tube, so as to solve the problems mentioned in the background art.
In order to achieve the purpose, the invention provides the following technical scheme: a manufacturing method of a small-capacitance guide rectifying tube is characterized in that junction capacitance is further reduced through high-resistance epitaxial materials, the area of an active area of a chip is reduced, and heavy metal doping is carried out.
Preferably, the silicon wafer cleaning method adopts a chemical reaction and a melt cleaning method to obtain a workpiece surface with high cleanliness.
Preferably, the primary oxidation is carried out in a high-temperature dry oxygen or wet oxygen atmosphere at 1100 ℃ for 160min, so that a 6500A thick silicon dioxide thin layer is formed on the surface of the silicon chip.
Preferably, the isolation stop ring is photoetched to select a photoetching plate, and an isolation stop ring window is etched on the specific thin film by adopting a method of localized light sensing and masking corrosion.
Preferably, the isolation region ion implantation implants boron high-energy ions as impurities into a silicon wafer to enable the silicon wafer to obtain a specified total amount of doped particles in a defined region, the implantation dosage is 1.0E15, the implantation energy is 80kev, the redistribution is performed in a high-temperature dry oxygen or wet oxygen atmosphere at 1050 ℃ for 150min, and the boron high-energy ions are implanted into a thin layer with junction depth of 6500A thickness.
Preferably, the main junction photolithography selects a photolithography mask, a main junction window is etched on a specific thin film by adopting a method of localized light sensing and masking corrosion, phosphorus is diffused as an impurity at 950 ℃ for 50min, and platinum is diffused as an impurity at 930 ℃ for 30 min.
Preferably, the photoetching lead hole selective photoetching plate adopts a method of localized light sensing and masking corrosion to etch lead holes on a specific thin film, the front side metallization bombards aluminum by adopting an electron beam in a vacuum environment to generate metal steam which is splashed on the front side of a silicon wafer to form a metal film with the thickness of 3 microns, and the reverse etching aluminum selective photoetching plate adopts a method of localized light sensing and masking corrosion to etch an electrode window on the specific thin film.
Preferably, the PECVD deposition is carried out for 12 +/-0.5 min at the temperature of 350 +/-5 ℃ to form a SI3N4 surface passivation film, the silicon nitride photoetching is selected from a photoetching plate, a silicon nitride protection area is etched on a specific film by adopting a method of localized light sensing and masking corrosion, the plasma etching is carried out under the radio frequency power of 70% -95% and is vacuumized to be below 0.1 torr to generate glow discharge to form plasma, so that reaction gas generates chemical active groups to carry out chemical corrosion reaction with a corroded film in a specified area to generate gas which can be taken away by gas flow, and the effect of dry etching is achieved.
Preferably, the back side thinning thins the silicon wafer to 220 μm ± 10 μm using a prescribed abrasive, the back side metallization bombards the Ti/Ni/Ag with an electron beam in a vacuum environment, generating a metal vapor sputter on the front side of the silicon wafer, forming a metal film of Ti/Ni/Ag =1150 a/2000 a/18000 a.
Preferably, the chip storage places the produced chip in a suitable environment for long-term storage.
Compared with the prior art, the invention has the following beneficial effects: the manufacturing method of the small-capacitance guiding rectifying tube has the advantages of small chip area, small capacitance, strong surge current resistance, high reliability and the like, can be widely applied to various small-capacitance high-power single-circuit or multi-circuit mode ESD protectors, and has performance parameters equivalent to or even better than those of most of foreign related products.
Drawings
FIG. 1 is a schematic diagram of a longitudinal cross-section of a small-capacitance directional rectifier tube according to the present invention.
FIG. 2 is a schematic diagram of a photolithography mask for a small-capacitance guided rectifier device according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1-2, the present invention provides a technical solution: a kind of ESD device structure design and manufacturing technique, the said manufacturing approach further reduces the junction capacitance through the high-resistance epitaxial material, reducing chip active area and heavy metal doping, the said manufacturing approach includes the following steps, the silicon chip is washed, oxidized once, isolate the stop ring photoengraving, isolate the ion implantation, redistribute, main junction photoengraving, phosphorus diffusion, platinum diffusion, photoengraving the pin hole, front metallization, reverse etching aluminium, PECVD deposit, silicon nitride photoengraving, plasma etching, back attenuate, back metallization and chip storage;
the manufacturing process mainly comprises the following seventeen steps:
the first step is as follows: silicon wafer cleaning
The method adopts chemical reaction and fusion washing to obtain the workpiece surface with high cleanliness.
The second step is that: first oxidation
And (3) forming a 6500A thick silicon dioxide thin layer on the surface of the silicon chip in a high-temperature dry oxygen or wet oxygen atmosphere at 1100 ℃ for 160 min.
The third step: isolated stop ring lithography
Selecting the photoetching sleeve plate shown in FIG. 2, and etching an isolation stop ring window on a specific film by adopting a method of localized light sensing and corrosion masking.
The fourth step: isolation region ion implantation
Boron high-energy ions are implanted into the silicon wafer as impurities to ensure that the silicon wafer obtains a specified total amount of doped particles in a limited area, the implantation dosage is 1.0E15, and the implantation energy is 80 kev.
The fifth step: redistribution of the components
And (3) implanting boron high-energy ions into a thin layer with junction depth of 6500A thickness in a high-temperature dry oxygen or wet oxygen atmosphere at 1050 ℃ for 150 min.
And a sixth step: main junction lithography
Selecting the photoetching sleeve plate shown in FIG. 2, and etching a main junction window on a specific film by adopting a method of localized light sensing and corrosion masking.
The seventh step: phosphorus diffusion
Taking a phosphorus source as an impurity, and performing main junction diffusion for 50min at the temperature of 950 ℃.
Eighth step: platinum diffusion
The main junction diffusion was carried out at 930 ℃ for 30min with a platinum source as an impurity.
The ninth step: photoetching lead hole
Selecting the photoetching sleeve plate in FIG. 2, and etching a lead hole on a specific film by adopting a method of localized light sensing and corrosion masking.
The tenth step: front side metallization
Bombarding aluminum by adopting electron beams in a vacuum environment, and generating metal steam which splashes on the front surface of the silicon wafer to form a metal film with the thickness of 3 mu m.
The eleventh step: reverse carving aluminum
Selecting the photoetching sleeve plate shown in FIG. 2, and etching an electrode window on a specific film by adopting a method of localized light sensing and corrosion masking.
The twelfth step: PECVD deposition
Deposition is carried out at the temperature of (350 +/-5) DEG C for 12 +/-0.5 min to form the SI3N4 surface passivation film.
The thirteenth step: silicon nitride lithography
Selecting the photoetching sleeve plate shown in FIG. 2, and etching a silicon nitride protection area on a specific film by adopting a method of localized light sensing and masking corrosion.
The fourteenth step is that: plasma etching
Under the radio frequency power of 70% -95%, vacuum pumping is carried out to below 0.1 torr, glow discharge is generated to form plasma, so that the reaction gas generates chemical active groups, and the chemical active groups and the corroded film in the specified area are subjected to chemical corrosion reaction to generate gas which can be taken away by gas flow, and the effect of dry etching is achieved.
The fifteenth step: back thinning
The silicon wafer was thinned to 220 μm. + -. 10 μm using a specified abrasive.
Sixteenth, step: back side metallization
Bombarding Ti/Ni/Ag by using an electron beam in a vacuum environment, generating metal vapor to splash on the front surface of the silicon chip, and forming a metal film of Ti/Ni/Ag = 1150A/2000A/18000A.
Seventeenth step: chip storage
The produced chips were placed in an appropriate environment for long-term storage.
To sum up, (1) low capacitance: the design and manufacturing technology can enable the capacitance to reach within 3PF, and can be used for protecting static sensitive devices in circuits such as power supplies and data transmission;
(2) high pressure: the design and manufacturing technology can enable the breakdown voltage to reach 300V, so that the application range of products is wider;
(3) the chip area is reduced: the area of the active area is reduced, so that the whole area of the chip is reduced, the capacitance can be reduced, and the subsequent packaging volume can be reduced.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (10)
1. A method for manufacturing a small-capacitance guide rectifier tube is characterized in that: the manufacturing method further reduces junction capacitance through high-resistance epitaxial materials, reduction of the area of an active area of a chip and heavy metal doping, and comprises the following steps of silicon wafer cleaning, primary oxidation, isolation stop ring photoetching, isolation area ion implantation, redistribution, main junction photoetching, phosphorus diffusion, platinum diffusion, photoetching wire holes, front metallization, reverse aluminum etching, PECVD deposition, silicon nitride photoetching, plasma etching, back thinning, back metallization and chip storage.
2. The method of claim 1, wherein the step of forming the rectifying tube comprises: the silicon wafer cleaning adopts a chemical reaction and melt cleaning method to obtain the workpiece surface with high cleanliness.
3. The method of claim 1, wherein the step of forming the rectifying tube comprises: the primary oxidation is carried out in a high-temperature dry oxygen or wet oxygen atmosphere at 1100 ℃ for 160min to form the surface of the silicon wafer
A thick thin layer of silicon dioxide.
4. The method of claim 1, wherein the step of forming the rectifying tube comprises: the isolation stop ring photoetching selective photoetching plate adopts a method of localized light sensing and masking corrosion to etch an isolation stop ring window on a specific film.
5. The method of claim 1, wherein the step of forming the rectifying tube comprises: the ion implantation of the isolation region takes boron high-energy ions as impurities to be implanted into a silicon wafer, so that the silicon wafer obtains the specified total amount of doped particles in a limited region, the implantation dosage is 1.0E15, the implantation energy is 80kev, the redistribution is carried out in a high-temperature dry oxygen or wet oxygen atmosphere at 1050 ℃, the duration is 150min, and the junction depth of the boron high-energy ion implantation is changed to
A thick thin layer.
6. The method of claim 1, wherein the step of forming the rectifying tube comprises: the main junction photoetching selects a photoetching plate, a main junction window is etched on a specific film by adopting a method of localized light sensing and masking corrosion, phosphorus is used as an impurity for main junction diffusion for 50min at the temperature of 950 ℃ by phosphorus diffusion, and platinum is used as an impurity for main junction diffusion for 30min at the temperature of 930 ℃.
7. The method of claim 1, wherein the step of forming the rectifying tube comprises: the photoetching lead hole selective photoetching plate adopts a method of localized light sensing and masking corrosion to etch lead holes on a specific thin film, the front side metallization bombards aluminum by adopting an electron beam under a vacuum environment to generate metal steam which splashes on the front side of a silicon wafer to form a metal film with the thickness of 3 mu m, and the reverse etching aluminum selective photoetching plate adopts a method of localized light sensing and masking corrosion to etch an electrode window on the specific thin film.
8. The method of claim 1, wherein the step of forming the rectifying tube comprises: the PECVD deposition is carried out for 12 +/-0.5 min at the temperature of 350 +/-5 ℃ to form a SI3N4 surface passivation film, the silicon nitride photoetching selective photoetching plate adopts a method of localized light sensing and masking corrosion to etch a silicon nitride protection area on a specific film, the plasma etching is carried out under the radio frequency power of 70-95 percent and is vacuumized to be below 0.1 torr to generate glow discharge to form plasma, so that reaction gas generates chemical active groups to carry out chemical corrosion reaction with a corroded film in a specified area to generate gas which can be taken away by gas flow, and the effect of dry etching is achieved.
9. The method of claim 1, wherein the step of forming the rectifying tube comprises: the back side thinning is realized by thinning the silicon wafer to 220 microns +/-10 microns by using a specified abrasive material, the back side metallization bombards Ti/Ni/Ag by adopting an electron beam in a vacuum environment to generate metal steam which splashes on the front side of the silicon wafer to form
The metal film of (2).
10. The method of claim 1, wherein the step of forming the rectifying tube comprises: the chip storage places the produced chip in a proper environment for long-term storage.
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| CN202010489856.5A CN111640670B (en) | 2020-06-02 | 2020-06-02 | Manufacturing method of small-capacitance guide rectifying tube |
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| CN202010489856.5A CN111640670B (en) | 2020-06-02 | 2020-06-02 | Manufacturing method of small-capacitance guide rectifying tube |
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| CN111640670B CN111640670B (en) | 2023-11-17 |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4151010A (en) * | 1978-06-30 | 1979-04-24 | International Business Machines Corporation | Forming adjacent impurity regions in a semiconductor by oxide masking |
| CN101969079A (en) * | 2009-06-01 | 2011-02-09 | Jds尤尼弗思公司 | Photodiode with high ESD threshold |
| CN102569067A (en) * | 2012-02-17 | 2012-07-11 | 北京时代民芯科技有限公司 | Method for manufacturing planar high-voltage ultrafast soft recovery diode |
| CN203351612U (en) * | 2013-08-01 | 2013-12-18 | 泰科天润半导体科技（北京）有限公司 | Schottky diode |
| CN108493108A (en) * | 2018-05-16 | 2018-09-04 | 江苏润奥电子制造股份有限公司 | A kind of manufacturing method of high-voltage high-speed soft-recovery diode |
-
2020
- 2020-06-02 CN CN202010489856.5A patent/CN111640670B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4151010A (en) * | 1978-06-30 | 1979-04-24 | International Business Machines Corporation | Forming adjacent impurity regions in a semiconductor by oxide masking |
| CN101969079A (en) * | 2009-06-01 | 2011-02-09 | Jds尤尼弗思公司 | Photodiode with high ESD threshold |
| CN102569067A (en) * | 2012-02-17 | 2012-07-11 | 北京时代民芯科技有限公司 | Method for manufacturing planar high-voltage ultrafast soft recovery diode |
| CN203351612U (en) * | 2013-08-01 | 2013-12-18 | 泰科天润半导体科技（北京）有限公司 | Schottky diode |
| CN108493108A (en) * | 2018-05-16 | 2018-09-04 | 江苏润奥电子制造股份有限公司 | A kind of manufacturing method of high-voltage high-speed soft-recovery diode |
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