CN111630509B - 执行积和运算的运算电路 - Google Patents

执行积和运算的运算电路 Download PDF

Info

Publication number
CN111630509B
CN111630509B CN201880085295.3A CN201880085295A CN111630509B CN 111630509 B CN111630509 B CN 111630509B CN 201880085295 A CN201880085295 A CN 201880085295A CN 111630509 B CN111630509 B CN 111630509B
Authority
CN
China
Prior art keywords
circuit
bit
value
circuits
real
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201880085295.3A
Other languages
English (en)
Chinese (zh)
Other versions
CN111630509A (zh
Inventor
川合健治
粟田亮
武井和人
饭塚公昭
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Entiti Corp
Ntt Innovative Devices Co ltd
Original Assignee
Ntt Innovative Devices Co ltd
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ntt Innovative Devices Co ltd, Nippon Telegraph and Telephone Corp filed Critical Ntt Innovative Devices Co ltd
Publication of CN111630509A publication Critical patent/CN111630509A/zh
Application granted granted Critical
Publication of CN111630509B publication Critical patent/CN111630509B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G06F7/5443—Sum of products
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
    • G06F7/5324—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel partitioned, i.e. using repetitively a smaller parallel parallel multiplier or using an array of such smaller multipliers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computing Systems (AREA)
  • Data Mining & Analysis (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • Databases & Information Systems (AREA)
  • Algebra (AREA)
  • Complex Calculations (AREA)
CN201880085295.3A 2018-01-05 2018-12-18 执行积和运算的运算电路 Active CN111630509B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2018000452A JP6863907B2 (ja) 2018-01-05 2018-01-05 演算回路
JP2018-000452 2018-01-05
PCT/JP2018/046496 WO2019135355A1 (ja) 2018-01-05 2018-12-18 演算回路

Publications (2)

Publication Number Publication Date
CN111630509A CN111630509A (zh) 2020-09-04
CN111630509B true CN111630509B (zh) 2023-12-08

Family

ID=67143671

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201880085295.3A Active CN111630509B (zh) 2018-01-05 2018-12-18 执行积和运算的运算电路

Country Status (4)

Country Link
US (1) US11494165B2 (https=)
JP (1) JP6863907B2 (https=)
CN (1) CN111630509B (https=)
WO (1) WO2019135355A1 (https=)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6995629B2 (ja) * 2018-01-05 2022-01-14 日本電信電話株式会社 演算回路
CN116010762B (zh) * 2021-10-22 2026-03-13 意法半导体(格勒诺布尔2)公司 包括硬件计算器的集成电路和相应的计算方法
CN117335810A (zh) * 2022-06-23 2024-01-02 加特兰微电子科技(上海)有限公司 数据压缩、解压缩方法及装置

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6423614A (en) * 1987-07-17 1989-01-26 Sanyo Electric Co Method for constituting low-band digital filter
JP2000132539A (ja) * 1998-10-28 2000-05-12 Matsushita Electric Ind Co Ltd 演算装置
JP2004121263A (ja) * 1998-09-04 2004-04-22 Aventis Pasteur Ltd 子宮頸がんの治療
JP2006157252A (ja) * 2004-11-26 2006-06-15 Canon Inc データ分類方法、多次元補間装置、多次元補間方法、及びコンピュータプログラム
CN101682297A (zh) * 2007-06-04 2010-03-24 Nxp股份有限公司 包含频带选择的数字信号处理电路和方法
JP2011186592A (ja) * 2010-03-05 2011-09-22 Renesas Electronics Corp フィルタ演算器、フィルタ演算方法及び動き補償処理装置
WO2014023871A1 (es) * 2012-08-09 2014-02-13 Universidade De Santiago De Compostela Aparato y método para calcular operaciones de potenciación y extracción de raíces
CN103677736A (zh) * 2012-09-04 2014-03-26 亚德诺半导体股份有限公司 数字信号处理器的数据路径电路
CN105849690A (zh) * 2014-07-02 2016-08-10 上海兆芯集成电路有限公司 使用第一和第二子运算的分路融合乘积-累加运算

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000062421A1 (en) * 1999-04-14 2000-10-19 Nokia Networks Oy Digital filter and method for performing a multiplication based on a look-up table
JP3875183B2 (ja) * 2002-11-20 2007-01-31 シャープ株式会社 演算装置
US7043515B2 (en) * 2002-12-10 2006-05-09 Isic Corporation Methods and apparatus for modular reduction circuits
US20050201457A1 (en) * 2004-03-10 2005-09-15 Allred Daniel J. Distributed arithmetic adaptive filter and method
EP1975906B1 (en) * 2006-01-13 2012-07-04 Fujitsu Ltd. Montgomery s algorithm multiplication remainder calculator
GB2448744A (en) * 2007-04-26 2008-10-29 Wolfson Microelectronics Plc Look-up table indexing scheme with null values used to expand table to have a power of two number of entries in each cycle of coefficients
KR20120077164A (ko) * 2010-12-30 2012-07-10 삼성전자주식회사 Ｓｉｍｄ 구조를 사용하는 복소수 연산을 위한 사용하는 장치 및 방법
JP5920226B2 (ja) * 2011-02-15 2016-05-18 日本電気株式会社 複素演算処理用コプロセッサ及びプロセッサシステム
US10303735B2 (en) * 2015-11-18 2019-05-28 Intel Corporation Systems, apparatuses, and methods for K nearest neighbor search
JP6995629B2 (ja) * 2018-01-05 2022-01-14 日本電信電話株式会社 演算回路

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6423614A (en) * 1987-07-17 1989-01-26 Sanyo Electric Co Method for constituting low-band digital filter
JP2004121263A (ja) * 1998-09-04 2004-04-22 Aventis Pasteur Ltd 子宮頸がんの治療
JP2000132539A (ja) * 1998-10-28 2000-05-12 Matsushita Electric Ind Co Ltd 演算装置
JP2006157252A (ja) * 2004-11-26 2006-06-15 Canon Inc データ分類方法、多次元補間装置、多次元補間方法、及びコンピュータプログラム
CN101682297A (zh) * 2007-06-04 2010-03-24 Nxp股份有限公司 包含频带选择的数字信号处理电路和方法
JP2011186592A (ja) * 2010-03-05 2011-09-22 Renesas Electronics Corp フィルタ演算器、フィルタ演算方法及び動き補償処理装置
WO2014023871A1 (es) * 2012-08-09 2014-02-13 Universidade De Santiago De Compostela Aparato y método para calcular operaciones de potenciación y extracción de raíces
CN103677736A (zh) * 2012-09-04 2014-03-26 亚德诺半导体股份有限公司 数字信号处理器的数据路径电路
CN105849690A (zh) * 2014-07-02 2016-08-10 上海兆芯集成电路有限公司 使用第一和第二子运算的分路融合乘积-累加运算

Also Published As

Publication number Publication date
US11494165B2 (en) 2022-11-08
JP6863907B2 (ja) 2021-04-21
CN111630509A (zh) 2020-09-04
JP2019121172A (ja) 2019-07-22
WO2019135355A1 (ja) 2019-07-11
US20210064340A1 (en) 2021-03-04

Similar Documents

Publication Publication Date Title
CN111630509B (zh) 执行积和运算的运算电路
CA1332196C (en) Radix-16 divider using overlapped quotient bit selection and concurrent quotient rounding and correction
KR20040092376A (ko) 몽고메리 모듈러 곱셈기 및 캐리 저장 가산을 이용한몽고메리 모듈러 곱셈 방법
Langhammer et al. Design and implementation of an embedded FPGA floating point DSP block
CN108334304B (zh) 数字递归除法
Molahosseini et al. New arithmetic residue to binary converters
Gowreesrinivas et al. Comparative study on performance of single precision floating point multiplier using vedic multiplier and different types of adders
Buddhe et al. Design and verification of dadda algorithm based binary floating point multiplier
KR100329914B1 (ko) 제산장치
RU2717915C1 (ru) Вычислительное устройство
US20230086090A1 (en) Methods and Apparatus for Quotient Digit Recoding in a High-Performance Arithmetic Unit
Laxman et al. FPGA implementation of different multiplier architectures
Iyer et al. Generalised algorithm for multiplying binary numbers via vedic mathematics
JP7191797B2 (ja) 演算回路
KR100853787B1 (ko) 가변 진법 나눗셈 연산기
Rouhifar et al. Fast overflow detection in moduli set {2n–1, 2n, 2n+ 1}
RU2829089C1 (ru) Умножитель по модулю
Rezai et al. Algorithm design and theoretical analysis of a novel CMM modular exponentiation algorithm for large integers
Sharoun Residue number system (RNS)
Awasthi et al. Hybrid signed digit arithmetic in efficient computing: A comparative approach to performance assay
Ram et al. Efficient hardware design of parameterized posit multiplier and posit adder
Teja et al. Implementation of vedic multiplier using modified architecture by routing rearrangement for high-optimization
Reshma et al. Two Speed Modified Radix-4 Booth Multiplier With Different Adder Configurations
RU2751802C1 (ru) Умножитель по модулю
Babu et al. Fpga implementation of energy efficient approximate multiplier with image processing applications

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
CB02 Change of applicant information

Address after: Kanagawa, Japan

Applicant after: NTT Innovative Devices Co.,Ltd.

Applicant after: NIPPON TELEGRAPH AND TELEPHONE Corp.

Address before: Kanagawa, Japan

Applicant before: NTT Electronics Corp.

Applicant before: NIPPON TELEGRAPH AND TELEPHONE Corp.

CB02 Change of applicant information
GR01 Patent grant
GR01 Patent grant
CP03 Change of name, title or address

Address after: Kanagawa, Japan

Patentee after: NTT Innovative Devices Co.,Ltd.

Country or region after: Japan

Patentee after: Entiti Corp.

Address before: Kanagawa, Japan

Patentee before: NTT Innovative Devices Co.,Ltd.

Country or region before: Japan

Patentee before: NIPPON TELEGRAPH AND TELEPHONE Corp.

CP03 Change of name, title or address