CN111627982B - Structure and method of high-performance super-junction structure IGBT - Google Patents
Structure and method of high-performance super-junction structure IGBT Download PDFInfo
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- 238000000992 sputter etching Methods 0.000 claims description 9
- 238000000137 annealing Methods 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
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- 238000005468 ion implantation Methods 0.000 claims description 3
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- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
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Abstract
The invention provides a structure of a high-performance super-junction structure IGBT and a method thereof, which comprises a collector, wherein a p-type buffer area is arranged above the collector, an n-type buffer area is arranged above the p-type buffer area, an n + -type drift area is arranged above the n-type buffer area, a p-type block is arranged inside the n + -type drift area, a first etching groove is arranged at the top of the n + -type drift area, a second etching groove is arranged at the bottom of the first etching groove, a p-type grid block is arranged inside the second etching groove, a p-type area is arranged inside the first etching groove, a third etching groove is arranged at the top of the p-type area, the drift area is divided into three parts by arranging the p-type block and the p-type grid block in the drift area, the p-type block and the p-type grid block both play a role of blocking holes, the conductance modulation effect is enhanced, and the device has smaller conduction voltage drop under large current, the doping concentration of the drift region can be improved while the same withstand voltage is ensured, the on-resistance and the forward voltage drop are reduced, and the power consumption is reduced.
Description
Technical Field
The invention relates to the technical field of Insulated Gate Bipolar Transistors (IGBT), in particular to a structure of a high-performance super-junction structure IGBT.
Background
At present, the novel power electronic devices in China mainly comprise VDMOS (vertical double-diffused metal oxide semiconductor) and IGBT (insulated gate bipolar transistor) devices, wherein the IGBT has MOS input and bipolar output functions and integrates the advantages of small on-state voltage drop, high current-carrying density, high voltage resistance, small power MOSFET (metal-oxide-semiconductor field effect transistor) driving power, high switching speed, high input impedance and good thermal stability of BJT devices. Since the advent, the switching device is rapidly developed to become the mainstream power switching device in the field of medium and high power electronics. The method is widely applied to the fields of industrial control, automotive electronics, household electrical appliances, network communication and the like. Like other power devices, the optimization of the IGBT structure mainly focuses on both reducing power consumption and increasing breakdown voltage. In order to reduce the power consumption of the device, the on-resistance is firstly reduced, which requires a drift layer of the device to have a higher concentration of free carriers in an on state, however, a large amount of free carriers can lead to a longer off time of the device and increase the off-loss of the device, so that there is a contradiction between reducing the on-resistance and reducing the off-loss, which is a main problem of the IGBT. In response to these problems, methods such as doping gold, platinum, or controlling the lifetime of carriers by irradiation, reducing reverse recovery charge, etc. have been proposed. However, the charge balance is damaged by doping, and the service life of the device is greatly influenced by irradiation. Therefore, it is proposed to use schottky contact in super junction MOSFET to improve the switching characteristics, and the third generation COOLMOSTMC3 series improves the reverse recovery characteristics by integrating a SiC diode inside, which achieves better effect but increases the manufacturing difficulty and cost.
Disclosure of Invention
The embodiment of the invention provides a structure of a high-performance super-junction structure IGBT, and a p-type block and a p-type grid leakage block are arranged in a drift region, so that the same withstand voltage can be ensured, the doping concentration of the drift region can be increased, the on-resistance and the forward voltage drop are reduced, and the power consumption is reduced.
In view of the above problems, the technical solution proposed by the present invention is:
a structure of a high-performance super junction structure IGBT comprises a collector, a p-type buffer area is arranged above the collector, an n-type buffer area is arranged above the p-type buffer area, an n + type drift area is arranged above the n-type buffer area, a p-type block is arranged inside the n + type drift region, a first etching groove is arranged at the top of the n + type drift region, a second etching groove is arranged at the bottom of the first etching groove, a p-type grid leakage block is arranged in the second etching groove, a p-type region is arranged in the first etching groove, a third etching groove is arranged at the top of the p-type region, an n-type region is arranged in the third etching groove, an emitter is arranged on one side of the top of the n-type region, and a grid electrode is arranged on the other side of the top of the n-type region, and channels are arranged on the surface of the p-type grid leakage block.
As a preferred embodiment of the present invention, the p-type blocks are disposed on two sides of the inside of the n + type drift region.
As a preferred embodiment of the present invention, the p-type buffer region, the n-type buffer region, and the n + -type drift region are formed on the surface of the substrate by a chemical vapor deposition method.
The embodiment of the invention provides a method for a high-performance super junction structure IGBT, which is characterized by comprising the following steps:
s1, setting a doped region, and growing a p-type buffer region on the surface of the substrate by a chemical vapor deposition method; growing an n-type buffer area on the surface of the p-type buffer area by a chemical vapor deposition method; growing an n + type drift region on the surface of the n type buffer region by a chemical vapor deposition method;
s2, etching for the first time, namely etching a first etching groove on the top of the n + type drift region through an ion etching process; etching a second etching groove at the bottom of the first etching groove by an ion etching process;
s3, arranging a buried layer, arranging p-type blocks on two sides of the inside of the n + type drift region through an ion implantation method, and arranging the p-type grid leakage blocks inside the second etched grooves;
s4, etching for the second time, generating a p-type area in the second etching groove through a chemical vapor deposition method, etching a third etching groove at the top of the p-type area through an ion etching process, and generating an n-type area in the third etching groove through the chemical vapor deposition method; removing the substrate by adopting a chemical mechanical polishing process;
s5, annealing, namely annealing for 5 minutes in a nitrogen atmosphere at the temperature of 900 ℃;
s6, setting a contact window, removing the back surface of the substrate and setting a metal material layer to form a collector; respectively arranging a metal layer and an oxide layer on the top of the structure finished part and respectively forming an emitter and a gate by arranging the metal layer on the oxide layer
Compared with the prior art, the invention has the beneficial effects that: the drift region is divided into three parts by arranging the p-type block and the p-type grid leakage block in the drift region, and the p-type block and the p-type grid leakage block play a role in blocking a cavity, so that the conductivity modulation effect is enhanced, a device has smaller conduction voltage drop under large current, the same withstand voltage can be ensured, the doping concentration of the drift region is improved, the conduction resistance and the forward voltage drop are reduced, and the power consumption is reduced.
The foregoing description is only an overview of the technical solutions of the present invention, and the embodiments of the present invention are described below in order to make the technical means of the present invention more clearly understood and to make the above and other objects, features, and advantages of the present invention more clearly understandable.
Drawings
FIG. 1 is a first structural diagram of step S1 according to the embodiment of the present invention;
FIG. 2 is a second structural diagram of step S1 according to the embodiment of the present invention;
FIG. 3 is a schematic diagram of a third structure of step S1 according to the embodiment of the present invention;
FIG. 4 is a first structural diagram of step S3 according to the embodiment of the present invention;
FIG. 5 is a first structural diagram of step S2 according to the embodiment of the present invention;
FIG. 6 is a second structural diagram of step S3 according to the embodiment of the present invention;
FIG. 7 is a first structural diagram of step S4 according to the embodiment of the present invention;
FIG. 8 is a second structural diagram of step S4 according to the embodiment of the present invention;
FIG. 9 is a schematic structural diagram of step S6 according to the disclosure of the present invention;
FIG. 10 is a schematic structural diagram of a p-type leakage grid block according to an embodiment of the present invention;
fig. 11 is a schematic flow chart of a method for a high-performance super junction IGBT disclosed in the embodiment of the present invention.
Reference numerals:
1-a substrate; a 2-p type buffer region; a 3-n type buffer region; a 4-n + type drift region; a 5-p type block; a 6-p type leaky grid block; a 7-p type region; an 8-n type region; 9-emission level; 10-a gate; 11-a collector electrode; 12 — first etch trench; 13-second etching the trench; 14-third etch trench.
DETAILED DESCRIPTION OF EMBODIMENT (S) OF INVENTION
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments.
Referring to fig. 1-10, a p-type buffer region 2 is disposed above the collector 11, an n-type buffer region 3 is disposed above the p-type buffer region 2, an n + type drift region 4 is disposed above the n-type buffer region 3, a p-type block 5 is disposed inside the n + type drift region 4, the p-type block 5 is disposed on two sides of the n + type drift region 4, a first etching trench 12 is disposed on the top of the n + type drift region 4, a second etching trench 13 is disposed on the bottom of the first etching trench 12, a p-type grid-leaking block 6 is disposed inside the second etching trench 13, a p-type region 7 is disposed inside the first etching trench 12, a third etching trench 14 is disposed on the top of the p-type region 7, an n-type region 8 is disposed inside the third etching trench 14, and an emitter stage 9 is disposed on one side of the top of the n-type region 8, the other side of the top of the n-type region 8 is provided with a grid 10, the surface of the p-type grid-leaking block 6 is provided with a channel, the p-type buffer region 2, the n-type buffer region 3 and the n + type drift region 4 are generated on the surface of the substrate 1 through a chemical vapor deposition method, when the current of the collector 11 is increased, free electrons enter the n + type drift region 4 through the p-type buffer region 2 and the n-type buffer region 3, the p-type block 5 and the p-type grid-leaking block 6 play a role in blocking holes and electrons, the free electrons can pass through the channel arranged on the p-type grid-leaking block 6, the conductivity modulation effect is enhanced, the super-junction structure IGBT has smaller conduction voltage drop under large current, the same withstand voltage can be ensured, the doping concentration of the drift region is improved, the conduction resistance and the forward voltage drop are reduced, and the power consumption is reduced.
Referring to fig. 1-11, a method for a high-performance super junction structure IGBT includes the following steps:
s1, setting a doped region, and growing a p-type buffer region 2 on the surface of the substrate 1 by a chemical vapor deposition method; growing an n-type buffer region 3 on the surface of the p-type buffer region 2 by a chemical vapor deposition method; growing an n + type drift region 4 on the surface of the n type buffer region 3 by a chemical vapor deposition method;
s2, etching for the first time, namely etching a first etching groove 12 on the top of the n + type drift region 4 through an ion etching process; etching a second etching trench 13 at the bottom of the first etching trench 12 by an ion etching process;
s3, arranging a buried layer, arranging p-type blocks 5 on two sides of the inside of the n + type drift region 4 through an ion implantation method, and arranging the p-type grid leakage blocks 6 inside the second etching grooves 13;
s4, etching for the second time, generating a p-type region 7 in the second etching groove 13 through a chemical vapor deposition method, etching a third etching groove 14 at the top of the p-type region 7 through an ion etching process, and generating an n-type region 8 in the third etching groove 14 through the chemical vapor deposition method; removing the substrate 1 by adopting a chemical mechanical polishing process;
s5, annealing, namely annealing for 5 minutes in a nitrogen atmosphere at the temperature of 900 ℃;
s6, setting a contact window, removing the metal material layer arranged on the back of the substrate 1 to form a collector 11; a metal layer and an oxide layer are respectively provided on top of the structure completed part and the metal layer is provided on the oxide layer to form an emitter 9 and a gate 10, respectively.
The specific working principle is that the p-type blocks 5 are arranged inside the n + type drift region 4, the p-type blocks 5 are arranged on two sides of the n + type drift region 4, free electrons enter the n + type drift region 4 through the p-type buffer region 2 and the n-type buffer region 3, the p-type blocks 5 and the p-type grid leakage blocks 6 play a role in blocking holes and electrons, the free electrons can pass through channels formed in the p-type grid leakage blocks 6, the conductance modulation effect is enhanced, the super-junction structure IGBT has smaller conduction voltage drop under large current, the doping concentration of the drift region can be improved while the same withstand voltage is guaranteed, the conduction resistance and the forward voltage drop are reduced, and the power consumption is reduced.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (4)
1. A structure of a high-performance super-junction structure IGBT is characterized by comprising a collector electrode, wherein a p-type buffer area is arranged above the collector electrode, an n-type buffer area is arranged above the p-type buffer area, an n + type drift area is arranged above the n-type buffer area, a p-type block is arranged inside the n + type drift area, a first etching groove is arranged at the top of the n + type drift area, a second etching groove is arranged at the bottom of the first etching groove, a p-type grid block is arranged inside the second etching groove, a p-type area is arranged inside the first etching groove, a third etching groove is arranged at the top of the p-type area, an n-type area is arranged inside the third etching groove, an emitter electrode is arranged on one side of the top of the n-type area, and a grid electrode is arranged on the other side of the top of the n-type area, and the surface of the p-type grid leakage block is provided with a channel.
2. The structure of the high-performance super junction structure IGBT according to claim 1, characterized in that: the p-type blocks are arranged on two sides of the inside of the n + type drift region.
3. The structure of the high-performance super junction structure IGBT according to claim 1, characterized in that: the p-type buffer region, the n-type buffer region and the n + type drift region are generated on the surface of the substrate through a chemical vapor deposition method.
4. A method for a high-performance super junction structure IGBT is characterized by comprising the following steps:
s1, setting a doped region, and growing a p-type buffer region on the surface of the substrate by a chemical vapor deposition method; growing an n-type buffer area on the surface of the p-type buffer area by a chemical vapor deposition method; growing an n + type drift region on the surface of the n type buffer region by a chemical vapor deposition method;
s2, etching for the first time, namely etching a first etching groove on the top of the n + type drift region through an ion etching process; etching a second etching groove at the bottom of the first etching groove by an ion etching process;
s3, arranging a buried layer, arranging p-type blocks on two sides of the inside of the n + type drift region through an ion implantation method, and arranging the p-type grid leakage blocks inside the second etching grooves;
s4, etching for the second time, generating a p-type area in the second etching groove through a chemical vapor deposition method, etching a third etching groove at the top of the p-type area through an ion etching process, and generating an n-type area in the third etching groove through the chemical vapor deposition method; removing the substrate by adopting a chemical mechanical polishing process;
s5, annealing, namely annealing for 5 minutes in a nitrogen atmosphere at the temperature of 900 ℃;
s6, setting a contact window, removing the back surface of the substrate and setting a metal material layer to form a collector; and respectively arranging a metal layer and an oxidation layer on the top of the structure finished part, and arranging the metal layer on the oxidation layer to respectively form an emitter and a grid.
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| US9236458B2 (en) * | 2013-07-11 | 2016-01-12 | Infineon Technologies Ag | Bipolar transistor and a method for manufacturing a bipolar transistor |
| CN103594503A (en) * | 2013-11-19 | 2014-02-19 | 西安永电电气有限责任公司 | IGBT with floating junction structure |
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