CN111614166A - Excitation power supply control system and method based on SFP + multi-module accelerator - Google Patents
Excitation power supply control system and method based on SFP + multi-module accelerator Download PDFInfo
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- CN111614166A CN111614166A CN202010523204.9A CN202010523204A CN111614166A CN 111614166 A CN111614166 A CN 111614166A CN 202010523204 A CN202010523204 A CN 202010523204A CN 111614166 A CN111614166 A CN 111614166A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J13/00—Circuit arrangements for providing remote indication of network conditions, e.g. an instantaneous record of the open or closed condition of each circuitbreaker in the network; Circuit arrangements for providing remote control of switching means in a power distribution network, e.g. switching in and out of current consumers by using a pulse code signal carried by the network
- H02J13/00001—Circuit arrangements for providing remote indication of network conditions, e.g. an instantaneous record of the open or closed condition of each circuitbreaker in the network; Circuit arrangements for providing remote control of switching means in a power distribution network, e.g. switching in and out of current consumers by using a pulse code signal carried by the network characterised by the display of information or by user interaction, e.g. supervisory control and data acquisition systems [SCADA] or graphical user interfaces [GUI]
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J13/00—Circuit arrangements for providing remote indication of network conditions, e.g. an instantaneous record of the open or closed condition of each circuitbreaker in the network; Circuit arrangements for providing remote control of switching means in a power distribution network, e.g. switching in and out of current consumers by using a pulse code signal carried by the network
- H02J13/00006—Circuit arrangements for providing remote indication of network conditions, e.g. an instantaneous record of the open or closed condition of each circuitbreaker in the network; Circuit arrangements for providing remote control of switching means in a power distribution network, e.g. switching in and out of current consumers by using a pulse code signal carried by the network characterised by information or instructions transport means between the monitoring, controlling or managing units and monitored, controlled or operated power network element or electrical equipment
- H02J13/00016—Circuit arrangements for providing remote indication of network conditions, e.g. an instantaneous record of the open or closed condition of each circuitbreaker in the network; Circuit arrangements for providing remote control of switching means in a power distribution network, e.g. switching in and out of current consumers by using a pulse code signal carried by the network characterised by information or instructions transport means between the monitoring, controlling or managing units and monitored, controlled or operated power network element or electrical equipment using a wired telecommunication network or a data transmission bus
- H02J13/00017—Circuit arrangements for providing remote indication of network conditions, e.g. an instantaneous record of the open or closed condition of each circuitbreaker in the network; Circuit arrangements for providing remote control of switching means in a power distribution network, e.g. switching in and out of current consumers by using a pulse code signal carried by the network characterised by information or instructions transport means between the monitoring, controlling or managing units and monitored, controlled or operated power network element or electrical equipment using a wired telecommunication network or a data transmission bus using optical fiber
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J13/00—Circuit arrangements for providing remote indication of network conditions, e.g. an instantaneous record of the open or closed condition of each circuitbreaker in the network; Circuit arrangements for providing remote control of switching means in a power distribution network, e.g. switching in and out of current consumers by using a pulse code signal carried by the network
- H02J13/00006—Circuit arrangements for providing remote indication of network conditions, e.g. an instantaneous record of the open or closed condition of each circuitbreaker in the network; Circuit arrangements for providing remote control of switching means in a power distribution network, e.g. switching in and out of current consumers by using a pulse code signal carried by the network characterised by information or instructions transport means between the monitoring, controlling or managing units and monitored, controlled or operated power network element or electrical equipment
- H02J13/00019—Circuit arrangements for providing remote indication of network conditions, e.g. an instantaneous record of the open or closed condition of each circuitbreaker in the network; Circuit arrangements for providing remote control of switching means in a power distribution network, e.g. switching in and out of current consumers by using a pulse code signal carried by the network characterised by information or instructions transport means between the monitoring, controlling or managing units and monitored, controlled or operated power network element or electrical equipment using optical means
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B90/00—Enabling technologies or technologies with a potential or indirect contribution to GHG emissions mitigation
- Y02B90/20—Smart grids as enabling technology in buildings sector
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y04—INFORMATION OR COMMUNICATION TECHNOLOGIES HAVING AN IMPACT ON OTHER TECHNOLOGY AREAS
- Y04S—SYSTEMS INTEGRATING TECHNOLOGIES RELATED TO POWER NETWORK OPERATION, COMMUNICATION OR INFORMATION TECHNOLOGIES FOR IMPROVING THE ELECTRICAL POWER GENERATION, TRANSMISSION, DISTRIBUTION, MANAGEMENT OR USAGE, i.e. SMART GRIDS
- Y04S40/00—Systems for electrical power generation, transmission, distribution or end-user application management characterised by the use of communication or information technologies, or communication or information technology specific aspects supporting them
- Y04S40/12—Systems for electrical power generation, transmission, distribution or end-user application management characterised by the use of communication or information technologies, or communication or information technology specific aspects supporting them characterised by data transport means between the monitoring, controlling or managing units and monitored, controlled or operated electrical equipment
- Y04S40/124—Systems for electrical power generation, transmission, distribution or end-user application management characterised by the use of communication or information technologies, or communication or information technology specific aspects supporting them characterised by data transport means between the monitoring, controlling or managing units and monitored, controlled or operated electrical equipment using wired telecommunication networks or data transmission busses
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Abstract
The invention relates to an excitation power supply control system and method based on an SFP + multi-module accelerator, which comprises the following steps: the system comprises a master controller and a plurality of slave controller branches; the main controller is arranged in the control cabinet; each slave controller branch is provided with a plurality of slave controllers which are connected in series, and each slave controller is respectively arranged in each power unit cabinet and connected with the power unit cabinet; the master controller is connected with the slave controllers on the branch circuits of the slave controllers through optical fibers to form a master-slave control structure; the master controller sends a control instruction sent by the upper computer to each slave controller; each slave controller is used for acquiring the temperature, the current voltage and the relay protection state data of the corresponding power unit cabinet; and the main controller processes the acquired data and then sends the related instruction to the corresponding slave controller, and the slave controller converts the related instruction information and then sends the converted related instruction information to the corresponding power unit cabinet. The invention can be widely applied to the field of accelerator power supply control.
Description
Technical Field
The invention relates to the field of accelerator power supplies, in particular to an excitation power supply control system and method based on an interface device for converting a high-speed SFP (Small Form-factor pluggable Small-size pluggable gigabit electric signal into an optical signal) and a multi-module accelerator.
Background
The control mode that accelerator device digital power control system used frequently at home and abroad is mostly single-chip distributed control mode at present, and it is single, logic is simple, the program development flexibility ratio is lower to adopt this kind of single-chip distributed control mode control overall structure. The common excitation power supplies of various types have different requirements on the computing capability of the controller, so that the computing capability and the cost are easily wasted by using a unified controller. In addition, due to the lack of a controller board level synchronous clock network, synchronous data of each node cannot be accurately given, and the system response can only reach millisecond level. Therefore, the existing digital power control system cannot control the synchronism of the power supply of the synchrotron with high precision, and the additional special time service system can greatly increase the cost.
A single-chip distributed power control system is disclosed in the literature 'digital power regulation system and regulation method of an ion cancer treatment accelerator', and is mainly characterized in that: 1. each power supply controller uses an Altera Cyclone EP2C70FPGA, and a programmable system on chip containing two NiosII CPUs is built by utilizing an SOPC builder tool; 2. the remote computer downloads the synchronous case table from the Ethernet chip and the universal asynchronous receiving/sending device serial communication equipment; 3. the output current or voltage of the digital power supply is converted into digital quantity and sent to the FPGA for closed-loop regulation. The system uses the same controller hardware for all power supplies, and ADC collected data are directly sent to the FPGA to be independently operated. The processor has unreasonable calculation capacity distribution, higher cost and simple structure. The network is used for issuing the synchronization case, and then the trigger pulse mechanism is low in synchronization precision. In addition, all data take electric signals as carriers, and the stability is influenced when the field electromagnetic environment is poor. With the development of the SFP + high-speed transmission technology, it is possible for the accelerator power supply controller ADC to collect a large amount of data and transmit the data to the existing board from the original board level for long distance transmission.
Disclosure of Invention
In view of the above problems, an object of the present invention is to provide an excitation power control system and method based on an SFP + multi-module accelerator, where the excitation power control system uses an independently designed multi-module accelerator excitation power controller, the power controller uses a centralized control strategy to develop an SFP + bottom driver and a dedicated communication protocol, connects a master controller and each slave controller at a transmission rate of 5Gbps, and transmits all data required by a digital power supply, such as ADC sampling data, relay protection state, temperature data, on/off, reset, self-check instructions, initialization parameters, various self-check instructions, current setting data, and the like sent back by each slave controller. The multimode optical fiber is used as a transmission medium and is connected with the master controller and the slave controllers of all branches, the data synchronization precision can reach within 1us, and the maximum distance can reach 300M. Provides a high-speed, long-distance and reliable technical solution.
In order to achieve the purpose, the invention adopts the following technical scheme:
the first aspect of the present invention provides an excitation power supply control system based on an SFP + multi-module accelerator, including a control cabinet and a plurality of power unit cabinets, where each power unit cabinet includes an IGBT drive circuit, a PLC and a sensor, and further including: the main controller is arranged in the control cabinet, and the auxiliary controllers, the upper computer and the debugging computer are arranged in the power unit cabinets; each slave controller is divided into a plurality of groups, each slave controller in each group is connected in series to form a slave controller branch, and each slave controller branch is connected with the master controller through an optical fiber to form a master-slave control structure; the master controller is used for configuring the master controller and each slave controller according to control and debugging parameters sent by the upper computer and the debugging computer; each slave controller is used for acquiring data of the power unit cabinet connected with the slave controller and sending the data to the master controller; and the master controller processes the data collected by each slave controller and then sends a control instruction to the corresponding slave controller, and the slave controller processes the control instruction and then sends the control instruction to the corresponding power unit cabinet.
Furthermore, the main controller comprises a first FPGA control unit, a DSP operation unit, an RJ45 network interface unit, an RS232 debugging interface unit, a first HFBR synchronous trigger unit, a first storage unit, a first SFP + communication unit and a second storage unit; the first FPGA control unit is communicated with the upper computer through the RJ45 network interface unit to realize power on/off, state detection and current setting control; the RS232 debugging interface unit is connected with a debugging computer to realize parameter configuration and fault diagnosis of the master controller and each slave controller; data storage is realized by reading and writing the first storage unit; sending a synchronous trigger signal to each slave controller branch circuit through the first HFBR synchronous trigger unit to realize trigger pulse current enabling; data transmission between the first SFP + communication unit and each slave branch is achieved, and the data transmission comprises receiving data collected by each slave branch and sending a control instruction obtained by calculation of the DSP operation unit to each slave branch; and the DSP operation unit is connected with the second storage unit, realizes closed-loop regulation and a vector rectification algorithm, and stores data before and after data processing.
Further, the first SFP + communication unit includes three parallel SFP + transceivers, and the SFP + transceivers support optical transceivers with 850nm wavelength and up to 10 Gbps.
Further, the number of the slave controller branches is at least one, and the number of the slave controllers arranged on each slave controller branch is at most 6.
Further, the slave controller comprises a second FPGA control unit, a second SFP + communication unit, an RS485 communication unit, a multi-path PWM driver unit, a multi-path ADC unit and a second HFBR synchronous trigger unit; the second HFBR synchronous trigger unit is used for receiving a synchronous trigger signal issued by the main controller and sending the synchronous trigger signal to the second FPGA control unit as a synchronous pulse signal; the multi-channel ADC unit is used for collecting current and voltage data in the power unit cabinet and sending the current and voltage data to the second FPGA control unit; the RS485 communication unit is used for communicating with the PLC in the power unit cabinet and sending temperature data and relay protection state data uploaded by the PLC to the second FPGA control unit; the second SFP + communication unit is used for gradually forwarding all data in the current-level slave controller and all data to be uploaded by the subordinate slave controllers until the data reach the master controller, sending given data issued by the master controller to the second FPGA control unit, sending a switching-on/off and reset command to a PLC in the power unit cabinet through the RS485 communication unit by the second FPGA control unit, converting current given data issued by the master controller into a multi-path PWM driving signal, and then sending the multi-path PWM driving signal to an IGBT driving circuit in the power unit cabinet through the multi-path PWM driver unit.
Furthermore, the communication optical fiber between the main controller and the branch of the slave controller is a multimode optical fiber, and the multimode optical fiber can realize long-distance connection within 300M.
The second aspect of the present invention provides an excitation power supply control method based on an SFP + multi-module accelerator, which includes the following steps: 1) the upper computer sends the controller configuration information, the initialization instruction and the self-checking instruction to the main controller, and the main controller sends the corresponding instruction to the corresponding slave controller; 2) each slave controller completes initialization, configuration and self-checking of the slave controller according to the received controller configuration information, initialization instructions and self-checking instructions, sends self-checking results to the master controller, and reports the self-checking results to an upper computer by the master controller; 3) in each preset period, the main controller continuously inquires the current and voltage data of the power unit cabinet corresponding to the current and voltage data acquired by each slave controller, performs closed-loop regulation according to the current data acquired by inquiry, acquires current given data and then sends the current given data to the corresponding slave controller, and meanwhile, the main controller extracts a startup and shutdown and reset instruction sent by an upper computer from a command buffer area and sends the instruction to the slave controller; 4) each slave controller sends the received on-off and reset instructions to a PLC in the power unit cabinet, converts the received current given data into a plurality of paths of PWM driving signals and sends the signals to an IGBT driving circuit in the power unit cabinet; 5) after each preset period is finished, the main controller inquires the relay protection state data and the temperature data of the power unit cabinet, which are received from the controllers and correspond to the controllers, once, and sends the relay protection state data and the temperature data to the main controller and then to an upper computer for displaying.
Further, in the step 2), the method for performing self-test from the controller includes:
when an RS485 or SFP self-checking command is received, the corresponding slave controller starts to carry out self-checking test, firstly, test data is sent to a PLC in a power balancing unit cabinet through an RS485 communication unit or to a master controller through a second SFP + communication unit, if the opposite side receives and returns the corresponding data, the communication is normal, otherwise, the test data is sent again, if the opposite side receives and returns the corresponding data, the communication is normal, otherwise, the communication self-checking error is reported;
when an ADC self-checking command is received, a plurality of paths of high-precision ADC units in the corresponding slave controllers sample a set value in a null mode and send the set value to the master controller, if the master controller returns corresponding data, the acquisition is normal, if the data is wrong, the set value is sent again, and if the data is still not answered correctly, the ADC self-checking error is reported.
Further, when the slave controller communicates data with the master controller, the adopted SFP + data transmission frame format includes: the first bus data holds K28.4 code for bit alignment of the transmitted data; a data arrival trigger code K28.5 used for clock alignment of data; the clock aligns the signal bit, is equivalent to the initial bit of the data bit, and this bit has included the information of the transmission mode, the length is 32 bits; the length of each data packet is 32 bits, wherein the first 20 bits are data, the last 4 bits are serial numbers, the last 8 bits are data check, and the data check bits use a polynomial according to CRC 8: x8+ x5+ x4+ 1; the first data packet is header data which comprises instruction information, branch numbers and slave controller numbers; the second bus data holds the K28.4 code for bit alignment of the transmitted data.
Further, when the slave controller and the master controller carry out data communication, whether the data are sent to the master controller in a serial mode or in a polling mode is judged according to a clock alignment signal position in a query instruction sent by the master controller and the first data packet; when the serial data are transmitted, firstly, the master controller transmits a data query instruction, each slave controller transmits the data query instruction to the last slave controller, and the serial data are waited after the data query instruction is transmitted; then, when uploading data according to a customized communication protocol, each slave controller puts the data into a data packet with a corresponding serial number, and sends the data packet transmitted by the slave controller with the previous serial number to the slave controller with the next serial number after the data packet is serially connected to the master controller; when polling is sent, the master controller sends a data query instruction to each slave controller independently, each slave controller judges whether the data query instruction is the instruction of the slave controller according to the content in the first data packet, when the data query instruction is not a corresponding sequence number, the data query instruction is not processed, only the instruction is forwarded until the slave controller corresponding to the data query instruction uploads data, and in the process of uploading data, other slave controllers do not process the data after receiving the uploaded data, and only the data are uploaded until the master controller receives corresponding query data.
Due to the adoption of the technical scheme, the invention has the following advantages: 1. the invention is applied to the field of accelerator power supply control, and ADC sampling data, temperature data and relay protection state data transmitted by each power unit cabinet are respectively transmitted by each slave controller module in each slave controller branch circuit through SFP + technology; then, the data are gathered in the master controller to carry out closed-loop regulation in a unified mode, given data and various control instructions are issued to the slave controllers through the SFP +, the chip operation efficiency is improved, and the slave controllers use the FPGA with low cost to reduce the cost. 2. The SFP + communication units in the master controller and the slave controllers respectively adopt SFP + optical transceivers with the wavelength of 850nm and capable of supporting 10Gbps at most, multimode optical fibers are adopted between the master controller and the slave controllers for transmission, the effective transmission distance is 300m, and long-distance real-time transmission of multi-module large data information is realized. 3. The invention uses multimode fiber as transmission medium between the main controller and the slave controller, which can be applied in strong electromagnetic field and other field environment, to improve the anti-interference ability of communication. 4. The master controller uniformly sends the synchronization pulse signals to the second HFBR synchronization trigger units in the slave controllers by adopting the first HFBR synchronization trigger units, so that the clock synchronization magnitude among the modules is ensured, the master controller is matched with the SFP + optical transceiver, and the bus data transmission speed and the clock synchronization magnitude among the modules are improved. Therefore, the method can be widely applied to the field of accelerator power supply control.
Drawings
FIG. 1 is a schematic block diagram of an excitation power supply control system for a high speed SFP + multi-module accelerator of the present invention;
FIG. 2 is a diagram of the controller communication logic of the present invention;
FIG. 3 is a data format of the present invention;
FIG. 4 is a data checksum store of the present invention;
FIG. 5a is a data polling mode of the present invention;
fig. 5b and 5c are data concatenation modes of the present invention.
Detailed Description
The present invention is further described below in conjunction with the following figures and specific examples to enable those skilled in the art to better utilize and practice the present invention, which are not intended to be limiting.
As shown in fig. 1, the excitation power supply control system based on the SFP + multi-module accelerator provided by the invention includes an existing control cabinet, an existing power unit cabinet, a master controller, a slave controller, an upper computer and a debugging computer. The slave controllers in each group are connected in series to form a slave controller branch (only three parallel branches are taken as an example in the invention, but not limited thereto), and each slave controller branch is connected with a master controller arranged in an existing control cabinet through an optical fiber to form a master-slave control structure. The master controller is used for configuring the master controller and each slave controller according to control and debugging parameters sent by the upper computer and the debugging computer; each slave controller is used for acquiring data of the power unit cabinet connected with the slave controller and transmitting the data to the master controller; and the master controller processes the data acquired by each slave controller and then sends the control instruction to the corresponding slave controller, and the slave controller converts the control instruction and then sends the control instruction to the corresponding power unit cabinet.
Furthermore, the main controller comprises a first FPGA control unit, a DSP operation unit, an RJ45 network interface unit, an RS232 debugging interface unit, a first HFBR synchronization trigger unit, a first storage unit, a first SFP + communication unit and a second storage unit. The first FPGA control unit is communicated with an upper computer through an RJ45 network interface unit to realize power on/off, state detection and current setting control; the RS232 debugging interface unit is connected with a debugging computer to realize parameter configuration and fault diagnosis of the master controller and each slave controller; data storage is realized by reading and writing the first storage unit; sending a synchronous trigger signal to each slave controller branch circuit through a first HFBR synchronous trigger unit to realize trigger pulse current enabling; the data transmission between each slave controller branch and each slave controller branch is realized through the first SFP + communication unit, and the data transmission comprises the steps of receiving data collected by each slave controller branch and sending a control instruction obtained by calculation of the DSP operation unit to each slave controller branch; and the DSP operation unit is connected with the second storage unit, realizes algorithms such as closed-loop regulation, vector rectification and the like, and stores data before and after data processing.
Furthermore, in the main controller, the first FPGA control unit performs data communication with the DSP operation unit by using an SRIO bus, and performs data communication with the RJ45 network interface unit, the RS232 debugging interface unit, the first HFBR synchronization trigger unit, the first storage unit, and the first SFP + communication unit by using a GTP bus.
Further, in the main controller, the first storage unit includes a first FLASH memory and a first SDRAM memory. The first FLASH memory is used for storing relevant configuration parameters of each controller, including the number of slave controllers on each slave controller branch, ADC enabling data, ADC filtering parameters, ADC maximum and minimum values, ADC integral step length and other parameters, and ensuring that data is not lost after power failure; the first SDRAM memory is used for storing contents such as read-back data, given data, sending instructions, sending parameters, temperature data, relay protection data and the like.
Further, in the main controller, the first SFP + communication unit includes three SFP + transceiver modules. The SFP + transceiver is used as a carrier of optical communication, and adopts an optical transceiver with 850nm wavelength and capable of supporting 10Gbps at most.
Furthermore, in the main controller, the second storage unit comprises a second FLASH memory and a second SDRAM memory, wherein the second FLASH memory is used for storing relevant configuration parameters of the DSP operation unit; the second SDRAM is used for storing data such as read-back data, given data, sending instructions, sending parameters, temperature data and relay protection data related to the algorithm.
Further, in the main controller, the first HFBR synchronization triggering unit adopts an HFBR-1414TZ interface unit.
Furthermore, the number of the slave controllers arranged on each slave controller branch is at most 6.
Further, the slave controller comprises a second FPGA control unit, a second SFP + communication unit, an RS485 communication unit, a multi-path PWM driver unit, a multi-path high-precision ADC unit and a second HFBR synchronous trigger unit. The second HFBR synchronous trigger unit is used for receiving a synchronous trigger signal issued by the main controller and sending the synchronous trigger signal to the second FPGA control unit as a synchronous pulse signal; the multi-path high-precision ADC unit is used for collecting current and voltage data in the power unit cabinet and sending the current and voltage data to the second FPGA control unit; the RS485 communication unit is used for communicating with a PLC in the power unit cabinet and sending temperature data and relay protection state data uploaded by the PLC to the second FPGA control unit; the second SFP + communication unit is used for gradually forwarding all data in the current-level slave controller and all data to be uploaded by the subordinate slave controllers until the data reach the master controller, sending given data issued by the master controller to the second FPGA control unit, sending a switching-on/off and reset command to a PLC (programmable logic controller) in the power unit cabinet through the RS485 communication unit by the second FPGA control unit, converting current given data issued by the master controller into a plurality of paths of PWM (pulse width modulation) driving signals, and then sending the signals to an IGBT (insulated gate bipolar translator) driving circuit in the power unit cabinet through the plurality of paths of PWM driving units.
Furthermore, the slave controller adopts a GTX bus to carry out data communication with the second SFP + communication unit, the RS485 communication unit, the multi-path PWM driver unit, the multi-path high-precision ADC unit and the second HFBR synchronous trigger unit.
Wherein, GTP and GTX are both FPGA high-speed serial transceivers of xilinx company. The difference is that GTP and GTX correspond to the physical interfaces of high-speed communication of different speed classes, respectively. All the modules support full duplex communication, the receiving and transmitting directions are composed of PMA and PCS, and PCS provides rich physical coding layer characteristics and uses 8b/10b coding; the PMA section is an analog circuit providing high performance serial interface characteristics. The bus protocol comprises a time synchronization unit, a polling and series mode conversion unit, a bus alignment unit, a data verification unit, a data series unit and a bus time sequence control unit.
Further, in the slave controller, the second SFP + communication unit includes two SFP + transceivers, which are respectively responsible for optical communication with the master controller and the next-stage slave controller.
Furthermore, in the slave controller, the second HFBR synchronization triggering unit adopts an HFBR-2412TZ interface unit, and is configured to receive a synchronization pulse signal sent by the master controller, where the received synchronization pulse signal is used as a start signal for various pulse power supply pulsing of the synchrotron.
Further, from the controller, the multichannel high-precision ADC unit includes one or two ADC acquisition boards.
Furthermore, each power unit cabinet is a high-precision constant current source and comprises an IGBT (insulated gate bipolar transistor) driving circuit, a PLC and a sensor. The IGBT driving circuit is used for controlling the on and off of the IGBT so as to control the output current; the sensor comprises a DCCT sensor, a voltage sensor and a temperature sensor, wherein the DCCT sensor is used for sampling current data and sending the sampled current data to the multi-channel high-precision ADC unit in the slave controller; the voltage sensor is used for sampling voltage data and sending the sampled current data to the multi-channel high-precision ADC unit in the slave controller; the multi-path high-precision ADC unit converts the received current and voltage data into digital quantity and sends the digital quantity to the second FPGA control unit; the temperature sensor is used for collecting temperature data of the power unit, and after the temperature data collected by the temperature sensor is sampled by the PLC, relay protection state data latched by the PLC are communicated and sent to the second FPGA control unit through the RS485 communication unit in the slave controller.
Furthermore, the communication optical fiber between the main controller and the branch of the slave controller is a multimode optical fiber, and the multimode optical fiber can realize long-distance connection within 300M.
As shown in fig. 2, the present invention further provides an excitation power control method based on an SFP + multi-module accelerator, which includes the following steps:
1) the upper computer and the debugging computer send the configuration information, the initialization instruction and the self-checking instruction of the controller to the main controller, and the main controller sends the corresponding instruction to the corresponding slave controller.
2) And each slave controller completes initialization, configuration and self-checking of the controller according to the received configuration information, initialization instructions and self-checking instructions of the controller, sends self-checking results to the master controller, and reports the self-checking results to an upper computer through the master controller.
3) In each preset period, the main controller continuously inquires the current and voltage data of the power unit cabinet corresponding to the current and voltage data acquired by each slave controller, performs closed-loop regulation according to the current data acquired by inquiry, acquires current given data and then sends the current given data to the corresponding slave controller, and meanwhile, the main controller extracts a startup and shutdown and reset instruction sent by the upper computer from the command buffer area and sends the instruction to the slave controller. The preset period is set to 0.4 second in the present invention.
4) And each slave controller sends the received on-off and reset instructions to a PLC in the power unit cabinet, converts the received current given data into a plurality of paths of PWM driving signals and sends the signals to an IGBT driving circuit in the power unit cabinet.
5) After each preset period is finished, the main controller inquires the relay protection state data and the temperature data of the power unit cabinet, which are received from the controllers and correspond to the controllers, once, and sends the relay protection state data and the temperature data to the main controller and then to the upper computer for displaying.
In the step 1), the controller configuration information includes the number of ADC acquisition boards in the multiple high-precision ADC units used by each slave controller and sampling configuration information, where the sampling configuration information mainly includes filter cut-off frequency, integration step length, output maximum, and output minimum; the self-checking instruction comprises RS485 self-checking, ADC self-checking and SFP + self-checking.
In the step 2), the self-checking method performed by the slave controller comprises the following steps:
when an RS485 or SFP self-checking command is received, the corresponding slave controller starts to carry out self-checking test, firstly, test data is sent to a PLC in a power balancing unit cabinet through an RS485 communication unit or to a master controller through a second SFP + communication unit, if the opposite side receives and returns the corresponding data, the communication is normal, otherwise, the test data is sent again, if the opposite side receives and returns the corresponding data, the communication is normal, otherwise, the communication self-checking error is reported;
when receiving an ADC self-checking command, a plurality of paths of high-precision ADC units in the corresponding slave controllers sample a set value in a null mode and send the set value to the master controller, if the master controller returns corresponding data, the acquisition is normal, if the data returned to the master controller is wrong, the set value is sent again, and if correct data are not responded, the ADC self-checking error is reported.
In the step 3), the length of each path of ADC data received from the controller is 32 bits.
In the step 4), the information length of the relay protection state data sent by the PLC in the power balance unit cabinet is 32 bits, and the lengths of the power on/off command and the reset command issued by the main controller are both 20 bits; each power cabinet supports at most 31 paths of temperature data, and the length of each path of temperature data is 1 byte.
In the above steps 1) to 4), as shown in fig. 3, when the slave controller and the master controller perform data transmission by using the SFP + communication unit, the SFP + data transmission frame format is: bus data hold K28.4 code, data to trigger code K28.5, clock alignment signal bit, data packets 1-15, bus data hold K28.4 code. Wherein each position has the following functions:
the bus data at the forefront keeps K28.4 codes for carrying out bit alignment of transmission data, and when the data arrives, K28.5 codes are triggered for carrying out clock alignment of the data; the clock alignment signal bit is equivalent to the start bit of the data bit, and the bit contains the information of the transmission mode and has the length of 32 bits; the data packet has 15 units, the length of each unit is 32 bits, wherein the first 20 bits are data, the middle 4 bits are the serial number of the slave controller, the last 8 bits are data check bits, and the data check bits use a polynomial according to CRC 8: x8+ x5+ x4+1 (binary: 100110001) for calculation; wherein, the data packet 1 is header data, which includes instruction information, branch numbers and slave controller numbers; data packet 15 is followed by a bus data hold K28.4 code, the bits being used to perform bit alignment of the transmitted data.
In the foregoing steps 1) to 4), as shown in fig. 4, when data transmission is performed between the master controller and the slave controller, data verification needs to be performed on the received data, and the method includes:
when an RX port of the SFP + receives a clock alignment signal, the 15 data packets are sequentially checked one by one, firstly, a sequence number bit is checked, the bit is from 1 to 15 according to hexadecimal number, the bits respectively correspond to the 15 data packets, and the method is mainly used for serial and parallel connection of each slave controller data; then CRC check is carried out, and the data frame is discarded as long as one data packet fails to check. When the main controller sends the command, the command is sent again because the data is discarded and not refreshed, and if the command is not refreshed, the command is reported to the upper computer. Finally, after the data is checked that the data packet 15 is all correct, the total 300bit data is stored in the register.
In the above steps 1) to 4), as shown in fig. 5a and 5b, the data concatenation and polling modes are introduced as follows:
and judging whether the data sent to the master controller is sent in series once or sent in a polling mode according to the clock alignment signal and the data packet 1 (because the types and the lengths of the transmitted data are different, when a communication protocol is formulated, the data are sent in series less than 300 bits according to the polling mode when the sum of the data sent by the slave controllers once exceeds 300 bits).
When the serial data are sent, the master controller sends a data query instruction, each slave controller forwards the data query instruction until the last slave controller, and the serial data are waited after the data query instruction is forwarded. Because the number of the ADC sampling plates mounted on each slave controller is different (one or two ADC sampling plates), namely the length of data sent by each slave controller is different, when data are uploaded according to a customized communication protocol, each slave controller puts the data into a data packet with a corresponding serial number, and sends the data sent by the slave controller with the previous serial number to the slave controller with the next serial number after the data are serially connected into the slave controller with the previous serial number until the master controller.
When polling is sent, the master controller sends a data query instruction to each slave controller independently, and according to the content in the data packet 1, the slave controllers do not process and only do instruction forwarding when the corresponding serial numbers are not queried. And uploading data until the corresponding slave controllers receive the data query instruction, and in the data uploading process, other slave controllers do not process the data after receiving the uploaded data, and only do data uploading until the master controller receives the corresponding data.
Example one
In this embodiment, the master controller includes a core board and a backplane. The core board comprises a Kintex-7 FPGA chip, a first SDRAM memory chip, a first FLASH memory chip, a TMS320C6678 DSP chip, a second SDRAM memory chip and a second FLASH memory chip. The bottom plate comprises an RJ45 remote control interface, an RS232 debugging interface, an HFBR-1414TZ interface, three SFP + light receivers connected in parallel and the like.
The first FPGA chip is communicated with an upper computer through an RJ45 network interface; the debugging interface is connected with a debugging computer through an RS232 debugging interface and is used for configuring the parameters of the controller; the contents such as read-back data, given data, sending instructions, sending parameters, temperature data, relay protection data and the like are saved by reading and writing the first FILSH memory chip; the contents such as read-back data, given data, sending instructions, sending parameters, temperature data, relay protection data and the like are saved by reading and writing the first SDRAM memory chip; data transmission between each sub-controller branch and each SFP + optical receiver is realized; sending synchronous trigger signals to each slave controller through an HFBR-1414TZ optical interface to realize trigger pulse current enabling; the system is connected with the DSP chip through an SRIO bus; the DSP chip realizes the storage of contents such as readback data, given data, sending instructions, sending parameters, temperature data, relay protection data and the like by reading and writing the second FLASH memory chip; and the storage of data before and after data processing is realized by reading and writing the second SDRAM memory chip.
The slave controller is divided into a core board, an expansion board, a bottom board and an ADC sampling board, wherein the core board is provided with an Artix-7 FPGA chip, and the bottom board is provided with two SFP + optical transceivers, an RS485 interface and an HFBR-2412TZ optical interface; two ADC sampling boards and an RS485 interface can be inserted into the expansion board, and the ADC sampling boards adopt AD763418 bit analog-to-digital converters. The Artix-7 FPGA chip performs data transmission with the master controller and the other slave controller through the two SFP + optical transceivers; receiving a synchronous trigger signal sent by a main controller through an HFBR-2412TZ optical interface to realize synchronous triggering of each power unit; the ADC sampling board on the expansion board is used for collecting current and voltage data in the power unit cabinet, and the RS485 interface is used for receiving relay protection state data and temperature data uploaded by the PLC; the Artix-7 FPGA chip reads the received RS485 and ADC read-back data and sends the data to the main controller, and generates PWM driving signals according to current given signals sent by the main controller, and the PWM driving signals are sent to the IGBT driving circuit in the power unit cabinet through the multi-path PWM driving unit.
The SFP + driver of the power control system selects a programmable crystal oscillator chip to generate a pair of 125Mhz differential clocks as a reference clock, and uses a 25Mhz crystal oscillator frequency-doubled 156.25Mhz clock as a data operation clock, wherein the width of the received and transmitted data is 32 bits. After passing through the SERDES deserializer, the data transmission rate at the optical fiber end is 5 Gbps. The encoding and decoding use an 8b/10b scheme. The main controller part provides 15 groups of 20bit output and 15 groups of 20bit input data ports, when the output enable signal is high level, the data can be sent. When the input enable is high, it represents that the new data reception is completed. The received data can be read at this time; the slave controller part SFP + driving program also provides 15 groups of 20bit output and 15 groups of 20bit input data ports, and when the output enable signal is in high level, the sending data can be sent. When the input enable is high, it represents that the new data reception is completed. The received data can be read at this time. In addition, the slave controller SFP + driving program has two functions, namely, when the power-on initialization is carried out, after the information of the branch number of the master controller and the number of the slave controllers is received, the branch number and the number of the slave controllers are subtracted by 1 and then sent to the next slave controller until the number of the controller reaches the number 1, and therefore the number distribution is automatically completed. Another function is to begin analyzing the data type, data transfer direction, and transfer mode in response to receiving a clock signal thereto.
In summary, the multi-mode SFP + optical fiber communication power control system adopted in the invention has the advantages of large bandwidth, large capacity, low transmission loss, high speed, long transmission distance, strong electromagnetic interference resistance, good insulation, no crosstalk, high confidentiality and the like, compared with the traditional electrical signal communication. The method provides important guarantee of high speed, high reliability and stability for the communication of the multi-module excitation power supply control system.
A specific embodiment is given above, but the invention is not limited to the described embodiment. The basic idea of the present invention lies in the above solution, and it is obvious to those skilled in the art that it is not necessary to spend creative efforts to design various modified models, formulas and parameters according to the teaching of the present invention. Variations, modifications, substitutions and alterations may be made to the embodiments without departing from the principles and spirit of the invention, and still fall within the scope of the invention.
Claims (10)
1. The utility model provides an excitation power supply control system based on SFP + multi-module accelerator, includes control box and a plurality of power unit rack, each power unit rack includes IGBT drive circuit, PLC and sensor, its characterized in that still includes: the main controller is arranged in the control cabinet, and the auxiliary controllers, the upper computer and the debugging computer are arranged in the power unit cabinets;
each slave controller is divided into a plurality of groups, each slave controller in each group is connected in series to form a slave controller branch, and each slave controller branch is connected with the master controller through an optical fiber to form a master-slave control structure;
the master controller is used for configuring the master controller and each slave controller according to control and debugging parameters sent by the upper computer and the debugging computer; each slave controller is used for acquiring data of the power unit cabinet connected with the slave controller and sending the data to the master controller; and the master controller processes the data collected by each slave controller and then sends a control instruction to the corresponding slave controller, and the slave controller processes the control instruction and then sends the control instruction to the corresponding power unit cabinet.
2. The SFP + multi-module accelerator-based excitation power control system of claim 1, wherein: the main controller comprises a first FPGA control unit, a DSP operation unit, an RJ45 network interface unit, an RS232 debugging interface unit, a first HFBR synchronous trigger unit, a first storage unit, a first SFP + communication unit and a second storage unit;
the first FPGA control unit is communicated with the upper computer through the RJ45 network interface unit to realize power on/off, state detection and current setting control;
the RS232 debugging interface unit is connected with a debugging computer to realize parameter configuration and fault diagnosis of the master controller and each slave controller;
data storage is realized by reading and writing the first storage unit;
sending a synchronous trigger signal to each slave controller branch circuit through the first HFBR synchronous trigger unit to realize trigger pulse current enabling;
data transmission between the first SFP + communication unit and each slave branch is achieved, and the data transmission comprises receiving data collected by each slave branch and sending a control instruction obtained by calculation of the DSP operation unit to each slave branch;
and the DSP operation unit is connected with the second storage unit, realizes current closed-loop regulation and vector rectification algorithm, and stores data before and after data processing.
3. The SFP + multi-module accelerator-based excitation power control system of claim 2, wherein: the first SFP + communication unit comprises three SFP + transceivers connected in parallel, and the SFP + transceivers adopt optical transceivers with 850nm wavelength and support the highest 10 Gbps.
4. The SFP + multi-module accelerator-based excitation power control system of claim 1, wherein: at least one slave controller branch is arranged, and the number of the slave controllers arranged on each slave controller branch is at most 6.
5. The SFP + multi-module accelerator-based excitation power control system of claim 1, wherein: the slave controller comprises a second FPGA control unit, a second SFP + communication unit, an RS485 communication unit, a multi-path PWM driver unit, a multi-path ADC unit and a second HFBR synchronous trigger unit;
the second HFBR synchronous trigger unit is used for receiving a synchronous trigger signal issued by the main controller and sending the synchronous trigger signal to the second FPGA control unit as a synchronous pulse signal;
the multi-channel ADC unit is used for collecting current and voltage data in the power unit cabinet and sending the current and voltage data to the second FPGA control unit;
the RS485 communication unit is used for communicating with the PLC in the power unit cabinet and sending temperature data and relay protection state data uploaded by the PLC to the second FPGA control unit;
the second SFP + communication unit is used for gradually forwarding all data in the current-level slave controller and all data to be uploaded by the subordinate slave controllers until the data reach the master controller, sending given data issued by the master controller to the second FPGA control unit, sending a switching-on/off and reset command to a PLC in the power unit cabinet through the RS485 communication unit by the second FPGA control unit, converting current given data issued by the master controller into a multi-path PWM driving signal, and then sending the multi-path PWM driving signal to an IGBT driving circuit in the power unit cabinet through the multi-path PWM driver unit.
6. The SFP + multi-module accelerator-based excitation power control system of claim 1, wherein: the communication optical fiber between the main controller and the branch of the slave controller is a multimode optical fiber, and the multimode optical fiber can realize long-distance connection within 300M.
7. An excitation power supply control method based on an SFP + multi-module accelerator by adopting the system as claimed in any one of claims 1 to 6, which is characterized by comprising the following steps:
1) the upper computer sends the controller configuration information, the initialization instruction and the self-checking instruction to the main controller, and the main controller sends the corresponding instruction to the corresponding slave controller;
2) each slave controller completes initialization, configuration and self-checking of the slave controller according to the received controller configuration information, initialization instructions and self-checking instructions, sends self-checking results to the master controller, and reports the self-checking results to an upper computer by the master controller;
3) in each preset period, the main controller continuously inquires the current and voltage data of the power unit cabinet corresponding to the current and voltage data acquired by each slave controller, performs closed-loop regulation according to the current data acquired by inquiry, acquires current given data and then sends the current given data to the corresponding slave controller, and meanwhile, the main controller extracts a startup and shutdown and reset instruction sent by an upper computer from a command buffer area and sends the instruction to the slave controller;
4) each slave controller sends the received on-off and reset instructions to a PLC in the power unit cabinet, converts the received current given data into a plurality of paths of PWM driving signals and sends the signals to an IGBT driving circuit in the power unit cabinet;
5) after each preset period is finished, the main controller inquires the relay protection state data and the temperature data of the power unit cabinet, which are received from the controllers and correspond to the controllers, once, and sends the relay protection state data and the temperature data to the main controller and then to an upper computer for displaying.
8. The SFP + multi-module accelerator-based excitation power supply control method according to claim 7, wherein: in the step 2), the self-checking method performed by the slave controller comprises the following steps:
when an RS485 or SFP self-checking command is received, the corresponding slave controller starts to carry out self-checking test, firstly, test data is sent to a PLC in a power balancing unit cabinet through an RS485 communication unit or to a master controller through a second SFP + communication unit, if the opposite side receives and returns the corresponding data, the communication is normal, otherwise, the test data is sent again, if the opposite side receives and returns the corresponding data, the communication is normal, otherwise, the communication self-checking error is reported;
when an ADC self-checking command is received, a plurality of paths of high-precision ADC units in the corresponding slave controllers sample a set value in a null mode and send the set value to the master controller, if the master controller returns corresponding data, the acquisition is normal, if the data is wrong, the set value is sent again, and if the data is still not answered correctly, the ADC self-checking error is reported.
9. The SFP + multi-module accelerator-based excitation power supply control method according to claim 7, wherein: when the slave controller and the master controller carry out data communication, the adopted SFP + data transmission frame format comprises the following steps:
the first bus data holds K28.4 code for bit alignment of the transmitted data;
a data arrival trigger code K28.5 used for clock alignment of data;
the clock aligns the signal bit, is equivalent to the initial bit of the data bit, and this bit has included the information of the transmission mode, the length is 32 bits;
the length of each data packet is 32 bits, wherein the first 20 bits are data, the middle 4 bits are serial numbers of the slave controllers, the last 8 bits are data check bits, and the data check bits use a polynomial according to CRC 8: x8+ x5+ x4+ 1; the first data packet is header data which comprises instruction information, branch numbers and slave controller numbers;
the second bus data holds the K28.4 code for bit alignment of the transmitted data.
10. The SFP + multi-module accelerator-based excitation power supply control method according to claim 9, wherein: when the slave controller and the master controller carry out data communication, judging whether the slave controller sends data to the master controller in a serial transmission mode or a polling transmission mode according to a clock alignment signal position in a query instruction sent by the master controller and the first data packet;
when the serial data are transmitted, firstly, the master controller transmits a data query instruction, each slave controller transmits the data query instruction to the last slave controller, and the serial data are waited after the data query instruction is transmitted; then, when data are uploaded according to a preset communication protocol, each slave controller puts the data into a data packet with a corresponding serial number, and transmits the data packet transmitted by the slave controller with the previous serial number to the slave controller with the next serial number after the data packet is serially connected to the master controller;
when polling is sent, the master controller sends a data query instruction to each slave controller independently, each slave controller judges whether the data query instruction is the instruction of the slave controller according to the content in the first data packet, when the data query instruction is not a corresponding sequence number, the data query instruction is not processed, only the instruction is forwarded until the slave controller corresponding to the data query instruction uploads data, and in the process of uploading data, other slave controllers do not process the data after receiving the uploaded data, and only the data are uploaded until the master controller receives corresponding query data.
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| CN114047714A (en) * | 2021-09-27 | 2022-02-15 | 中天海洋系统有限公司 | Multiprocessor cooperative control system and method |
| CN115484219A (en) * | 2022-08-23 | 2022-12-16 | 中国电子科技集团公司第十研究所 | Method, equipment and medium for avoiding port association of domestic SRIO (serial-to-input/output) switching chip |
| CN115484219B (en) * | 2022-08-23 | 2023-06-27 | 中国电子科技集团公司第十研究所 | Method, equipment and medium for avoiding port association of domestic SRIO exchange chip |
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