CN115484219A - Method, equipment and medium for avoiding port association of domestic SRIO (serial-to-input/output) switching chip - Google Patents
Method, equipment and medium for avoiding port association of domestic SRIO (serial-to-input/output) switching chip Download PDFInfo
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- CN115484219A CN115484219A CN202211011225.8A CN202211011225A CN115484219A CN 115484219 A CN115484219 A CN 115484219A CN 202211011225 A CN202211011225 A CN 202211011225A CN 115484219 A CN115484219 A CN 115484219A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/55—Prevention, detection or correction of errors
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The invention discloses a method, equipment and medium for avoiding port association of a domestic SRIO switching chip, belonging to the field of SRIO networks and comprising the following steps: according to RIO Port Error and Status CSR register state bars of all ports of a domestic SRIO switching chip, enabling of Port events is set respectively and used for detecting power-down and power-up events of RIO nodes. The invention avoids the correlation condition of the SRIO switching chip port event and increases the reliability.
Description
Technical Field
The invention relates to the field of SRIO networks, in particular to a method, equipment and a medium for avoiding port association of a domestic SRIO switching chip.
Background
RapidIO is a high performance, low pin count, packet switch based interconnect technology pioneered by companies such as Motorola and Mercury. The method has the advantages of strong flexibility, simple protocol layer and low system overhead, and meets the rapid development of the embedded system. The high-speed transmission of RapidIO technology between chips and modules makes the RapidIO technology widely applied to integrated electronic information systems.
At present, a comprehensive electronic information system mainly comprises a general Data Processing Module (DPM), a general Signal Processing Module (SPM), a network switching module (RCM), an IO module and the like, and a rapid IO interconnection bus protocol is adopted between chips and between boards to realize high-reliability data transmission. One or more domestic SRIO switching chips are arranged in the network switching module, the IO module and the data processing module to form a RapidIO network transmission frame.
The SRIO nodes in the integrated electronic information system have the conditions of dynamic network access and network exit, and are similar to the timely access and timely use scene in the Ethernet. The dynamic network access and network exit of the SRIO node are realized by the detection of an event through a domestic SRIO exchange chip port in a network exchange module. Reporting port-write packets through each port of a domestic SRIO switching chip, and correspondingly processing reported events by a main control module so as to complete the management of the whole RapidIO network node.
Whether the port of the domestic SRIO switch chip can report the corresponding port-write packet or not is that the relevant register of each port of each domestic SRIO switch chip needs to be set to be capable through the main control module in the process of scanning the whole RapidIO network node. Under the normal condition, checking a state bar of a domestic SRIO switch chip RIO Port Error and Status CSR register, if the state bar is in a PORT _ OK state, configuring an IDT _ LANE _ ERR _ REPORT _ EN register, enabling a LANE event, and detecting a RIO node power-down event; if the state of PORT _ UNINICAL is present, the register of PORT _ {0..17} _ OPS and PORT _ n _ ERROR _ REPORT _ ENABLE _ CSR is used to ENABLE the PORT event, so as to detect the power-on event of RIO node. At present, the prior art has the technical problems of influence on the processing of a main control module and poor reliability caused by the port event correlation of a domestic SRIO switching chip.
Disclosure of Invention
The invention aims to overcome the defects of the prior art, provides a method, equipment and a medium for avoiding the correlation of ports of a domestic SRIO switching chip, avoids the correlation of SRIO switching chip ports and increases the reliability.
The purpose of the invention is realized by the following scheme:
a method for avoiding port association of a domestic SRIO switching chip comprises the following steps:
according to RIO Port Error and Status CSR register state bars of all ports of a domestic SRIO switching chip, enabling of Port events is set respectively and used for detecting power-down and power-up events of RIO nodes.
Furthermore, different event enables are set for different ports, so that the home-made SRIO switch chip port can correctly identify the RIO nodes powered down and powered up in real time, and the event correlation of the SRIO switch chip port is avoided.
Further, the setting of the enabling of the Port event according to the RIO Port Error and Status CSR register Status bars of all ports of the domestic SRIO switch chip respectively comprises the following substeps:
s1, detecting RIO Port Error and Status CSR registers of all ports of a domestic SRIO switching chip;
s2, if the RIO Port Error and Status CSR register is in the state of PORT _ UNINITAL, setting a PORT _ {0..17} _ OPS register and a PORT _ n _ ERROR _ REPORT _ ENABLE _ CSR register, enabling a Port event, and detecting a power-on event of the RIO node; if the RIO Port Error and Status CSR register is the state of PORT _ OK, then the Port number of the SRIO exchange chip is judged and corresponding processing is carried out.
Further, the step of judging the port number of the SRIO switching chip and performing corresponding processing includes the substeps of: if the SRIO switch chip port numbers are 8, 9 and 17, an IDT _ LANE _ ERR _ REPORT _ EN register is set, and LANE events are enabled.
Further, the step of judging the port number of the SRIO switching chip and performing corresponding processing includes the substeps of: if the switching chip is other PORTs, setting a PORT _ {0..17} _ OPS register and a PORT _ n _ ERROR _ REPORT _ ENABLE _ CSR register, enabling the PORT event, and detecting the RIO node power-down event.
Further, the other ports are other ports than 8, 9 and 17.
Further, the domestic SRIO switching chip forms an SRIO network.
Furthermore, the SRIO network also comprises a plurality of SRIO domestic exchange boards, and the SRIO domestic exchange boards are connected in pairs to complete SRIO networking communication.
A computer device comprising a processor and a memory, the memory having stored therein a computer program which, when loaded by the processor and executed, carries out the method of any preceding claim.
A readable storage medium, in which a computer program is stored, which computer program is loaded by a processor and executes a method according to any of the above.
The beneficial effects of the invention include:
the invention provides a method for avoiding correlation of port events of a domestic SRIO switching chip.
According to RIO Port Error and Status CSR register state bars of all ports of a domestic SRIO switching chip, the enabling of Port events are respectively set for detecting power-down and power-up events of RIO nodes. Due to the limitation of the SRIO switch chip, the event correlation report of some ports is caused, which affects the processing of the main control module. The invention avoids the correlation of the SRIO switching chip port events by enabling different registers of different ports.
The invention has the advantages of high reliability: different event enables are set for different ports of the domestic SRIO switch chip port, the domestic SRIO switch chip port can correctly identify the RIO nodes of power failure and power up in real time, and reliability is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic diagram of an event correlation for avoiding a port of a domestic SRIO switch chip according to an embodiment of the present invention.
Detailed Description
All features disclosed in all embodiments in this specification, or all methods or process steps implicitly disclosed, may be combined and/or expanded, or substituted, in any way, except for mutually exclusive features and/or steps.
In the actual use process, the inventor of the present invention found the following technical problems: the domestic SRIO switching chip is externally connected with three data processing modules, wherein two RIO nodes in the data processing module 1 are respectively connected with the ports 9 and 17, two RIO nodes in the data processing module 2 are respectively connected with the ports 2 and 14, and two RIO nodes in the data processing module 3 are respectively connected with the ports 1 and 13. If the module 1 is powered down, it is found that the SRIO switch chip port corresponding to the module 3 also reports a power down event, and if the module 1 is powered down, the SRIO switch chip port 17 reports an event, and the port 9 does not report an event. The event correlation reported by the ports of the domestic SRIO switching chip influences the management of the whole RapidIO network by the main control module.
The invention provides a method for avoiding the correlation of a domestic SRIO switch chip port event aiming at the technical problem of the correlation of the domestic SRIO switch chip port event in an SRIO communication network, which comprises the following steps:
s1, detecting RIO Port Error and Status CSR registers of all ports of a domestic SRIO switching chip;
s2, if the RIO Port Error and Status CSR is registered as the state of Port _ UNINICAL, setting a Port _ {0..17} _ OPS and a Port _ n _ ERROR _ REPORT _ ENABLE _ CSR register, enabling a Port event and detecting a power-on event of the RIO node.
If the RIO Port Error and Status CSR register is the state of PORT _ OK, then the SRIO exchange chip Port number is determined. If the port numbers of the SRIO switching chips are 8, 9 and 17, setting an IDT _ LANE _ ERR _ REPORT _ EN register to enable a LANE event; if the PORTs are other PORTs of the switching chip, a register of PORT _ {0..17} _ OPS and PORT _ n _ ERROR _ REPORT _ ENABLE _ CSR is set, and the PORT event is enabled, so that the RIO node power-down event can be detected.
Example 1
A method for avoiding port association of a domestic SRIO switching chip comprises the following steps:
according to RIO Port Error and Status CSR register state bars of all ports of the domestic SRIO switching chip, enabling of Port events is set respectively and used for detecting power-down and power-up events of RIO nodes.
Example 2
On the basis of the embodiment 1, by setting different event enables for different ports, the ports of the domestic SRIO switch chip can correctly and real-timely identify the RIO nodes which are powered off and on, and the event correlation of the ports of the SRIO switch chip is avoided.
Example 3
On the basis of the embodiment 1, the respectively setting the enabling of the Port event according to the RIO Port Error and Status CSR register state bars of all ports of the domestic SRIO switching chip comprises the following substeps:
s1, detecting RIO Port Error and Status CSR registers of all ports of a domestic SRIO switching chip;
s2, if the RIO Port Error and Status CSR is registered as the state of PORT _ UNINITAL, setting a PORT _ {0..17} _ OPS, PORT _ n _ ERROR _ REPORT _ ENABLE _ CSR register, enabling a Port event, and detecting a power-on event of the RIO node; if the RIO Port Error and Status CSR register is the state of PORT _ OK, then the Port number of the SRIO exchange chip is judged and corresponding processing is carried out.
Example 4
On the basis of embodiment 1, the step of judging the port number of the SRIO switching chip and performing corresponding processing includes the substeps of: if the SRIO switch chip port numbers are 8, 9 and 17, an IDT _ LANE _ ERR _ REPORT _ EN register is set, and LANE events are enabled.
Example 5
On the basis of embodiment 4, the step of determining the SRIO switching chip port number and performing corresponding processing includes the substeps of: if the switching chip is other PORTs, setting a PORT _ {0..17} _ OPS register and a PORT _ n _ ERROR _ REPORT _ ENABLE _ CSR register, enabling the PORT event, and detecting the RIO node power-down event.
Example 6
On the basis of embodiment 5, the other ports are other ports than 8, 9 and 17.
Example 7
On the basis of the embodiment 1, the domestic SRIO switching chip forms an SRIO network.
Example 8
On the basis of the embodiment 7, the SRIO network further includes a plurality of SRIO home switch boards, and the SRIO home switch boards are connected two by two to complete SRIO networking communication.
Example 9
A computer device comprising a processor and a memory, the memory having stored therein a computer program which, when loaded by the processor, performs the method of any of embodiments 1 to 8.
Example 10
A readable storage medium, in which a computer program is stored, which computer program is loaded by a processor and executes a method according to any of embodiments 1-8.
The units described in the embodiments of the present invention may be implemented by software, or may be implemented by hardware, and the described units may also be disposed in a processor. Wherein the names of the elements do not in some way constitute a limitation on the elements themselves.
According to an aspect of the application, there is provided a computer program product or computer program comprising computer instructions stored in a computer readable storage medium. The processor of the computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device executes the method provided in the above-mentioned various alternative implementation modes.
As another aspect, the present application also provides a computer-readable medium, which may be contained in the electronic device described in the above embodiment; or may be separate and not incorporated into the electronic device. The computer readable medium carries one or more programs which, when executed by an electronic device, cause the electronic device to implement the method described in the above embodiments.
The parts not involved in the present invention are the same as or can be implemented using the prior art.
The above-described embodiments are intended to be illustrative only, and various modifications and variations such as those described in the above-described embodiments of the invention may be readily made by those skilled in the art based upon the teachings and teachings of the present invention without departing from the spirit and scope of the invention.
Other embodiments than the above examples may be devised by those skilled in the art based on the foregoing disclosure, or by adapting and using knowledge or techniques of the relevant art, and features of various embodiments may be interchanged or substituted and such modifications and variations that may be made by those skilled in the art without departing from the spirit and scope of the present invention are intended to be within the scope of the following claims.
Claims (10)
1. A method for avoiding port association of a domestic SRIO switching chip is characterized by comprising the following steps:
according to RIO Port Error and Status CSR register state bars of all ports of the domestic SRIO switching chip, enabling of Port events is set respectively and used for detecting power-down and power-up events of RIO nodes.
2. The method for avoiding the correlation of the ports of the domestic SRIO switch chips as claimed in claim 1, wherein different event enables are set for different ports, so that the domestic SRIO switch chip ports can correctly identify RIO nodes with power down and power up in real time, and the correlation of the SRIO switch chip ports events is avoided.
3. The method for avoiding Port association of a domestic SRIO switch chip as claimed in claim 1, wherein said setting the enabling of Port events according to the RIO Port Error and Status CSR register Status bars of all ports of the domestic SRIO switch chip respectively comprises the sub-steps of:
s1, detecting RIO Port Error and Status CSR registers of all ports of a domestic SRIO switching chip;
s2, if the RIO Port Error and Status CSR is registered as the state of PORT _ UNINITAL, setting a PORT _ {0..17} _ OPS, PORT _ n _ ERROR _ REPORT _ ENABLE _ CSR register, enabling a Port event, and detecting a power-on event of the RIO node; if the RIO Port Error and Status CSR register is the state of PORT _ OK, then the Port number of the SRIO exchange chip is judged and corresponding processing is carried out.
4. The method for avoiding port association of a domestic SRIO switch chip as claimed in claim 1, wherein the step of judging the port number of the SRIO switch chip and performing corresponding processing comprises the substeps of: if the SRIO switch chip port numbers are 8, 9 and 17, an IDT _ LANE _ ERR _ REPORT _ EN register is set, and a LANE event is enabled.
5. The method for avoiding port association of a domestic SRIO switch chip as claimed in claim 4, wherein the step of judging the port number of the SRIO switch chip and performing corresponding processing comprises the substeps of: if the switching chip is other PORTs, setting a PORT _ {0..17} _ OPS register and a PORT _ n _ ERROR _ REPORT _ ENABLE _ CSR register, enabling the PORT event, and detecting the RIO node power-down event.
6. The method for circumventing port association of a domestic SRIO switch chip as claimed in claim 5, wherein the other ports are other than 8, 9, 17.
7. The method for avoiding port association of a homemade SRIO switch chip as claimed in claim 1, wherein the homemade SRIO switch chip constitutes an SRIO network.
8. The method for avoiding port association of home-made SRIO switch chips of claim 7, wherein the SRIO network further comprises a plurality of SRIO home-made switch boards, and the SRIO home-made switch boards are connected two by two to complete SRIO networking communication.
9. A computer arrangement, characterized in that the computer arrangement comprises a processor and a memory, in which a computer program is stored which, when loaded by the processor, carries out the method according to any one of claims 1-8.
10. A readable storage medium, in which a computer program is stored which is loaded by a processor and which performs the method according to any one of claims 1 to 8.
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