CN111600583B - Random frequency triangular wave generator based on diffusion memristor and current transmitter - Google Patents
Random frequency triangular wave generator based on diffusion memristor and current transmitter Download PDFInfo
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- CN111600583B CN111600583B CN202010491699.1A CN202010491699A CN111600583B CN 111600583 B CN111600583 B CN 111600583B CN 202010491699 A CN202010491699 A CN 202010491699A CN 111600583 B CN111600583 B CN 111600583B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K4/00—Generating pulses having essentially a finite slope or stepped portions
- H03K4/06—Generating pulses having essentially a finite slope or stepped portions having triangular shape
- H03K4/08—Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape
- H03K4/48—Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape using as active elements semiconductor devices
- H03K4/50—Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape using as active elements semiconductor devices in which a sawtooth voltage is produced across a capacitor
- H03K4/501—Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape using as active elements semiconductor devices in which a sawtooth voltage is produced across a capacitor the starting point of the flyback period being determined by the amplitude of the voltage across the capacitor, e.g. by a comparator
- H03K4/502—Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape using as active elements semiconductor devices in which a sawtooth voltage is produced across a capacitor the starting point of the flyback period being determined by the amplitude of the voltage across the capacitor, e.g. by a comparator the capacitor being charged from a constant-current source
Abstract
A random frequency triangular wave generator based on a diffusion memristor and a current transmitter belongs to an integrated circuitThe technical field is as follows. The invention aims to solve the problems of complex circuit and high design difficulty of the conventional random frequency triangular carrier wave generator due to the use of a random number generator. The invention comprises a control logic unit, a random delay unit, a delay chain unit, a first register unit, a second register unit, a current transmitter, N NMOS tubes M 1 To M N Capacitor array and comparator U 1 And a resistor R A And a resistor R B And a resistance R X (ii) a The constant charge-discharge current is provided by using the current transmitter, the random delay time of the diffusion memristor is encoded by using a time interval measurement technology, and the obtained random thermometer code is used for controlling the size of a charge-discharge capacitor, so that a constant-amplitude triangular wave with a period and a frequency which are randomly changed is obtained. The invention is mainly applied to the random PWM technology.
Description
Technical Field
The invention belongs to the technical field of integrated circuits.
Background
The application of Pulse Width Modulation (Pulse Width Modulation) technology is very critical in power control and conversion integrated circuits such as switching power supplies and motor drives. Conventional PWM control signals are generated by comparing a fixed frequency triangular or sawtooth carrier signal with an error signal and then utilized to control the on-time of the switching device over a fixed period to achieve a timely response to load variations. Research shows that the conventional PWM technology has a large harmonic component near the switching frequency and an integral multiple of the switching frequency, which may cause many adverse effects to the system, such as causing a great amount of electromagnetic noise interference, causing distortion of voltage and current waveforms, and even causing abnormal operation of the subsequent devices.
For the occasion that the carrier frequency must be limited to a lower frequency, the problems of electromagnetic interference and the like caused by the conventional PWM technology can be better solved by adopting the random PWM technology. The random PWM technology disperses the energy of harmonic frequency spectrum which is intensively distributed at the switching frequency and the frequency multiplication position thereof by randomly changing the carrier frequency under the premise of ensuring that the duty ratio is not changed, thereby enabling the electromagnetic noise to be approximately band-limited white noise, and greatly weakening the intensity of colored noise which is characterized by fixing the switching frequency.
In order to achieve the purpose of randomizing the switching frequency, firstly, a carrier signal with randomly changeable frequency is generated, and the random frequency triangular carrier has higher research value because the triangular wave has higher control precision relative to the sawtooth wave and can realize the function of bilateral modulation. Such a triangular carrier wave is required to be a constant-amplitude isosceles triangular wave in each period, but the period thereof is randomly changed. At present, most of the developments of the random frequency triangular carrier wave generator need to use a random number generator for providing randomly changing frequency values, which increases the complexity and design difficulty of the circuit, and therefore, the above problems need to be solved urgently.
Disclosure of Invention
The invention aims to solve the problems of complex circuit and high design difficulty caused by the use of a random number generator in the conventional random frequency triangular carrier wave generator, and provides a random frequency triangular wave generator based on a diffusion memristor and a current transmitter.
A random frequency triangular wave generator based on a diffusion memristor and a current transmitter comprises a control logic unit, a random time delay unit, a time delay chain unit, a first register unit, a second register unit, the current transmitter and N NMOS tubes M 1 To M N Capacitor array and comparator U 1 And a resistor R A And a resistor R B And a resistance R X (ii) a Wherein the capacitor array comprises a capacitor C 0 To C N ；
The control logic unit is used for generating a pulse signal V P0 And simultaneously sending the time delay data to the random time delay unit and the time delay chain unit; the reset circuit is also used for generating a reset signal Rst to reset the delay chain unit; and also for generating a clock signal Clk L Clock control is carried out on the second register unit; and is also used for receiving the pulse signal V output by the random delay unit P1 (ii) a And also for receiving the comparator U 1 Voltage signal V output from output terminal Y ；
The random delay unit is realized by adopting a diffusion memristor and is used for receiving a pulse signal V P0 Processing to obtain pulse signal V P1 And will pulse signal V P1 Simultaneously input to the control logic unit and the first register unit; wherein the pulse signal V P1 And pulse signal V P0 Are equal in period, and the pulse signal V P1 And pulse signal V P0 Are coincident with each other, pulse signal V P0 High level duration t p Is a fixed value, a pulse signal V P1 High level duration t d Is a random value, and t d ＜t p ；
The random delay time of the diffusion memristor is equal to t d ；
A delay chain unit for receiving the pulse signal V P0 Generating an N-bit thermometer code and sending the N-bit thermometer code to a first register unit;
the first register unit receives the pulse signal V P1 At its pulse signal V P1 The falling edge time of the first register unit latches the received N-bit thermometer code and sends the latched result to the second register unit;
the second register unit being responsive to the received clock signal Clk L At its clock signal Clk L The rising edge time of the first register unit latches the latch result output by the first register unit to obtain the N-bit thermometer code d 1 To d N And coding the N-bit thermometer by d 1 To d N Respectively sent to NMOS tubes M 1 To M N The grid electrode controls the corresponding NMOS tube; wherein when d i When =1, represents d i Is high level; when d is i When =0, represents d i Is low level, i =1, 2, 3 \8230, 8230N;
NMOS tube M 1 To M N Source and capacitor C 0 One end of each of the two ends is connected with a power ground;
NMOS tube M 1 To M N Respectively with the capacitor C 1 To C N Is connected to a capacitor C 0 To C N And the other end of the current transmitter, a Z port of the current transmitter and a comparator U 1 Are connected simultaneously, and the voltage signal V of the connection point Cap As a random-frequency triangular carrier signal generated by a triangular carrier generator, and a voltage signal V Cap Is a random frequency isosceles triangular wave signal with equal amplitude;
comparator U 1 Non-inverting input terminal and resistor R A And a resistor R B Are connected at the same time to a resistor R B The other end of the resistor R is connected with a power ground A And the other end of the comparator U 1 Output terminal of current conveyor, Y port of current conveyor and control logicVoltage signal V of cell Y The input ends are connected;
x port and resistor R of current transmitter X Is connected to a resistor R X The other end of the first power supply is connected with a power ground;
comparator U 1 The positive voltage input end is connected with a power supply V DD Comparator U 1 Negative voltage input end is connected with a power supply V SS And V is DD ＝-V SS 。
Preferably, the delay chain unit includes N delay modules, and the N delay modules are cascaded in series, wherein a signal input end of a first delay module is used as the delay chain unit to receive the pulse signal V P0 An input terminal of (1);
each delay module is used for delaying the rising edge of an input signal of the delay module, and delay signal values output by the first to Nth delay modules are respectively used as first to Nth thermometer codes output by the delay chain unit;
the reset signal input end of each delay module is used for receiving a reset signal Rst, and when the reset signal Rst is at a high level, the output states of the N delay modules are reset to be 0.
Preferably, the delay module comprises a not gate Y 1 NOT gate Y 2 NMOS transistor M a And NMOS transistor M b ；
NOT gate Y 1 The input end of the delay module is used as the data signal input end of the delay module;
NOT gate Y 1 Of the output NAND gate Y 2 Is connected to the input terminal of a NOT gate Y 2 Output end of the NMOS transistor M is simultaneously connected with the NMOS transistor M a Drain electrode of (1) and NMOS tube M b After being connected, the grid of the delay module is used as a data signal output end of the delay module;
NMOS tube M a The grid of the delay module is used as a reset signal input end of the delay module;
NMOS tube M a Source electrode of (1) and NMOS tube M b Source electrode and NMOS transistor M b The drains are connected simultaneously and then connected to the power ground.
Preferably, the first register unit includes a not gate Y 3 And N D flip-flops;
NOT gate Y 3 As a first register unit receiving a pulse signal V P1 An input terminal of (1);
NOT gate Y 3 The output end of the D trigger is simultaneously connected with the clock signal input ends of the N D triggers;
d input ends of the first to Nth D triggers are respectively used as input ends of first to Nth thermometer codes of the first register unit;
q output ends of the first to Nth D flip-flops are respectively used as output ends of the first to Nth thermometer codes of the first register unit.
Preferably, the second register unit includes N D flip-flops, and clock signal input terminals of the N D flip-flops are connected at the same time and then serve as a clock signal input terminal of the second register unit;
d input ends of first to Nth D triggers in the second register unit are respectively used as input ends of first to Nth thermometer codes of the second register unit;
q output ends of first to Nth D flip-flops in the second register unit are respectively used as output ends of first to Nth thermometer codes of the second register unit.
Preferably, the random delay unit comprises a level shifter and a diffusion memristor R M Resistance R r Comparator U 2 And an AND gate X1;
the input end of the level shifter is used as the input end of the random time delay unit to receive the pulse signal V P0 And the input end of the level shifter is connected with one input end of the AND gate X1;
a level shifter for shifting the received pulse signal V P0 Is lowered, and the obtained programming pulse signal V is 1 Output to diffused memristor R M One end of (1), diffusion memristor R M Another terminal of (1) and a resistor R r And a comparator U 2 The inverting input terminals of the two-way switch are connected at the same time; resistance R r The other end of the first power supply is connected with a power ground;
comparator U 2 For receiving a reference voltage V ref Comparator U 2 Output terminal of (2)Is connected with the other input end of the AND gate X1;
the output end of the AND gate X1 is used as the output end of the random delay unit to output a pulse signal V P1 。
Preferably, the control logic unit comprises a nor gate, an and gate X2, an and gate X3, an xor gate, a preset number counter and two fixed time-delay units, wherein the delay time of the first fixed time-delay unit is τ 0 The delay time of the second fixed delayer is 2 tau 0 ；
One input end of the NOR gate is used as a control logic unit for receiving the pulse signal V P1 After the other input end of the NOR gate is simultaneously connected with the input ends of the two fixed time delayers, the NOR gate is used as a control logic unit to receive a voltage signal V Y An input terminal of (1);
the output end of the NOR gate is simultaneously connected with one input end of the AND gate X2 and one input end of the AND gate X3;
the output end of the first fixed time delay is connected with the other input end of the AND gate X2, and the output end of the second fixed time delay is connected with the other input end of the AND gate X3;
the output end of the AND gate X2 is connected with one input end of the exclusive-OR gate, and the output end of the AND gate X2 is used as a clock signal Clk output by the control logic unit L An output terminal of (a);
the output end of the AND gate X3 is connected with the other input end of the XOR gate, and the output end of the XOR gate is used as the output end of the control logic unit for outputting a reset signal Rst after being connected with the reset signal input end of the preset number counter;
the clock signal input end of the preset number counter is used for receiving an external clock signal Clk;
the output end of the preset number counter is used as a control logic unit to output a pulse signal V P0 To the output terminal of (a).
The constant-amplitude isosceles triangular wave with randomly changed frequency can be generated, firstly, a constant charging and discharging current is provided by using a current transmitter (CCII +), then, the random delay time of the diffusion memristor is coded by using a time interval measuring technology, and the obtained random thermometer code is used for controlling the size of a charging and discharging capacitor, so that the constant-amplitude triangular wave with the randomly changed period and frequency is obtained. Therefore, the amplitude of the generated random frequency triangular carrier signal is controlled by using the current transmitter and the diffusion memristor in combination with the peripheral circuit, the uniform-amplitude random frequency isosceles triangular wave signal is obtained, and the whole circuit structure and the design difficulty are greatly reduced.
The random frequency of the triangular wave is set by using the random delay time of the diffusion memristor, so that the scale and the power consumption of a circuit are reduced; on the other hand, in recent years, the integration research of the memristor and the traditional CMOS device is rapidly advanced, and commercial products are available, so that the technology provided by the invention provides a brand new idea for realizing the integration of the random PWM technology and low power consumption.
The constant-amplitude triangular wave signal generated by the invention can be used as a carrier signal to be applied to a random PWM technology.
Drawings
FIG. 1 is a schematic structural diagram of a random frequency triangular wave generator based on a diffusion memristor and a current conveyor according to the present invention; wherein, I Z Is the current flowing from the current conveyor to the capacitor array or the current flowing from the capacitor array to the current conveyor; i is X Is the current flowing through the X port of the current conveyor, V X Is the voltage at the X port of the current conveyor;
FIG. 2 is a schematic diagram of the internal structure of the delay chain unit, the first register unit and the second register unit;
FIG. 3 is a schematic diagram of a first delay module;
FIG. 4 is a schematic diagram of a random delay unit; wherein, V 1 Outputting a programming pulse voltage, V, for the level shifter 2 Is a resistance R r Voltage component of V 3 Is a comparator U 2 The output voltage signal;
FIG. 5 is a schematic diagram of a control logic unit;
FIG. 6 is a schematic diagram of waveforms of key signals in a triangular wave generation process;
FIG. 7 is a waveform diagram of a key signal in the random delay unit of FIG. 4;
FIG. 8 shows Ag: siO 2 A structural schematic of a diffused memristor;
FIG. 9 is a numerical distribution graph of a random delay time of a diffusion memristor.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict.
Referring to fig. 1, the random frequency triangle generator based on the diffusion memristor and the current conveyor according to the present embodiment includes a control logic unit, a random delay unit, a delay chain unit, a first register unit, a second register unit, a current conveyor, N NMOS transistors M 1 To M N Capacitor array and comparator U 1 Resistance R A And a resistor R B And a resistance R X (ii) a Wherein the capacitor array comprises a capacitor C 0 To C N ；
The control logic unit is used for generating a pulse signal V P0 And simultaneously sending the data to the random delay unit and the delay chain unit; the reset circuit is also used for generating a reset signal Rst to reset the delay chain unit; and also for generating clock signals Clk L Clock control is carried out on the second register unit; and is also used for receiving the pulse signal V output by the random delay unit P1 (ii) a And also for receiving the comparator U 1 Voltage signal V output from output terminal Y ；
The random delay unit is realized by adopting a diffusion memristor and is used for receiving a pulse signal V P0 Processing to obtain pulse signal V P1 And will pulse signal V P1 Simultaneously input to the control logic unit and the first register unit; wherein the pulse signal V P1 And pulse signal V P0 Are equal in period, and the pulse signal V P1 And pulse signal V P0 Are coincident in time, pulse signal V P0 High level duration t p Is a fixed value, pulse signal V P1 High level duration t d Is a random value, and t d ＜t p ；
The random delay time of the diffusion memristor is equal to t d ；
A delay chain unit for receiving the pulse signal V P0 Generating an N-bit thermometer code and sending the N-bit thermometer code to a first register unit;
the first register unit receives the pulse signal V P1 At its pulse signal V P1 The falling edge time of the first register unit latches the received N-bit thermometer code and sends the latched result to the second register unit;
the second register unit is based on the received clock signal Clk L At its clock signal Clk L The rising edge time of the first register unit latches the latch result output by the first register unit to obtain the N-bit thermometer code d 1 To d N And an N-bit thermometer code d 1 To d N Respectively sent to NMOS tubes M 1 To M N The grid of (3) controls the corresponding NMOS tube; wherein when d i When =1, represents d i Is at a high level; when d is i When =0, represents d i Low level, i =1, 2, 3 \8230, N;
NMOS tube M 1 To M N Source and capacitor C 0 One end of the power supply is connected with a power ground;
NMOS tube M 1 To M N Respectively with the capacitor C 1 To C N Is connected to a capacitor C 0 To C N And the other end of the current transmitter, a Z port of the current transmitter and a comparator U 1 Are connected simultaneously, and the voltage signal V of the connection point Cap As a random frequency triangular carrier signal generated by a triangular carrier generator, and a voltage signal V Cap Is a random frequency isosceles triangle wave signal with equal amplitude;
comparator U 1 Non-inverting input terminal and resistor R A And a resistor R B Are connected at the same time, resistor R B The other end of the resistor R is connected with a power ground A And the other end of the comparator U 1 Output terminal of current conveyor, Y port of current conveyor and voltage signal V of control logic unit Y The input ends are connected;
x port and resistor R of current transmitter X Is connected to a resistor R X The other end of the first power supply is connected with a power ground;
comparator U 1 The positive voltage input end is connected with a power supply V DD Comparator U 1 Negative voltage input end is connected with a power supply V SS And V is DD ＝-V SS 。
In this embodiment, the input of the delay chain unit is a pulse signal V P0 And a reset signal Rst, the states of N signals output by the delay chain unit, namely the N-bit thermometer code reflects the pulse signal V of the delay chain unit P0 Delay state of rising edge.
The input and output of the first and second register units are transmitted in the form of thermometer codes. Second register unit at Clk L The input is latched at the time of rising edge, and the first register unit is at V P1 Latching and inputting at the falling edge moment, wherein the input and output signals are logic level signals; counting the code d by temperature 1 ～d N For example, d i =1, means d i Is high level, d i =0, denotes d i Is low. d is a radical of 1 ～d N The logic state of (B) reflects V P1 Relative to V P0 Time delay of the rising edge instant of (i.e. t) d 。
N-bit thermometer code is characterized in that 1 and 0 are distributed in a centralized way, 1 is concentrated at the front section of the code group, 0 is concentrated at the rear section of the code group, for example, when N =8, the thermometer code d 1 ～d 8 Can take the value of [11100000 ]]. This encoding is very common in time interval measurement techniques. For the present invention at V P1 Is loweredAlong the time, the number of 1 in the thermometer code output by the delay chain unit latched by the first register unit is recorded as m, and then m tau represents V P1 Falling edge relative to V P0 The delay time of the rising edge is m tau = t d . Due to t d Is random, τ is deterministic, so m is a random number. τ denotes the fixed delay time of each delay module.
d 1 ～d N Respectively controlling NMOS tubes M of active switches 1 To M N On/off of (d) i =1 denotes M i On, d is turned on i =0, represents M i Cutoff, therefore, d i =1 also denotes capacitance C i And C 0 Parallel connection, otherwise, if d i =0 also representing the capacitance C i Is disconnected and does not participate in the charging and discharging process. So that the total capacitance of the capacitor array during a charge-discharge cycle is
Wherein, the capacitor C 0 To C N All the capacitance values of (A) are C, C T Has a charging and discharging current of I Z ，I Z Is provided by CCII + (i.e., current conveyor).
In a specific application, V exists according to the characteristics of the current transmitter X ＝V Y ，I X ＝I Z And then, the following steps are known: when the capacitor array is in the process of charging, I Z From the current conveyor to the capacitor array, in this case V Cap Is smaller than the comparator U 1 Positive phase input terminal voltage V TH ＝V DD R B /(R A +R B ) Comparator U 1 Has an output voltage of V Y ＝V DD Thus, there is I Z ＝I X ＝V DD /R X When the capacitor is charged to V Cap Greater than V TH ＝V DD R B /(R A +R B ) Time comparator U 1 Has an output voltage of V Y ＝V SS ＝-V DD Thus, there is I Z ＝I X ＝-V DD /R X ，I Z The capacitor array starts to discharge from the current transmitter, and the comparator starts to dischargeU 1 The positive phase input terminal voltage of TH ＝-V DD R B /(R A +R B ) (ii) a When the capacitor discharges to V Cap Less than-V DD R B /(R A +R B ) Time comparator U 1 Is changed back to V Y ＝V DD The capacitor starts to charge again; the process is repeated in cycles. The charging and discharging currents on the capacitor array are equal in magnitude and are due to C T Is relatively large and I Z Is relatively small, so that in the charging and discharging process, the voltage V on the capacitor Cap Approximately linearly varying.
To sum up, during charging, V Cap from-V DD R B /(R A +R B ) Increase linearly to V DD R B /(R A +R B ) At time of discharge, V Cap Then by V DD R B /(R A +R B ) Linear down to-V DD R B /(R A +R B ) The charging and discharging time is equal, therefore, V Cap Is a constant-amplitude isosceles triangular wave signal with a period of 4C T R B R X /(R A +R B )；d 1 ～d N The larger the number m of (1) s, the larger C T The larger the triangular wave period is, the longer the triangular wave period is, and the lower the frequency is; the smaller m is, C T The smaller, the shorter the period, the higher the frequency; due to t d Is random, d 1 ～d N The number m of 1 s is also random, and the period of the triangular wave is random.
The diffused memristor has two characteristics: 1. the device is switched from a high-resistance state to a low-resistance state under the action of certain voltage pulse, and a random delay time is required to be passed; 2. after the voltage pulse is removed, the device can be automatically restored to a high-resistance state from a low-resistance state, namely volatility.
The diffusion memristor is very suitable for being applied to a random pulse width modulation technology, the distribution range of random time delay can be adjusted to a required working frequency range, the distribution range is wider in a low-frequency range, the randomness is better, and the random pulse width modulation technology is mainly applied to the low-frequency range; due to volatility, the diffusion memristor does not need to erase a circuit, and the complexity of circuit design is reduced; on the other hand, the difficulty of integrating the diffusion memristor and the CMOS device is lower.
The triangular carrier generator according to the embodiment can generate a constant-amplitude isosceles triangular wave with randomly changing frequency, firstly, a current transmitter (CCII +) is used for providing constant charging and discharging current, then, a time interval measurement technology is used for coding random delay time of a diffusion memristor, and an obtained random thermometer code is used for controlling the size of a charging and discharging capacitor, so that the constant-amplitude triangular wave with randomly changing period and frequency is obtained. Therefore, the amplitude of the generated random frequency triangular carrier signal is controlled by using the current transmitter and the diffusion memristor in combination with the peripheral circuit, so that a random frequency isosceles triangular signal with equal amplitude is obtained, and the whole circuit structure and the design difficulty are greatly reduced.
The waveforms of the key signals in the triangular wave generation process are given in fig. 6, where V Cap Is a constant-amplitude isosceles triangular wave signal, and the period is changed. V P1 At low level, when V Cap Discharging to below-V TH ，V Y From V DD Becomes V SS This will result in Clk L A high level narrow pulse, clk, appears L Latches the thermometer code obtained by the first register unit in the previous triangular wave generation process into the second register unit, and uses the code to control the total capacitance value of the capacitor array in the first triangular wave generation process in fig. 6. Clk L After the high-level narrow pulse is ended, the Rst generates a high-level narrow pulse, the high level of the Rst resets the output state of the delay chain unit, after the reset is ended, the Rst is restored to be a low level, and then the control logic unit outputs a pulse signal V P0 ，V P0 High level duration t p Is fixed, and the random delay unit is receiving V P0 Then outputs a pulse signal V P1 ，V P1 Rising edge time V of P0 Synchronous, but high level duration t d Is random and satisfies t d ≤t p ；V P0 Input delay chain unit, pair of delay chain units V P0 Is delayed at V P1 The falling edge first register unit latches the thermometer code on the delay chain unit, which is used to set the total capacitance value of the capacitor array in the second triangular wave generation process in fig. 6. In summary, when the previous triangle wave ends, the second register unit obtains a random N-bit thermometer code d 1 ～d N And using it to determine the period of the triangular wave currently to be generated, d 1 ～d N For the last triangular wave duration V P1 The pulse width, namely: for t d Is quantized, and d 1 ～d N Is constant during the current charge-discharge cycle.
Further, referring specifically to fig. 2, the delay chain unit includes N delay modules, where the N delay modules are cascaded in series, and a signal input end of a first delay module is used as the delay chain unit to receive the pulse signal V P0 An input terminal of (1);
each delay module is used for delaying the rising edge of an input signal of the delay module, and delay signal values output by the first to Nth delay modules are respectively used as first to Nth thermometer codes output by the delay chain unit;
the reset signal input end of each delay module is used for receiving a reset signal Rst, and when the reset signal Rst is at a high level, the output states of the N delay modules are reset to be 0.
In specific application, the N cascaded delay modules are sequentially a first delay module to an Nth delay module from left to right, and the signal input end of the first delay module is used as a delay chain unit to receive a pulse signal V P0 An input terminal of (1); the signal output end of the first delay module is connected with the signal input end of the second delay module, the signal output end of the second delay module is connected with the signal input end of the third delay module, \8230, and so on, the signal output end of the (N-1) th delay module is connected with the signal input end of the Nth delay module.
In the preferred embodiment, the input of the delay chain unit is a pulse signal V P0 And a reset signal Rst, wherein the delay chain unit is formed by cascading N delay modules, each delay module generates a certain delay for the rising edge of the input signal and is all at the RstThe output state is reset to 0 at high level, since the input of the first delay module is V P0 Then pulse signal V P0 The rising edge of the delay chain is gradually conducted in the delay chain unit, if the output of one delay module is 1, V is shown P0 The rising edge of (c) passes through the delay module and passes through the time that τ is required; if the output of one delay module is 0, V is indicated P0 The rising edge has not yet come or is passing. For example, the output of the m-th delay cell is 1 (denoted by V) P0 The delay cell that is the input is the 1 st), and the output of the m +1 th delay cell is 0, then V is considered P0 Is conducted for m tau in the delay chain, and thus, V P1 At the falling edge time, the output state of the delay chain unit reflects V P1 Relative to V P0 Random delay time t of rising edge d 。
Further, with particular reference to FIG. 3, the delay module includes a NOT gate Y 1 NOT gate Y 2 NMOS tube M a And NMOS transistor M b ；
NOT gate Y 1 The input end of the delay module is used as the data signal input end of the delay module;
NOT gate Y 1 Of the output nand gate Y 2 Is connected with the input end of a NOT gate Y 2 Output end of the NMOS transistor M a Drain electrode of (1) and NMOS tube M b The grid of the delay module is connected with the grid of the first transistor and then used as a data signal output end of the delay module;
NMOS tube M a The grid of the delay module is used as a reset signal input end of the delay module;
NMOS tube M a Source electrode of (1) and NMOS tube M b Source electrode and NMOS transistor M b The drains are connected simultaneously and then connected to the power ground.
In the preferred embodiment, the first delay module is used for explanation, and the NMOS transistor M b The high level of Rst enables NMOS transistor M to be used as MOS capacitor a Conducting to connect the NMOS transistor M b The charge stored on the delay module quickly drains away so that the output state of the delay module is reset to 0.V P0 The rising edge of the NMOS transistor M b The parasitic capacitance of the gate is charged from the reset stateTherefore, the output of the delay module can not follow V P0 The high level is immediately changed to high level, and the output will reach the high level threshold value after a delay time τ, which is determined by the design parameters of the delay unit module and can be considered as a fixed value. At the beginning of each working cycle, rst resets the output state of the delay unit module, so that the delay unit module only has a pair V P0 Delay of the rising edge of (c). The rest N-1 delay modules in the delay chain unit have the same structure as the unit, the delay time of each delay module is tau, the reset operation is carried out by utilizing the high level of Rst, and the difference is only that the input signals of the cascade NOT gate are different.
Further, with particular reference to FIG. 2, the first register cell includes a NOT gate Y 3 And N D flip-flops;
NOT gate Y 3 As a first register unit receiving a pulse signal V P1 An input terminal of (1);
NOT gate Y 3 The output end of the D trigger is simultaneously connected with the clock signal input ends of the N D triggers;
d input ends of the first to Nth D triggers are respectively used as input ends of first to Nth thermometer codes of the first register unit;
q output ends of the first to Nth D flip-flops are respectively used as output ends of the first to Nth thermometer codes of the first register unit.
Furthermore, referring specifically to fig. 2, the second register unit includes N D flip-flops, and the clock signal input terminals of the N D flip-flops are connected at the same time and then used as the clock signal input terminal of the second register unit;
d input ends of first to Nth D triggers in the second register unit are respectively used as input ends of first to Nth thermometer codes of the second register unit;
q output ends of first to Nth D flip-flops in the second register unit are respectively used as output ends of first to Nth thermometer codes of the second register unit.
In the preferred embodiment of the invention, the first register unit and the second register unit are both realized by N D triggers, and the invention has simple structure and convenient realization.
Further, referring specifically to fig. 4, the random delay unit includes a level shifter, a diffusion memristor R M And a resistor R r Comparator U 2 And an AND gate X1;
the input end of the level shifter is used as the input end of the random time delay unit to receive the pulse signal V P0 And the input end of the level shifter is connected with one input end of the AND gate X1;
a level shifter for shifting the received pulse signal V P0 Is lowered and the obtained programming pulse signal V is applied 1 Output to diffused memristor R M One end of (1), diffusion memristor R M Another terminal of (1) and a resistor R r And a comparator U 2 The inverting input terminals of the two-way switch are connected simultaneously; resistance R r The other end of the first power supply is connected with a power ground;
comparator U 2 For receiving a reference voltage V ref Comparator U 2 Is connected with the other input end of the AND gate X1;
the output end of the AND gate X1 is used as the output end of the random delay unit to output a pulse signal V P1 。
In the preferred embodiment, a circuit structure of the random delay unit is provided, and referring to fig. 4 specifically, the circuit parameters may be selected as follows: pulse signal V P0 Has a frequency of 1kHz and a pulse width of 300 mus, and a programming pulse voltage V is obtained by reducing the amplitude of the high level through level shifting 1 ，V 1 Amplitude of 0.5V (0.5V for high level and 0V for low level), V ref ＝0.15V，R r =120k Ω, and a schematic diagram of the output waveform of the circuit obtained under the condition is shown in fig. 7.
The principle of operation of the random delay unit is analyzed in conjunction with FIG. 4 as follows, at pulse V 1 Under the action of high level, the memristor R is diffused for a certain time M From an initially high-resistance state to a low-resistance state, such that V 1 Through R M And R r Partial pressure value V of 2 Also increases to be higher than the comparator U at a certain time 2 Reference voltage V of ref At this moment, the comparator U 2 Output voltage V of 3 It is switched from high to low. Memristor R due to diffusion M Randomness of resistance change, voltage V 2 Increase to above V ref A certain random delay time t is needed to pass before d Therefore, the comparator U 2 Output voltage V of 3 Is of high level duration t d ；V P0 And V 3 Output V after AND operation P1 It is easy to know that the high level duration is t d See fig. 7.
In specific application, the diffusion memristor R M Optionally Ag or SiO 2 The diffusion memristor is realized by Ag: siO with specific reference to figure 8 2 The diffusion memristor is made of Pt/Ag/Ag SiO 2 The Pt/laminated structure consists of a 15nm thick Pt bottom electrode at the bottom, a 10nm Ag-SiO 2 covering layer and a 5nm Ag metal reservoir layer at the top, a 20nm Pt/30nm Au deposition layer at the top, a 30nm Au layer for improving the electric contact characteristic of the bonding pad, and a 5nm Ag reservoir layer for supplying enough Ag atoms. According to Ag to SiO 2 If a conductive channel formed by Ag nano particles exists in the layer, the memristor can be switched between a low resistance state and a high resistance state, so that Ag is SiO 2 The layer may be referred to as a resistive layer. In addition, the resistance state of the memristor is volatile, and under the action of a certain voltage pulse, after a random delay time, the device is switched from a high resistance state to a low resistance state, and automatically restores to the high resistance state after the applied voltage pulse is removed, which is different from the common nonvolatile memristor. The switching of the resistance state is due to the separation of Ag nanoparticles from the Ag reservoir and in the Ag: siO 2 A conductive channel is formed in the layer, and the diffusion process of the Ag nano particles is a random process, so that the resistance state switching of the diffusion memristor is random, and random delay time t can be used d This randomness is characterized quantitatively.
Random delay time t d Distribution of (2) and input programming pulse voltage (V) 1 Is related to the amplitude of (d), t can be adjusted accordingly d So that t is distributed d ≤t p Is satisfied. In FIG. 9 is given at V 1 T measured at different values of (0.4 to 0.9V) d It can be seen that the higher the programming pulse voltage amplitude, the shorter the average delay time, and the narrower the distribution range.
Further, referring specifically to fig. 5, the control logic unit includes a nor gate, an and gate X2, an and gate X3, an xor gate, a preset number counter and two fixed time-delay units, wherein the delay time of the first fixed time-delay unit is τ 0 The delay time of the second fixed delayer is 2 tau 0 ；
One input end of the NOR gate is used as a control logic unit for receiving the pulse signal V P1 After the other input end of the NOR gate is simultaneously connected with the input ends of the two fixed time delayers, the NOR gate is used as a control logic unit to receive a voltage signal V Y An input terminal of (a);
the output end of the NOR gate is simultaneously connected with one input end of the AND gate X2 and one input end of the AND gate X3;
the output end of the first fixed time delay is connected with the other input end of the AND gate X2, and the output end of the second fixed time delay is connected with the other input end of the AND gate X3;
the output end of the AND gate X2 is connected with one input end of the exclusive-OR gate, and the output end of the AND gate X2 is used as a clock signal Clk output by the control logic unit L An output terminal of (a);
the output end of the AND gate X3 is connected with the other input end of the XOR gate, and the output end of the XOR gate is used as the output end of the control logic unit for outputting a reset signal Rst after being connected with the reset signal input end of the preset number counter;
the clock signal input end of the preset number counter is used for receiving an external clock signal Clk;
the output end of the preset number counter is used as a control logic unit to output a pulse signal V P0 To the output terminal of (a).
In this embodiment, the input to the control logic is V Y 、V P1 The output is V P0 Rst and Clk L The function of the control logic is as shown in FIG. 5, when V P1 At low level, the input voltageV Y From V DD Variable V SS Meanwhile, the output of the NOR gate is changed from low to high, and the outputs of the NOR gate are respectively input into the AND gates X2 and X3. Voltage V Y Is delayed by a time delay tau 0 The obtained signal is input into an AND gate X2, and the output Clk of the AND gate X2 L Will be at a voltage V Y After the end of the falling edge, appears for a period of time tau 0 High-level narrow pulses of (2); similarly, the output of AND gate X3 will be at V Y After the end of the falling edge, the time is 2 tau 0 High-level narrow pulses of (2); the two high-level narrow pulses pass through an exclusive-or gate to obtain an output reset signal Rst, and the reset signal Rst appears for a period of time tau 0 And the high level narrow pulse is in the clock signal Clk L And the high level narrow pulse occurs after the end. The reset signal Rst is used as a reset signal of the preset number counter, and when the high level is reset, the high level of the reset signal Rst ends, namely, the reset completion time, the preset number counter starts counting the clock signal Clk, and the pulse signal V is enabled P0 From low to high, with a lag of V at this time Y Has a falling edge of 2 tau 0 The time of (d); when the preset number counter counts to a preset value D p Time, pulse signal V P0 From high to low, the high level lasts for t p ＝D p T, T is the period of the clock Clk, so T p Is stationary.
It is noted that the random delay unit enables the pulse signal V to be pulsed P1 Following pulse signal V P0 While changing from low to high, when the pulse signal V P1 When the output of the NOR gate of the control logic unit is in high level, the output of the NOR gate of the control logic unit is always in low level, so that narrow pulses do not appear at the outputs of X2 and X3, and the clock signal Clk L And the potential of the reset signal Rst remains unchanged; and because of the pulse signal V P1 Rising edge distance voltage signal V Y Has a falling edge of 2 tau 0 Time of (1), thus V P1 Does not affect the Clk L And Rst.
There is also a case, as shown in FIG. 6, when V Y Is a V SS When, V P1 The NOR gate outputs from high to low and then from low to high, but because of the random delayThe output of the cell remains low, so the outputs of X2 and X3 remain unchanged, clk L And Rst remains unaffected.
In general, the control logic unit is only at V P1 Is low level, and V Y When a falling edge occurs, V is enabled P0 Rst and Clk L Is changed to start a new duty cycle, V P0 The rising edge of the random delay unit enables the random delay unit to start working; clk L Causes the second register unit to obtain the random value d stored in the first register unit 1 ～d N And sending the triangular wave to a capacitor array for controlling the period of the triangular wave generated currently; the output states of all delay modules in the delay chain unit are reset and cleared by the high-level narrow pulse of Rst, and the delay chain unit is used for resetting V after the clearing is finished P0 Is delayed at V P1 The falling edge first register unit latches the random value of the delay chain unit, and the random value is used for controlling the period of the next triangular wave.
Although the invention herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present invention. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims. It should be understood that features described in different dependent claims and herein may be combined in ways different from those described in the original claims. It is also to be understood that features described in connection with individual embodiments may be used in other described embodiments.
Claims (7)
1. The random frequency triangular wave generator based on the diffusion memristor and the current transmitter is characterized by comprising a control logic unit, a random time delay unit, a time delay chain unit, a first register unit, a second register unit, the current transmitter and N NMOS tubes M 1 To M N Capacitor array and comparator U 1 Resistance R A Resistance R B And electricityResistance R X (ii) a Wherein the capacitor array comprises a capacitor C 0 To C N ；
The control logic unit is used for generating a pulse signal V P0 And simultaneously sending the data to the random delay unit and the delay chain unit; the reset circuit is also used for generating a reset signal Rst to reset the delay chain unit; and also for generating a clock signal Clk L Clock control is carried out on the second register unit; and is also used for receiving the pulse signal V output by the random delay unit P1 (ii) a And also for receiving the comparator U 1 Voltage signal V output from output terminal Y ；
The random delay unit is realized by adopting a diffusion memristor and is used for receiving a pulse signal V P0 Processing to obtain pulse signal V P1 And will pulse signal V P1 Simultaneously inputting the signals to the control logic unit and the first register unit; wherein the pulse signal V P1 And pulse signal V P0 Are equal in period, and the pulse signal V P1 And pulse signal V P0 Are coincident in time, pulse signal V P0 High level duration t p Is a fixed value, a pulse signal V P1 High level duration t d Is a random value, and t d ＜t p ；
The random delay time of the diffusion memristor is equal to t d ；
A delay chain unit for receiving the pulse signal V P0 Generating an N-bit thermometer code and sending the N-bit thermometer code to a first register unit;
the first register unit receives the pulse signal V P1 At its pulse signal V P1 The falling edge time of the first register unit latches the received N-bit thermometer code and sends the latched result to the second register unit;
the second register unit is based on the received clock signal Clk L At its clock signal Clk L Latches the latch result output from the first register unit at the rising edge time to obtain an N-bit thermometer code d 1 To d N And coding the N-bit thermometer by d 1 To d N Respectively sent to NMOS tubes M 1 To M N Of a grid electrodeControlling the corresponding NMOS tube; wherein when d i When =1, represents d i Is high level; when d is i When =0, represents d i Low level, i =1, 2, 3 \8230, N;
NMOS tube M 1 To M N Source and capacitor C 0 One end of each of the two ends is connected with a power ground;
NMOS tube M 1 To M N Respectively with the capacitor C 1 To C N Is connected to a capacitor C 0 To C N And the other end of the comparator U is connected with the Z port of the current transmitter and the comparator U 1 Are connected simultaneously, and the voltage signal V of the connection point Cap As a random frequency triangular carrier signal generated by a triangular carrier generator, and a voltage signal V Cap Is a random frequency isosceles triangle wave signal with equal amplitude;
comparator U 1 Non-inverting input terminal and resistor R A And a resistor R B Are connected at the same time, resistor R B The other end of the resistor R is connected with a power ground A And the other end of the comparator U 1 Output terminal of current conveyor, Y port of current conveyor and voltage signal V of control logic unit Y The input ends are connected;
x port and resistor R of current transmitter X Is connected to a resistor R X The other end of the first power supply is connected with a power ground;
comparator U 1 The positive voltage input end is connected with a power supply V DD Comparator U 1 Negative voltage input end is connected with a power supply V SS And V is DD ＝-V SS 。
2. The random frequency triangular wave generator based on the diffusion memristor and the current conveyor as claimed in claim 1, wherein the delay chain unit comprises N delay modules, and the N delay modules are cascaded in series, wherein the signal input end of the first delay module is used as the delay chain unit to receive the pulse signal V P0 An input terminal of (1);
each delay module is used for delaying the rising edge of an input signal of the delay module, and delay signal values output by the first to Nth delay modules are respectively used as first to Nth thermometer codes output by the delay chain unit;
the reset signal input end of each delay module is used for receiving a reset signal Rst, and when the reset signal Rst is at a high level, the output states of the N delay modules are reset to be 0.
3. The diffused memristor and current conveyor based random frequency triangle wave generator of claim 2, wherein the delay block comprises a not gate Y 1 NOT gate Y 2 NMOS tube M a And NMOS transistor M b ；
NOT gate Y 1 The input end of the delay module is used as the data signal input end of the delay module;
NOT gate Y 1 Of the output nand gate Y 2 Is connected to the input terminal of a NOT gate Y 2 Output end of the NMOS transistor M a Drain electrode of (1) and NMOS tube M b The grid of the delay module is connected with the grid of the first transistor and then used as a data signal output end of the delay module;
NMOS tube M a The grid of the delay module is used as a reset signal input end of the delay module;
NMOS tube M a Source electrode of and NMOS tube M b Source electrode and NMOS transistor M b The drain electrodes of the two transistors are connected to a power ground.
4. The diffused memristor-and-current-conveyor-based random frequency triangle wave generator of claim 1, wherein the first register cell comprises a not gate Y 3 And N D flip-flops;
NOT gate Y 3 As a first register unit receiving a pulse signal V P1 An input terminal of (1);
NOT gate Y 3 The output end of the D flip-flop is simultaneously connected with the clock signal input ends of the N D flip-flops;
d input ends of the first to Nth D flip-flops are respectively used as input ends of first to Nth thermometer codes of the first register unit;
q output ends of the first to Nth D flip-flops are respectively used as output ends of the first to Nth thermometer codes of the first register unit.
5. The random frequency triangular wave generator based on the diffusion memristor and the current conveyor as claimed in claim 1, wherein the second register unit comprises N D flip-flops, and the clock signal input ends of the N D flip-flops are connected at the same time to be used as the clock signal input end of the second register unit;
d input ends of first to Nth D triggers in the second register unit are respectively used as input ends of first to Nth thermometer codes of the second register unit;
q output ends of first to Nth D flip-flops in the second register unit are respectively used as output ends of first to Nth thermometer codes of the second register unit.
6. The random frequency triangle wave generator based on diffused memristor and current conveyor of claim 1, wherein the random delay unit comprises a level shifter, a diffused memristor R M Resistance R r Comparator U 2 And an AND gate X1;
the input end of the level shifter is used as the input end of the random time delay unit to receive the pulse signal V P0 And the input end of the level shifter is connected with one input end of the AND gate X1;
level shifter for receiving pulse signal V P0 Is lowered and the obtained programming pulse signal V is applied 1 Output to diffused memristor R M One end of (1), diffusion memristor R M The other end of (2) and a resistor R r And a comparator U 2 The inverting input terminals of the two-way switch are connected simultaneously; resistance R r The other end of the first power supply is connected with a power ground;
comparator U 2 For receiving a reference voltage V ref Comparator U 2 The output end of the AND gate is connected with the other input end of the AND gate X1;
the output end of the AND gate X1 is used as the output end of the random time delay unit to output a pulse signal V P1 。
7. The random frequency triangular wave generator based on the diffusion memristor and the current conveyor as claimed in claim 1, wherein the control logic unit comprises a nor gate, an and gate X2, an and gate X3, an xor gate, a preset number counter and two fixed delayers, wherein the delay time of the first fixed delayer is τ 0 The delay time of the second fixed delayer is 2 tau 0 ；
One input end of the NOR gate is used as a control logic unit for receiving the pulse signal V P1 After the other input end of the NOR gate is simultaneously connected with the input ends of the two fixed time delayers, the NOR gate is used as a control logic unit to receive a voltage signal V Y An input terminal of (1);
the output end of the NOR gate is simultaneously connected with one input end of the AND gate X2 and one input end of the AND gate X3;
the output end of the first fixed delayer is connected with the other input end of the AND gate X2, and the output end of the second fixed delayer is connected with the other input end of the AND gate X3;
the output end of the AND gate X2 is connected with one input end of the exclusive-OR gate, and the output end of the AND gate X2 is used as a clock signal Clk output by the control logic unit L An output terminal of (a);
the output end of the AND gate X3 is connected with the other input end of the XOR gate, and the output end of the XOR gate is used as the output end of the control logic unit for outputting a reset signal Rst after being connected with the reset signal input end of the preset number counter;
the clock signal input end of the preset number counter is used for receiving an external clock signal Clk;
the output end of the preset number counter is used as a control logic unit to output a pulse signal V P0 To the output terminal of (a).
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| CN112734022B (en) * | 2021-02-02 | 2023-12-19 | 郑州轻工业大学 | Four-character memristor neural network circuit with recognition and sequencing functions |
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| JP2004266780A (en) * | 2003-03-04 | 2004-09-24 | Fuji Electric Device Technology Co Ltd | Pulse width modulation circuit |
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