CN111599864B - P-type MOSFET and manufacturing method thereof - Google Patents

P-type MOSFET and manufacturing method thereof Download PDF

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CN111599864B
CN111599864B CN202010466627.1A CN202010466627A CN111599864B CN 111599864 B CN111599864 B CN 111599864B CN 202010466627 A CN202010466627 A CN 202010466627A CN 111599864 B CN111599864 B CN 111599864B
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CN111599864A (en
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李中华
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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Abstract

The invention discloses a P-type MOSFET, wherein a channel region consists of an N well covered by a grid structure, the N well comprises a superposition region consisting of first to third injection regions, and the superposition region is annealed; the implantation impurities of the first to third implantation regions are phosphorus, xenon and arsenic respectively; the doping concentration of the third implantation region is used for adjusting the threshold voltage, the ion implantation process of the third implantation region is performed after the ion implantation process of the second implantation region is completed, and the second implantation region forms an amorphized layer in the semiconductor substrate so as to make arsenic implantation of the third implantation region uniform. The invention also discloses a manufacturing method of the P-type MOSFET. The invention can reduce the local fluctuation of the threshold voltage and improve the device performance and the product yield.

Description

P-type MOSFET and manufacturing method thereof
Technical Field
The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a P-type MOSFET. The invention also relates to a manufacturing method of the P-type MOSFET.
Background
P-type MOSFETs, i.e., PMOS, are typically formed in Deep Nwelllayer (DNW), with the channel region formed using an N-well. The ion implantation process of the N-type deep well is typically preceded by the ion implantation process of the N-well. The ion implantation process of the N-type deep well has large implantation energy and deep implantation depth. A blanket oxide layer is typically formed on the surface of a semiconductor substrate, such as a silicon substrate, prior to ion implantation of an N-type deep well through which the ion implantation of the N-type deep well may pass.
But after the ion implantation process of the N-type deep well, the compactness of the cushion oxide layer can be damaged. This can adversely affect the subsequent ion implantation process of the N-well.
As the technology node of semiconductor devices continues to shrink, the junction depth of each doped region becomes shallower, which places increasing demands on the process of forming the N-well of the channel region. In the prior art, the N well is usually realized by adopting a layer of phosphorus ion implantation, the depth fluctuation of the phosphorus ion implantation is large, and the influence on the threshold voltage of the device is large.
Disclosure of Invention
The invention aims to solve the technical problem of providing a P-type MOSFET which can reduce the local fluctuation of threshold voltage and improve the device performance and the product yield. Therefore, the invention also provides a manufacturing method of the P-type MOSFET.
In order to solve the technical problem, the channel region of the P-type MOSFET provided by the invention is composed of an N well covered by a gate structure, the N well comprises a superposition region composed of a first injection region, a second injection region and a third injection region which are formed in a semiconductor substrate, and the superposition region is subjected to annealing treatment.
The implant impurity of the first implant region is phosphorus.
The implantation impurity of the second implantation region is xenon.
The implantation impurity of the third implantation region is arsenic.
The junction depth of the first injection region is larger than that of the second injection region, and the junction depth of the first injection region is larger than that of the third injection region.
The doping concentration of the third implantation region is used for adjusting the threshold voltage, the ion implantation process of the third implantation region is performed after the ion implantation process of the second implantation region is completed, and before the ion implantation of the third implantation region, an amorphization layer is formed in the semiconductor substrate by the second implantation region, and the amorphization layer enables the third implantation region to form uniform arsenic implantation so as to reduce fluctuation of the threshold voltage.
A further improvement is that the semiconductor substrate comprises a silicon substrate.
In a further improvement, a field oxide layer is formed on the semiconductor substrate, an active region is isolated by the field oxide layer, and a P-type MOSFET is formed in the active region.
A further improvement is that an N-type deep well is formed on the semiconductor substrate, the N-type deep well being formed therein.
A further improvement is that a drain region and a source region are formed in the semiconductor substrate on both sides of the gate structure.
The grid structure comprises a grid dielectric layer and a grid conductive material layer which are overlapped.
Further improvements include materials for the gate dielectric layer including silicon oxide, silicon oxynitride or high dielectric constant materials.
The gate conductive material layer is a polysilicon gate or a metal gate.
A further improvement is that the high dielectric constant material comprises hafnium oxide.
The ion implantation of the first implantation region has an implantation energy of 100 KeV-300 KeV and an implantation dosage of 1×10 13 cm -2 ～1×10 14 cm -2 ；
The ion implantation of the second implantation region has an implantation energy of 1 KeV-100 KeV and an implantation dose of 1×10 14 cm -2 ～1×10 16 cm -2 ；
The ion implantation of the third implantation region has an implantation energy of 1KeV to 80KeV and an implantation dose of 1×10 12 cm -2 ～1*10 14 cm -2 。
The further improvement is that the temperature of the overlapped area after annealing treatment is 1000-1300 ℃.
In order to solve the technical problems, the manufacturing method of the P-type MOSFET provided by the invention comprises the following steps:
step one, providing a semiconductor substrate, defining an active region on the semiconductor substrate, and forming an N-type deep well, wherein the N-type deep well is formed through an ion implantation and annealing process, and the ion implantation of the N-type deep well passes through a cushion oxide layer.
And step two, removing the cushion oxide layer and forming a sacrificial oxide layer before ion implantation of the N well.
Step three, ion implantation of the N trap is carried out, and the method comprises the following sub-steps:
a first phosphorus ion implantation is performed to form a first implantation region.
A second xenon ion implantation is performed to form a second implantation region.
A third arsenic ion implantation is performed to form a third implantation region.
And the superposition area is formed by the first injection area, the second injection area and the third injection area and is positioned in the N-type deep well.
The junction depth of the first injection region is larger than that of the second injection region, and the junction depth of the first injection region is larger than that of the third injection region.
The doping concentration of the third implantation region is used for adjusting the threshold voltage, and before the third arsenic ion implantation, the second xenon ion implantation forms an amorphized layer in the semiconductor substrate, and the amorphized layer makes the third arsenic ion implantation uniform so as to reduce fluctuation of the threshold voltage.
And fourthly, annealing the overlapped region to form the N well.
And fifthly, removing the sacrificial oxide layer.
And step six, forming a grid structure on the semiconductor substrate.
Step seven, performing source-drain injection in the N well at two sides of the grid structure to form a source region and a drain region; a channel region is comprised of the N-well covered by the gate structure, the channel region being located between the source region and the drain region.
A further improvement is that the semiconductor substrate comprises a silicon substrate.
A further improvement is that the step of defining the active region comprises:
and forming a field oxide layer on the semiconductor substrate, isolating an active region from the field oxide layer, and forming a P-type MOSFET in the active region.
In the second step, the wet etching or plasma etching process is adopted to remove the pad oxide layer;
and fifthly, removing the sacrificial oxide layer by adopting a wet etching or plasma etching process.
In the second step, a wet oxygen oxidation process is adopted to grow the sacrificial oxide layer, and the temperature of the wet oxygen oxidation process of the sacrificial oxide layer is 1000-1300 ℃; the thickness of the sacrificial oxide layer is
The grid structure comprises a grid dielectric layer and a grid conductive material layer which are overlapped.
The further improvement is that the material of the gate dielectric layer comprises silicon oxide, silicon oxynitride or a high dielectric constant material; the high dielectric constant material includes hafnium oxide.
The gate conductive material layer is a polysilicon gate or a metal gate.
Further improvement is that the method further comprises:
and eighth, forming metal silicide, an interlayer film, a contact hole, a through hole and a front metal layer.
Further improvement is that the implantation energy of the first phosphorus ion implantation is 100 KeV-300 KeV, and the implantation dosage is 1 multiplied by 10 13 cm -2 ～1×10 14 cm -2 ；
The implantation energy of the second xenon ion implantation is 1 KeV-100 KeV, and the implantation dosage is 1 multiplied by 10 14 cm -2 ～1×10 16 cm -2 ；
The implantation energy of the third arsenic ion implantation is 1 KeV-80 KeV, and the implantation dosage is 1×10 12 cm -2 ～1*10 14 cm -2 。
The further improvement is that the annealing treatment temperature of the superposition area in the fourth step is 1000-1300 ℃.
The invention sets up the structure of N well used for forming the channel region specially, N well no longer is made up of single doped structure, but divide into the stack area formed by first to three injection regions, after annealing, the invention sets up the doped structure of the first to three injection regions specially and has realized different functional structures separately, wherein:
the first injection region is doped with phosphorus, and the injection depth of the first injection region is deeper, so that isolation between the source and the drain can be well realized.
The second injection region adopts xenon doping, the ion injection process of xenon doping can enable the surface of the semiconductor substrate to be amorphized, compared with the non-purification achieved by silicon injection in the prior art, the amorphization effect achieved by xenon injection is better, and finally arsenic uniform doping of the third injection region can be improved.
The third implantation region adopts arsenic doping, the arsenic doping is positioned on the outermost surface of the channel region, the threshold voltage of the device can be well adjusted, and an amorphized layer is formed before the arsenic doping ion implantation, so that the uniformity of the arsenic doping is easily improved, the local fluctuation of the threshold voltage can be reduced, and the product yield can be improved.
Therefore, the invention can reduce the local fluctuation of the threshold voltage and improve the device performance and the product yield after specially setting the doping structure of the N well.
Drawings
The invention is described in further detail below with reference to the attached drawings and detailed description:
FIGS. 1A-1L are schematic views of a device structure at various steps in a method for fabricating a P-type MOSFET according to an embodiment of the present invention;
FIG. 2A is a photograph of an interface between amorphous silicon and crystalline silicon formed by amorphization using Si implantation in a prior art method;
FIG. 2B is a photograph of a second interface between amorphous silicon and crystalline silicon formed by amorphization using Xe implantation in a method according to an embodiment of the present invention;
FIG. 2C is a photograph of an interface between amorphous silicon and crystalline silicon formed by amorphization using Si implantation in a prior art method;
fig. 2D is a photograph of an interface between amorphous silicon and crystalline silicon formed by amorphization using Xe implantation in a method according to an embodiment of the present invention.
Detailed Description
Referring to fig. 1K and 1L, the structure of the channel region of the P-type MOSFET according to the embodiment of the present invention is shown, where the channel region is formed by an N-well 8 covered by a gate structure, the N-well 8 includes a stack region 7 formed by a first injection region 4, a second injection region 5, and a third injection region 6 formed in a semiconductor substrate 101, and the stack region 7 is subjected to an annealing process, that is, the stack region 7 is subjected to an annealing process to form the N-well 8. Referring to fig. 1A, fig. 1K illustrates only the structure of an N-type deep well 2 formed in the semiconductor substrate 101.
In an embodiment of the present invention, the semiconductor substrate 101 includes a silicon substrate.
Preferably, a field oxide layer 1 is formed on the semiconductor substrate 101, and an active region is isolated by the field oxide layer 1, that is, the semiconductor substrate 101 in a region surrounded by the field oxide layer 1 serves as the active region. A P-type MOSFET is formed in the active region.
An N-type deep well 2 is formed on the semiconductor substrate 101, and the N-well 8 is formed in the N-type deep well 2. In fig. 1J, the semiconductor substrate 101 at the bottom of the N-type deep well 2 is not shown.
The implanted impurity of the first implanted region 4 is phosphorus.
Preferably, the ion implantation of the first implantation region 4 has an implantation energy of 100KeV to 300KeV and an implantation dose of 1×10 13 cm -2 ～1×10 14 cm -2 ；
The implanted impurity of the second implanted region 5 is xenon.
Preferably, the ion implantation of the second implantation region 5 has an implantation energy of 1KeV to 100KeV and an implantation dose of 1×10 14 cm -2 ～1×10 16 cm -2 ；
The implanted impurity of the third implanted region 6 is arsenic.
Preferably, the ion implantation of the third implantation region 6 has an implantation energy of 1KeV to 80KeV and an implantation dose of 1×10 12 cm -2 ～1*10 14 cm -2 。
The temperature of the overlapped area 7 after annealing treatment is 1000-1300 ℃.
As can be seen from fig. 1J, the ion implantation processes of the first implantation region 4, the second implantation region 5 and the third implantation region 6 corresponding to the N-well 8 in the embodiment of the present invention all penetrate through the sacrificial oxide layer 3; the sacrificial oxide layer 3 is removed after the annealing of the overlap region 7 is completed, as shown in fig. 1L. In the embodiment of the present invention, the ion implantation of the first implantation region 4 is performed first, and the sacrificial oxide layer 3 is required to be grown before the ion implantation of the first implantation region 4 is performed, so as to ensure the compactness of the sacrificial oxide layer 3, thereby ensuring the uniformity of each ion implantation of the N-well 8, and thus improving the quality of the N-well 8.
The junction depth of the first injection region 4 is greater than the junction depth of the second injection region 5, and the junction depth of the first injection region 4 is also greater than the junction depth of the third injection region 6.
The doping concentration of the third implantation region 6 is used to adjust the threshold voltage, the ion implantation process of the third implantation region 6 is performed after the ion implantation process of the second implantation region 5 is completed, and before the ion implantation of the third implantation region 6, the second implantation region 5 forms an amorphized layer in the semiconductor substrate 101, which causes the third implantation region 6 to form a uniform arsenic implantation to reduce the fluctuation of the threshold voltage.
The junction depth of the first injection region 4 is deeper, so that good isolation can be formed between the source region and the drain region, and the situation of electric leakage such as punching through of the source region and the drain region can be prevented.
When the device is conducted, a gate voltage larger than or equal to a threshold voltage is added to the gate structure, so that an inversion layer is formed on the surface of the channel region, and the inversion layer is used as a conducting channel for conducting source drain; an inversion layer is formed only on the surface of the channel region and is mainly located in the third implantation region 6, so that the third implantation region 6 in the embodiment of the present invention is mainly used for adjusting the threshold voltage. Experimental structure shows that the xenon doping corresponding to the second injection region 5 does not affect the threshold voltage of the device.
Drain and source regions are formed in the semiconductor substrate 101 on both sides of the gate structure.
The grid structure comprises a layer of overlapped grid dielectric layer and a layer of grid conductive material.
The gate dielectric layer is made of silicon oxide, silicon oxynitride or high dielectric constant material; the high dielectric constant material includes hafnium oxide. The gate conductive material layer is a polysilicon gate or a metal gate.
In the embodiment of the present invention, the function of the xenon doping introduced in the second implantation region 5 is to achieve amorphization of the semiconductor substrate 101, so that the subsequent arsenic implantation in the third implantation region 6 can be more uniform, and the threshold voltage adjustment of the device can be more stable and precise.
Compared with the prior art that the amorphization is carried out by adopting silicon injection, the amorphization of xenon injection can obtain better effect:
as shown in fig. 2A, a photograph of an interface between amorphous silicon and crystalline silicon formed by amorphization using Si implantation in the conventional method is shown; amorphous silicon is denoted by α -Si, crystalline silicon is denoted by c-Si, and the interface between amorphous silicon and crystalline silicon is denoted by reference numeral 401.
FIG. 2B is a photograph showing an interface between amorphous silicon and crystalline silicon formed by amorphization using Xe implantation in accordance with the present invention; the interface of amorphous silicon and crystalline silicon is shown as 402. The magnification of fig. 2B and 2A is the same, and it can be seen that interface 402 will be flatter than interface 401.
As shown in fig. 2C, a third photo of an interface between amorphous silicon and crystalline silicon formed by amorphization using Si implantation in the conventional method; in FIG. 2C, the thickness d1 of the damaged layer corresponding to the interface 401 was measured asA in FIG. 2C represents +.>The thickness d2 of the amorphous silicon is +.>
As shown in fig. 2D, a photograph of an interface between amorphous silicon and crystalline silicon formed by amorphization using Xe implantation in the method according to the embodiment of the present invention is four. Fig. 2D and 2C have the same magnification, and in fig. 2C, the thickness D3 of the damaged layer corresponding to the interface 402 is measured to beA in FIG. 2D represents +.>The thickness d4 of the amorphous silicon is +.>Therefore, the thickness d3 of the damaged layer corresponding to the interface 402 in the embodiment of the present invention is smaller than the thickness d1 of the damaged layer corresponding to the interface 401 in the prior art. The amorphization effect of the embodiments of the present invention is better.
The structure of the N-well 8 for forming the channel region is specially set in the embodiment of the present invention, the N-well 8 is not composed of a single doped structure, but is formed by dividing the N-well into overlapped regions composed of the first to third implanted regions after annealing, the doped structures of the first to third implanted regions are specially set in the embodiment of the present invention, and different functional structures are respectively realized, wherein:
the first injection region 4 is doped with phosphorus, and the injection depth of the first injection region 4 is deeper, so that isolation between source and drain can be well realized.
The second implantation region 5 adopts xenon doping, the ion implantation process of xenon doping can enable the surface of the semiconductor substrate to be amorphized, compared with the non-purification realized by silicon implantation in the prior art, the amorphization effect realized by xenon implantation is better, and finally the arsenic uniform doping of the third implantation region 6 can be improved.
The third implantation region 6 is doped with arsenic, the arsenic doping is located on the outermost surface of the channel region, the threshold voltage of the device can be well adjusted, and an amorphous layer is formed before the ion implantation of the arsenic doping, so that the uniformity of the arsenic doping is easily improved, the local fluctuation of the threshold voltage can be reduced, and the product yield can be improved.
Therefore, the embodiment of the invention can reduce the local fluctuation of the threshold voltage and improve the device performance and the product yield by specially setting the doping structure of the N well 8.
As shown in fig. 1A to 1L, a schematic device structure of the P-type MOSFET in the steps of the method for manufacturing a P-type MOSFET according to an embodiment of the present invention is shown; the manufacturing method of the P-type MOSFET comprises the following steps:
step one, as shown in fig. 1A, a semiconductor substrate 101 is provided, the semiconductor substrate 101 including a silicon substrate.
An active region is defined on the semiconductor substrate 101, and the step of defining the active region includes:
a field oxide layer 1 is formed on the semiconductor substrate 101, an active region is isolated by the field oxide layer 1, and a P-type MOSFET is formed in the active region.
Forming an N-type deep well 2, comprising the steps of:
forming a pad oxide layer 102;
as shown in fig. 1B, ion implantation of the N-type deep well 2 shown by reference numeral 103 is performed.
As shown in fig. 1C, an annealing process is performed to form the N-type deep well 2. In fig. 1C, the semiconductor substrate 101 at the bottom of the N-type deep well 2 is not shown.
Since the implantation energy of the ion implantation 103 of the N-type deep well 2 is relatively high, a certain damage effect may be generated on the pad oxide layer 102, and in fig. 1C, the pad oxide layer after the ion implantation 103 is completed is denoted by a reference numeral 102a alone.
Step two, as shown in fig. 1D, the pad oxide layer 102 is removed before the ion implantation of the N-well 8.
In the method of the embodiment of the invention, the pad oxide layer 102 is removed by adopting a wet etching or plasma etching process;
as shown in fig. 1E, a sacrificial oxide layer 3 is formed.
In the method of the embodiment of the invention, the sacrificial oxide layer 3 is grown by adopting a wet oxygen oxidation process, and the temperature of the wet oxygen oxidation process of the sacrificial oxide layer 3 is 1000-1300 ℃; the thickness of the sacrificial oxide layer 3 is
Step three, ion implantation of the N-well 8 is performed, including the following sub-steps:
as shown in fig. 1F, a first phosphorus ion implantation 104 is performed; as shown in fig. 1G, the first implant region 4 is formed after the first phosphorus ion implantation 104 is completed. PreferablyThe implantation energy of the first phosphorus ion implantation 104 is 100KeV to 300KeV, and the implantation dose is 1×10 13 cm -2 ～1×10 14 cm -2 。
As shown in fig. 1H, a second xenon ion implantation 105 is performed; as shown in fig. 1I, the second implantation region 5 is formed after the second xenon ion implantation 105 is completed. The second xenon ion implantation 105 has an implantation energy of 1KeV to 100KeV and an implantation dose of 1×10 14 cm -2 ～1×10 16 cm -2 。
As shown in fig. 1J, a third arsenic ion implantation 106 is performed; as shown in fig. 1K, the third implant region 6 is formed after the third arsenic ion implantation 106 is completed. The implantation energy of the third arsenic ion implantation 106 is 1KeV to 80KeV, and the implantation dose is 1×10 12 cm -2 ～1*10 14 cm -2 。
As shown in fig. 1K, a stack region 7 is formed by the first implantation region 4, the second implantation region 5 and the third implantation region 6, and the stack region 7 is located in the N-type deep well 2.
The junction depth of the first injection region 4 is greater than the junction depth of the second injection region 5, and the junction depth of the first injection region 4 is also greater than the junction depth of the third injection region 6.
The doping concentration of the third implantation region 6 is used to adjust the threshold voltage, and the second xenon ion implantation 105 forms an amorphized layer in the semiconductor substrate 101 before the third arsenic ion implantation 106, which makes the third arsenic ion implantation 106 uniform to reduce fluctuation of the threshold voltage.
And step four, as shown in fig. 1L, annealing the overlapped region 7 to form the N well 8.
In the method of the embodiment of the invention, the annealing treatment temperature of the superposition area 7 is 1000-1300 ℃.
And fifthly, removing the sacrificial oxide layer 3 as shown in fig. 1L.
In the method of the embodiment of the invention, the sacrificial oxide layer 3 is removed by adopting a wet etching or plasma etching process.
And step six, forming a gate structure on the semiconductor substrate 101.
The grid structure comprises a layer of overlapped grid dielectric layer and a layer of grid conductive material.
The gate dielectric layer is made of silicon oxide, silicon oxynitride or high dielectric constant material; the high dielectric constant material includes hafnium oxide.
The gate conductive material layer is a polysilicon gate or a metal gate.
Step seven, performing source-drain injection in the N well 8 at two sides of the grid structure to form a source region and a drain region; a channel region is comprised of the N-well 8 covered by the gate structure, the channel region being located between the source region and the drain region.
Further comprises:
and eighth, forming metal silicide, an interlayer film, a contact hole, a through hole and a front metal layer.
Preferably, the metal silicide is nickel silicide, the contact hole is a contact hole filled with tungsten, the through hole is a tungsten through hole, and the front metal layer is a copper interconnection structure.
The present invention has been described in detail by way of specific examples, but these should not be construed as limiting the invention. Many variations and modifications may be made by one skilled in the art without departing from the principles of the invention, which is also considered to be within the scope of the invention.

Claims (20)

1. A P-type MOSFET, characterized by: the channel region is composed of an N well covered by a gate structure, the N well comprises a superposition region composed of a first injection region, a second injection region and a third injection region which are formed in the semiconductor substrate, and the superposition region is subjected to annealing treatment;
the implantation impurity of the first implantation region is phosphorus;
the implantation impurity of the second implantation region is xenon;
the implantation impurity of the third implantation region is arsenic;
the junction depth of the first injection region is larger than that of the second injection region, and the junction depth of the first injection region is larger than that of the third injection region;
the doping concentration of the third implantation region is used for adjusting the threshold voltage, the ion implantation process of the third implantation region is performed after the ion implantation process of the second implantation region is completed, and before the ion implantation of the third implantation region, an amorphization layer is formed in the semiconductor substrate by the second implantation region, and the amorphization layer enables the third implantation region to form uniform arsenic implantation so as to reduce fluctuation of the threshold voltage.
2. The P-type MOSFET of claim 1 wherein: the semiconductor substrate includes a silicon substrate.
3. The P-type MOSFET of claim 1 wherein: and forming a field oxide layer on the semiconductor substrate, isolating an active region from the field oxide layer, and forming a P-type MOSFET in the active region.
4. The P-type MOSFET of claim 1 wherein: an N-type deep well is formed on the semiconductor substrate, and the N-type deep well is formed therein.
5. The P-type MOSFET of claim 2 wherein: and forming a drain region and a source region in the semiconductor substrate at two sides of the gate structure.
6. The P-type MOSFET of claim 2 wherein: the grid structure comprises a layer of overlapped grid dielectric layer and a layer of grid conductive material.
7. The P-type MOSFET of claim 6 wherein: the gate dielectric layer is made of silicon oxide, silicon oxynitride or high dielectric constant material;
the gate conductive material layer is a polysilicon gate or a metal gate.
8. The P-type MOSFET of claim 7 wherein: the high dielectric constant material includes hafnium oxide.
9. The P-type MOSFET of claim 1 wherein:
the ion implantation of the first implantation region has an implantation energy of 100 KeV-300 KeV and an implantation dose of 1×10 13 cm -2 ～1×10 14 cm -2 ；
The ion implantation of the second implantation region has an implantation energy of 1 KeV-100 KeV and an implantation dose of 1×10 14 cm -2 ～1×10 16 cm -2 ；
The ion implantation of the third implantation region has an implantation energy of 1KeV to 80KeV and an implantation dose of 1×10 12 cm -2 ～1*10 14 cm -2 。
10. The P-type MOSFET of claim 9 wherein: the temperature of the overlapped area after annealing treatment is 1000-1300 ℃.
11. A method of fabricating a P-type MOSFET, comprising the steps of:
step one, providing a semiconductor substrate, defining an active region on the semiconductor substrate, and forming an N-type deep well, wherein the N-type deep well is formed by an ion implantation and annealing process, and the ion implantation of the N-type deep well passes through a cushion oxide layer;
step two, removing the cushion oxide layer and forming a sacrificial oxide layer before ion implantation of the N well;
step three, ion implantation of the N trap is carried out, and the method comprises the following sub-steps:
performing a first phosphorus ion implantation to form a first implantation region;
performing second xenon ion implantation to form a second implantation region;
performing a third arsenic ion implantation to form a third implantation region;
the first injection region, the second injection region and the third injection region form a superposition region, and the superposition region is positioned in the N-type deep well;
the junction depth of the first injection region is larger than that of the second injection region, and the junction depth of the first injection region is larger than that of the third injection region;
the doping concentration of the third implantation region is used for adjusting the threshold voltage, and before the third arsenic ion implantation, the second xenon ion implantation forms an amorphization layer in the semiconductor substrate, and the amorphization layer makes the third arsenic ion implantation uniform so as to reduce fluctuation of the threshold voltage;
annealing the overlapped region to form the N well;
step five, removing the sacrificial oxide layer;
step six, forming a grid structure on the semiconductor substrate;
step seven, performing source-drain injection in the N well at two sides of the grid structure to form a source region and a drain region; a channel region is comprised of the N-well covered by the gate structure, the channel region being located between the source region and the drain region.
12. The method of manufacturing a P-type MOSFET of claim 11, wherein: the semiconductor substrate includes a silicon substrate.
13. The method of manufacturing a P-type MOSFET of claim 11, wherein: the step of defining the active region comprises:
and forming a field oxide layer on the semiconductor substrate, isolating an active region from the field oxide layer, and forming a P-type MOSFET in the active region.
14. The method of manufacturing a P-type MOSFET of claim 11, wherein: step two, removing the cushion oxide layer by adopting a wet etching or plasma etching process;
and fifthly, removing the sacrificial oxide layer by adopting a wet etching or plasma etching process.
15. As claimed inThe method for manufacturing a P-type MOSFET of 11, comprising: in the second step, a wet oxygen oxidation process is adopted to grow the sacrificial oxide layer, and the temperature of the wet oxygen oxidation process of the sacrificial oxide layer is 1000-1300 ℃; the thickness of the sacrificial oxide layer is
16. The method of manufacturing a P-type MOSFET of claim 12, wherein: the grid structure comprises a layer of overlapped grid dielectric layer and a layer of grid conductive material.
17. The method of manufacturing a P-type MOSFET of claim 16, wherein: the gate dielectric layer is made of silicon oxide, silicon oxynitride or high dielectric constant material; the high dielectric constant material comprises hafnium oxide,
the gate conductive material layer is a polysilicon gate or a metal gate.
18. The method of manufacturing a P-type MOSFET of claim 11, further comprising:
and eighth, forming metal silicide, an interlayer film, a contact hole, a through hole and a front metal layer.
19. The method of manufacturing a P-type MOSFET of claim 11, wherein:
the implantation energy of the first phosphorus ion implantation is 100 KeV-300 KeV, and the implantation dosage is 1 multiplied by 10 13 cm -2 ～1×10 14 cm -2 ；
The implantation energy of the second xenon ion implantation is 1 KeV-100 KeV, and the implantation dosage is 1 multiplied by 10 14 cm -2 ～1×10 16 cm -2 ；
The implantation energy of the third arsenic ion implantation is 1 KeV-80 KeV, and the implantation dosage is 1×10 12 cm -2 ～1*10 14 cm -2 。
20. The method of manufacturing a P-type MOSFET of claim 19, wherein: and in the fourth step, the annealing treatment temperature of the superposition area is 1000-1300 ℃.
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