CN111584518B - Array substrate, manufacturing method thereof and display panel - Google Patents
Array substrate, manufacturing method thereof and display panel Download PDFInfo
- Publication number
- CN111584518B CN111584518B CN202010412366.5A CN202010412366A CN111584518B CN 111584518 B CN111584518 B CN 111584518B CN 202010412366 A CN202010412366 A CN 202010412366A CN 111584518 B CN111584518 B CN 111584518B
- Authority
- CN
- China
- Prior art keywords
- layer
- substrate
- metal
- array substrate
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
- G02F1/13452—Conductors connecting driver circuitry and terminals of panels
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136277—Active matrix addressed cells formed on a semiconductor substrate, e.g. of silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
Abstract
The array substrate comprises a side binding structure connected with a flexible circuit board, the flexible circuit board comprises a driving wafer, and the side binding structure is electrically connected with the driving wafer through the flexible circuit board. The side binding structure comprises a first area and a second area, wherein the first area comprises a substrate, a plurality of non-metal film layers and a plurality of metal film layers, and the second area comprises the substrate and the plurality of metal film layers.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate, a manufacturing method thereof and a display panel.
Background
With the continuous development of Liquid Crystal Display (LCD) technology, the screen ratio of light and thin electronic products is more and more required by consumers, and the full-screen has become the mainstream of mobile terminal development. Therefore, various micro-assembly technologies have been developed, such as: chip On Glass (COG) technology and Chip On Film (COF) technology. Specifically, the COG technology binds the driver chip to the glass substrate of the thin film transistor array substrate (TFT array substrate), and the COF technology binds the driver chip to the flexible substrate and connects the flexible substrate to the glass substrate of the thin film transistor array substrate (TFT array substrate). However, neither the COG technology nor the COF technology can satisfy the requirements of the full-screen, and the emergence of the side binding technology is promoted.
The conventional side binding technology is limited by the metal area (usually only a gate layer is connected with a flexible plate) on the side of a thin film transistor array substrate (TFT array substrate), so that the number of conductive ions is small and the conductivity of the device is poor.
Disclosure of Invention
An object of the present invention is to provide an array substrate, a method for manufacturing the same, and a display panel, in which a side film layer of a thin film transistor array substrate (TFT array substrate) is optimized through a mask plate, so as to greatly increase a conduction area of a bonding region.
The application provides an array substrate, which comprises a side binding structure connected with a flexible circuit board, wherein the flexible circuit board comprises a driving wafer, and the side binding structure is electrically connected with the driving wafer through the flexible circuit board;
the side binding structure comprises a first area and a second area, wherein the first area comprises a substrate, a plurality of non-metal film layers and a plurality of metal film layers, and the second area comprises the substrate and the plurality of metal film layers.
According to an embodiment of the present invention, the multi-layer metal film in the first region and the multi-layer metal film in the second region are continuous structures.
According to an embodiment of the present invention, the first region includes, from bottom to top: the substrate, the composite layer, the grid electrode insulating layer, the grid electrode layer, the interlayer dielectric layer, the first metal layer, the flat layer, the first indium tin oxide layer, the interlayer insulating layer, the second metal layer, the passivation layer and the second indium tin oxide layer.
According to an embodiment of the present invention, the second region includes, from bottom to top: the substrate, the gate layer, the first metal layer, the first ITO layer, the second metal layer and the second ITO layer.
According to an embodiment of the invention, the side binding structure is connected with the flexible circuit board by welding.
Further, the present application also provides a manufacturing method of an array substrate, including the following steps:
providing a substrate;
depositing a composite layer over the substrate, depositing a gate insulating layer over the composite layer;
etching the composite layer and the gate insulating layer in the second region by using a mask plate;
depositing a gate layer over the gate insulating layer in the first region and over the substrate in the second region;
depositing an interlayer dielectric layer on the gate electrode layer, and etching the interlayer dielectric layer in the second area by using a mask plate;
depositing a first metal layer over the interlevel dielectric layer in the first region and over the gate layer in the second region;
depositing a flat layer on the first metal layer, and etching the flat layer in the second area by using a mask plate;
depositing a first ITO layer over the planarization layer in the first region and over the first metal layer in the second region;
depositing an interlayer insulating layer on the first ITO layer, and etching the interlayer insulating layer in the second area by using a mask plate;
depositing a second metal layer over the interlayer insulating layer in the first region and over the first ITO layer in the second region;
depositing a passivation layer on the second metal layer, and etching the passivation layer in the second area by using a mask plate; and
depositing a second indium tin oxide layer over the passivation layer in the first region and over the second metal layer in the second region.
Further, the present application also provides a display panel, which includes an array substrate, a color film substrate, and a liquid crystal layer disposed between the array substrate and the color film substrate, where the array substrate includes a side binding structure connected to a flexible circuit board, the flexible circuit board includes a driver chip, and the side binding structure is electrically connected to the driver chip through the flexible circuit board;
the side binding structure comprises a first area and a second area, wherein the first area comprises a substrate, a plurality of metal film layers and a plurality of metal film layers, and the second area comprises the substrate and the plurality of metal film layers.
According to an embodiment of the present invention, the multi-layer metal film in the first region and the multi-layer metal film in the second region are continuous structures.
According to an embodiment of the present invention, the first region includes, from bottom to top: the substrate, the composite layer, the grid electrode insulating layer, the grid electrode layer, the interlayer dielectric layer, the first metal layer, the flat layer, the first indium tin oxide layer, the interlayer insulating layer, the second metal layer, the passivation layer and the second indium tin oxide layer.
According to an embodiment of the present invention, the second region includes, from bottom to top: the substrate, the gate layer, the first metal layer, the first ITO layer, the second metal layer and the second ITO layer.
The application provides an array substrate, a manufacturing method thereof and a display panel, wherein a side film layer of a thin film transistor array substrate (TFT array substrate) is optimized through a mask plate, the conduction area of a binding area is greatly improved, and the problems that the traditional side binding technology is limited by the side metal area of the TFT array substrate (TFT array substrate), the number of conductive ions is small, and the conductivity of devices is poor are solved.
Drawings
In order to illustrate the embodiments or the technical solutions in the prior art more clearly, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the invention, and it is obvious for a person skilled in the art that other drawings can be obtained according to these drawings without creative efforts.
In the drawings, there is shown in the drawings,
fig. 1 is a schematic cross-sectional view illustrating a side bonding structure of an array substrate according to an embodiment of the present disclosure.
Fig. 2 is a flowchart illustrating a method for manufacturing an array substrate according to an embodiment of the present disclosure.
Fig. 3 is a perspective schematic view of a display panel according to an embodiment of the present disclosure.
Fig. 4 is a side view of a display panel provided in an embodiment of the present application.
Detailed Description
To further illustrate the technical means and effects of the present invention, the following detailed description is given with reference to the preferred embodiments of the present invention and the accompanying drawings.
In the description of the present application, it is to be understood that the terms "upper", "lower", and the like, indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, are only for convenience in describing the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present application.
Referring to fig. 1, an embodiment of the present application provides an array substrate, including a side bonding structure 100 connected to a flexible printed circuit board, where the flexible printed circuit board includes a driver chip, and the side bonding structure 100 and the driver chip are electrically connected through the flexible printed circuit board.
Referring to fig. 1, the side binding structure 100 may include a first region and a second region, where the first region includes, from bottom to top: the substrate 1000, the composite layer 1001, the gate insulating layer 1002, the gate layer 1003, the interlayer dielectric layer 1004, the first metal layer 1005, the planarization layer 1006, the first indium tin oxide layer 1007, the interlayer insulating layer 1008, the second metal layer 1009, the passivation layer 1010, and the second indium tin oxide layer 1011. The second region includes from bottom to top: the substrate 1000, the first metal layer 1005, the first ito layer 1007, the second metal layer 1009, and the second ito layer 1011. In this embodiment, the first region includes the substrate 1000, a plurality of metal film layers, and a plurality of non-metal film layers, and the second region includes only the substrate 1000 and the plurality of metal film layers, so that the upper surface of the side binding structure 100 has a convex-concave structure, and the first region has more non-metal film layers than the second region. Compared with the conventional side binding structure, the side binding structure 100 provided by the embodiment has more metal film layers, so that the conduction area with the flexible circuit board having the driving wafer is greatly increased, the problems of less conductive ions and poorer device conduction in the conventional side binding technology are solved, and the failure risk of the product is remarkably reduced. On the other hand, the non-metal film layer can increase the stability of the multi-layer metal film layer, prevent the multi-layer metal film layer from peeling off or generating abnormity, and ensure that the device can normally operate.
It should be noted that the first region and the second region defined in this embodiment may have irregular shapes.
In this embodiment, the array substrate may be a thin film transistor array substrate.
In this embodiment, the composite layer 1001 may include a silicon nitride (SIN) layer, a silicon oxide (SIO) layer, and a polysilicon (Poly-Si) layer.
In this embodiment, the first metal layer 1005 may be a source drain layer.
In this embodiment, the material of the interlayer insulating layer 1008 may be SIN or SIO.
In this embodiment, the second metal layer 1009 may be a pixel electrode layer.
In this embodiment, since the plurality of metal films in the first region and the plurality of metal films in the second region are integrally formed and have a continuous structure, the electrical connection between the side bonding structure 100 and the flexible circuit board can be ensured, and the stability of the device can be enhanced.
In this embodiment, the number of the first regions and the second regions may be multiple and alternately arranged, so that the surface of the side binding structure 100 forms an uneven structure, and the number of the first regions and the second regions is not limited herein, and those skilled in the art can determine that the number of the first regions and the second regions has reached the preset device performance according to the concept provided by this embodiment.
In this embodiment, since the conduction area between the side binding structure 100 and the flexible printed circuit board is increased, the binding structure 100 and the flexible printed circuit board can be electrically connected directly by welding without using an intermediate to bond the two, so as to reduce the production cost of the product, simplify the production process, and increase the reliability of the product.
Further, referring to fig. 2, another embodiment of the present application further provides a method for manufacturing an array substrate, including the following steps:
s1: providing a substrate;
s2: depositing a composite layer over the substrate, depositing a gate insulating layer over the composite layer;
s3: etching the composite layer and the gate insulating layer in the second region by using a mask plate;
s4: depositing a gate layer over the gate insulating layer in the first region and over the substrate in the second region;
s5: depositing an interlayer dielectric layer on the gate electrode layer, and etching the interlayer dielectric layer in the second area by using a mask plate;
s6: depositing a first metal layer over the interlevel dielectric layer in the first region and over the gate layer in the second region;
s7: depositing a flat layer on the first metal layer, and etching the flat layer in the second area by using a mask plate;
s8: depositing a first ITO layer over the planarization layer in the first region and over the first metal layer in the second region;
s9: depositing an interlayer insulating layer on the first ITO layer, and etching the interlayer insulating layer in the second area by using a mask plate;
s10: depositing a second metal layer on the interlayer insulating layer in the first region and on the first ITO layer in the second region;
s11: depositing a passivation layer on the second metal layer, and etching the passivation layer in the second area by using a mask plate; and
s12: depositing a second indium tin oxide layer over the passivation layer in the first region and over the second metal layer in the second region.
It should be noted that, since the multi-layer metal film in the first region and the multi-layer metal film in the second region are integrally formed, and have a continuous structure, the electrical connection between the side bonding structure and the flexible circuit board can be ensured, and the stability of the device can be enhanced.
The manufacturing method of the array substrate provided by the embodiment is simple in process, and the problems that the number of conductive ions is small and the conductivity of a device is poor due to the fact that the traditional side binding technology is limited by the metal area of the side of the TFT array substrate by optimizing the film layer design of the binding area of the array substrate are solved.
Further, referring to fig. 3 and 4, another embodiment of the present application further provides a display panel 1, including an array substrate 10, a color filter substrate 30, and a liquid crystal layer 20 disposed between the array substrate 10 and the color filter substrate 30, where the array substrate 10 includes a side binding structure 100 connected to a flexible circuit board 50, the flexible circuit board 50 includes a driver chip 40, and the side binding structure 100 and the driver chip 40 are electrically connected through the flexible circuit board 50, and a specific structure of the side binding structure 100 may refer to the foregoing embodiments, and is not described herein again.
It should be noted that, referring to fig. 4, since the conduction area between the side surface bonding structure 100 and the flexible circuit board 50 is increased, the flexible circuit board 50 can be directly welded on the side surface of the side surface bonding structure 100 to electrically connect the driver chip 40 and the array substrate 10, and the two are not required to be bonded through an intermediate, thereby reducing the production cost of the product, simplifying the production process, and increasing the reliability of the product.
The application provides an array substrate, a manufacturing method thereof and a display panel, wherein a side film layer of a thin film transistor array substrate (TFT array substrate) is optimized through a mask plate, the conduction area of a binding area is greatly improved, and the problems that the traditional side binding technology is limited by the side metal area of the TFT array substrate (TFT array substrate), the number of conductive ions is small, and the conductivity of devices is poor are solved.
Although the present invention has been described with reference to a preferred embodiment, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (7)
1. An array substrate is characterized by comprising a side binding structure connected with a flexible circuit board, wherein the flexible circuit board comprises a driving wafer, and the side binding structure is electrically connected with the driving wafer through the flexible circuit board;
the side binding structure comprises a first area and a second area, the first area comprises a substrate, a plurality of layers of non-metal film layers and a plurality of layers of metal film layers, the second area comprises the substrate and the plurality of layers of metal film layers, and the second area comprises the following components from bottom to top: the substrate, the gate layer, the first metal layer, the first ITO layer, the second metal layer and the second ITO layer.
2. The array substrate of claim 1, wherein the plurality of metal films in the first region and the plurality of metal films in the second region are continuous structures.
3. The array substrate of claim 1, wherein the first region comprises, from bottom to top: the substrate, the composite layer, the grid electrode insulating layer, the grid electrode layer, the interlayer dielectric layer, the first metal layer, the flat layer, the first indium tin oxide layer, the interlayer insulating layer, the second metal layer, the passivation layer and the second indium tin oxide layer.
4. The array substrate of claim 1, wherein the flexible circuit board of the side bonding structure is connected by soldering.
5. A display panel is characterized by comprising an array substrate, a color film substrate and a liquid crystal layer arranged between the array substrate and the color film substrate, wherein the array substrate comprises a side binding structure connected with a flexible circuit board, the flexible circuit board comprises a driving wafer, and the side binding structure is electrically connected with the driving wafer through the flexible circuit board;
the side binding structure comprises a first area and a second area, the first area comprises a substrate, a plurality of metal film layers and a plurality of metal film layers, the second area comprises the substrate and the plurality of metal film layers, and the second area comprises the following components from bottom to top: the substrate, the gate layer, the first metal layer, the first ITO layer, the second metal layer and the second ITO layer.
6. The display panel according to claim 5, wherein the plurality of metal films in the first region and the plurality of metal films in the second region are continuous structures.
7. The display panel according to claim 5, wherein the first region comprises, from bottom to top: the substrate, the composite layer, the grid electrode insulating layer, the grid electrode layer, the interlayer dielectric layer, the first metal layer, the flat layer, the first indium tin oxide layer, the interlayer insulating layer, the second metal layer, the passivation layer and the second indium tin oxide layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010412366.5A CN111584518B (en) | 2020-05-15 | 2020-05-15 | Array substrate, manufacturing method thereof and display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010412366.5A CN111584518B (en) | 2020-05-15 | 2020-05-15 | Array substrate, manufacturing method thereof and display panel |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111584518A CN111584518A (en) | 2020-08-25 |
| CN111584518B true CN111584518B (en) | 2022-07-12 |
Family
ID=72113790
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010412366.5A Active CN111584518B (en) | 2020-05-15 | 2020-05-15 | Array substrate, manufacturing method thereof and display panel |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111584518B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114038869B (en) * | 2021-05-14 | 2023-01-13 | 重庆康佳光电技术研究院有限公司 | Display panel, display back panel and manufacturing method thereof |
| CN114019706B (en) * | 2021-10-21 | 2023-03-28 | 武汉华星光电技术有限公司 | Display panel and manufacturing method thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102956672A (en) * | 2011-08-18 | 2013-03-06 | 乐金显示有限公司 | Display device and fabrication method thereof |
| CN107658320A (en) * | 2017-10-26 | 2018-02-02 | 京东方科技集团股份有限公司 | Function panel and its manufacture method, display device |
| CN110109297A (en) * | 2019-03-29 | 2019-08-09 | 武汉华星光电技术有限公司 | Display panel and its manufacturing method |
| CN110491919A (en) * | 2019-08-14 | 2019-11-22 | 深圳市华星光电半导体显示技术有限公司 | Bind structure in the side of display panel |
| CN110970484A (en) * | 2019-12-20 | 2020-04-07 | 京东方科技集团股份有限公司 | Display substrate and display device |
-
2020
- 2020-05-15 CN CN202010412366.5A patent/CN111584518B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102956672A (en) * | 2011-08-18 | 2013-03-06 | 乐金显示有限公司 | Display device and fabrication method thereof |
| CN107658320A (en) * | 2017-10-26 | 2018-02-02 | 京东方科技集团股份有限公司 | Function panel and its manufacture method, display device |
| CN110109297A (en) * | 2019-03-29 | 2019-08-09 | 武汉华星光电技术有限公司 | Display panel and its manufacturing method |
| CN110491919A (en) * | 2019-08-14 | 2019-11-22 | 深圳市华星光电半导体显示技术有限公司 | Bind structure in the side of display panel |
| CN110970484A (en) * | 2019-12-20 | 2020-04-07 | 京东方科技集团股份有限公司 | Display substrate and display device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111584518A (en) | 2020-08-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10338443B2 (en) | Amorphous silicon thin film transistor-liquid crystal display device and method of manufacturing the same | |
| US11126044B1 (en) | Display device comprising a flip chip film connected to a connecting surface of a plurality of bonding pins and manufacturing method thereof | |
| US7732266B2 (en) | Thin film array panel and manufacturing method thereof | |
| US7947539B2 (en) | Thin film transistor array panel for a display device and a method of manufacturing the same | |
| US7459753B2 (en) | Electro-optical device, method for manufacturing electro-optical device, and electronic apparatus | |
| US11251257B2 (en) | Manufacturing method of display panel having pad comprising embedded part and protruded part | |
| US20170250199A1 (en) | Display device | |
| JP2003107523A (en) | Liquid crystal display device | |
| JP2007025562A (en) | Liquid crystal display and its manufacturing method | |
| CN107546242B (en) | Display apparatus | |
| CN111584518B (en) | Array substrate, manufacturing method thereof and display panel | |
| US20090026462A1 (en) | Wiring substrate and method of manufacturing same, and display device | |
| US20070139572A1 (en) | Thin film transistor array panel for liquid crystal display and manufacturing method thereof | |
| JPH05243333A (en) | Thin film field-effect transistor substrate | |
| CN100378560C (en) | Active matrix substrate and method of manufacturing the same | |
| KR20040090697A (en) | Display device and method of manufacturing display device | |
| JP3713197B2 (en) | Liquid crystal display device | |
| JP4253181B2 (en) | Image display panel, photomask, image display device, and method for manufacturing image display panel | |
| EP1478971B1 (en) | Liquid crystal display device | |
| US20120257133A1 (en) | Manufacturing method of liquid crystal display device and liquid crystal display device | |
| CN111341790B (en) | Display device and manufacturing method thereof | |
| CN218995843U (en) | Array substrate, display panel and display device | |
| CN114545689B (en) | Liquid crystal display panel, preparation method thereof and display device | |
| JP2003007749A (en) | Integrated circuit and display | |
| JP2004118089A (en) | Liquid crystal display |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |