CN111584512A - Array substrate, manufacturing method thereof and display device - Google Patents
Array substrate, manufacturing method thereof and display device Download PDFInfo
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- CN111584512A CN111584512A CN202010407095.4A CN202010407095A CN111584512A CN 111584512 A CN111584512 A CN 111584512A CN 202010407095 A CN202010407095 A CN 202010407095A CN 111584512 A CN111584512 A CN 111584512A
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- 239000000758 substrate Substances 0.000 title claims abstract description 86
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 33
- 239000004065 semiconductor Substances 0.000 claims abstract description 34
- 238000000034 method Methods 0.000 claims abstract description 26
- 230000008569 process Effects 0.000 claims abstract description 15
- 238000000059 patterning Methods 0.000 claims abstract description 10
- 229920002120 photoresistant polymer Polymers 0.000 claims description 55
- 239000000463 material Substances 0.000 claims description 24
- 229910045601 alloy Inorganic materials 0.000 claims description 19
- 239000000956 alloy Substances 0.000 claims description 19
- 230000000149 penetrating effect Effects 0.000 claims description 12
- 229910001182 Mo alloy Inorganic materials 0.000 claims description 6
- 229910052750 molybdenum Inorganic materials 0.000 claims description 3
- 239000000203 mixture Substances 0.000 abstract description 4
- 238000005516 engineering process Methods 0.000 abstract description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 24
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 7
- 229910052802 copper Inorganic materials 0.000 description 7
- 239000010949 copper Substances 0.000 description 7
- 239000010408 film Substances 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- 238000007796 conventional method Methods 0.000 description 4
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 4
- 238000002161 passivation Methods 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000005260 corrosion Methods 0.000 description 3
- 230000007797 corrosion Effects 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 230000000903 blocking effect Effects 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 238000009877 rendering Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000000638 stimulation Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
- G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Theoretical Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
The application provides an array substrate, a manufacturing method thereof and a display device, wherein the manufacturing method comprises the following steps: forming a first patterned conductive layer on the substrate, wherein the first patterned conductive layer comprises a gate; forming an insulating layer covering the first patterned conductive layer and the substrate; forming a whole semiconductor layer on one side of the insulating layer, which is far away from the substrate; forming a second conducting layer on the whole surface of one side, far away from the substrate, of the semiconductor layer, patterning the semiconductor layer and the second conducting layer by adopting a composition process to obtain an active layer, a source drain electrode, a first conducting electrode and a first conducting component, wherein the active layer is arranged corresponding to the grid electrode, and the source drain electrode is electrically connected with the active layer; and forming a patterned shading insulating layer which covers the source drain electrode, the active layer and the insulating layer and exposes the first conductive electrode and the first conductive member to obtain the array substrate. Compared with the traditional technology, the manufacturing process is simplified and the number of used photomasks is reduced while the light shielding layer is formed.
Description
Technical Field
The present disclosure relates to the field of display technologies, and in particular, to an array substrate, a manufacturing method thereof, and a display device.
Background
The submillimeter light-emitting diode (Mini-LED) backboard is used as a product for combining a miniaturized light-emitting diode and a backboard, has the characteristics of high contrast, high color rendering performance and the like which are comparable to those of an organic light-emitting diode, the cost is only about 60 percent of that of the organic light-emitting diode, and the submillimeter light-emitting diode backboard is easier to implement compared with the organic light-emitting diode, so the submillimeter light-emitting diode backboard becomes the current research hotspot.
However, the conventional sub-millimeter light emitting diode back plate has the problems of complicated process and more masks.
Disclosure of Invention
The present disclosure provides an array substrate, a method for manufacturing the same, and a display device, so as to simplify a manufacturing process of the array substrate and reduce the number of masks used in the manufacturing process of the array substrate.
In order to achieve the above object, the present application provides a method for manufacturing an array substrate, the method comprising the steps of:
forming a first patterned conductive layer on a substrate, the first patterned conductive layer including a gate electrode;
forming an insulating layer covering the first patterned conductive layer and the substrate;
forming a whole semiconductor layer on one side of the insulating layer, which is far away from the substrate;
forming a second whole conductive layer on one side of the semiconductor layer, which is far away from the substrate, and patterning the semiconductor layer and the second conductive layer by adopting a patterning process to obtain an active layer, a source drain electrode, a first conductive electrode and a first conductive member, wherein the active layer is arranged corresponding to the grid electrode, and the source drain electrode is arranged corresponding to the active layer and is electrically connected with the active layer;
and forming a patterned shading insulating layer which covers the source drain electrode, the active layer and the insulating layer and exposes the first conductive electrode and the first conductive member to obtain the array substrate.
In the array substrate, the first patterned conductive layer further includes a second conductive electrode and a second conductive member, the first conductive electrode is disposed corresponding to the second conductive electrode, and the first conductive member is disposed corresponding to the second conductive member, and the manufacturing method further includes the following steps:
forming a first contact hole and a second contact hole penetrating through the insulating layer and the semiconductor layer, the first contact hole being disposed corresponding to the second conductive electrode, the second contact hole being disposed corresponding to the second conductive member, the first conductive electrode being electrically connected to the second conductive electrode through the first contact hole, and the first conductive member being electrically connected to the second conductive member through the second contact hole.
In the array substrate, the material for preparing the patterned light-shielding insulating layer is selected from at least one of a black organic photoresist or ink.
In the array substrate, the first patterned conductive layer is made of a material including Mo or a Mo alloy, and the second conductive layer is made of a material including Mo or a Mo alloy.
In the array substrate, the first patterned conductive layer is made of a MoTiNi alloy, and the second conductive layer is made of a MoTiNi alloy.
An array substrate, comprising:
a substrate;
a first patterned conductive layer formed on the substrate, the first patterned conductive layer including a gate electrode;
an insulating layer covering the first patterned conductive layer and the substrate;
the patterned semiconductor layer is formed on one side, away from the substrate, of the insulating layer and comprises an active layer;
the second patterned conducting layer is formed on one side, far away from the substrate, of the patterned semiconductor layer and comprises a first conducting component, a source electrode, a drain electrode and a first conducting electrode, and the source electrode and the drain electrode are arranged corresponding to the active layer and are electrically connected with the active layer; and
and a patterned light-shielding insulating layer covering the source-drain electrode, the insulating layer, and the active layer and exposing the first conductive electrode and the first conductive member.
In the array substrate, the first patterned conductive layer further includes a second conductive electrode and a second conductive member, the first conductive electrode is disposed corresponding to the second conductive electrode, the first conductive member is disposed corresponding to the second conductive member, the first conductive electrode and the second conductive electrode are electrically connected through a first contact hole penetrating through the patterned semiconductor layer and the insulating layer, and the first conductive member and the second conductive member are electrically connected through a second contact hole penetrating through the patterned semiconductor layer and the insulating layer.
In the array substrate, the material for preparing the patterned light-shielding insulating layer is selected from at least one of a black organic photoresist or ink.
In the array substrate, the first patterned conductive layer is made of a material including a MoTiNi alloy, and the second patterned conductive layer is made of a material including a MoTiNi alloy.
A display device comprises a backlight module, and the backlight module comprises the array substrate.
Has the advantages that: the application provides an array substrate, a manufacturing method thereof and a display device, wherein the manufacturing method comprises the following steps: forming a first patterned conductive layer on the substrate, wherein the first patterned conductive layer comprises a gate; forming an insulating layer covering the first patterned conductive layer and the substrate; forming a whole semiconductor layer on one side of the insulating layer, which is far away from the substrate; forming a second conducting layer on the whole surface of one side, far away from the substrate, of the semiconductor layer, patterning the semiconductor layer and the second conducting layer by adopting a composition process to obtain an active layer, a source drain electrode, a first conducting electrode and a first conducting component, wherein the active layer is arranged corresponding to the grid electrode, and the source drain electrode is electrically connected with the active layer; and forming a patterned shading insulating layer which covers the source drain electrode, the active layer and the insulating layer and exposes part of the first conductive electrode and the first conductive member to obtain the array substrate. Compared with the prior art, the light shielding layer is formed by forming the patterned light shielding insulating layer which covers the source drain electrode, the active layer and the insulating layer and exposes the first conductive electrode and the first conductive member, so that the light generated current of the active layer is avoided, meanwhile, a passivation layer, an indium tin oxide and other conductive layers are not required to be formed, a light shield is not required to be added to pattern the passivation layer and the indium tin oxide layer, the manufacturing process is simplified, and the number of used light shields is reduced.
Drawings
FIG. 1 is a schematic view illustrating a process of manufacturing a backlight module without a light-shielding layer by a conventional method;
FIG. 2 is a schematic view of a conventional process for manufacturing a backlight module including a light-shielding layer;
FIG. 3 is a schematic flow chart illustrating a method for fabricating an array substrate according to an embodiment of the present disclosure;
fig. 4 is a schematic view of a process for manufacturing the array substrate according to the flowchart shown in fig. 3.
The drawings are numbered as follows:
1011, 2011 second conductive member; 1012, 2012 gates; 102 a first insulating layer; 1031, 2031 a layer of amorphous silicon; 1032, 2032 n-type doped amorphous silicon layer; 100a first via; 104, 204 second conductive layer; 1041 a first conductive electrode; 1042 a first conductive member; 1043, 2043 source drain electrodes; 100b a second via; 100c a third via; 105 a second insulating layer; 106 a conductive block; 107 a third insulating layer; 108 a light-shielding layer; 2013 a second conductive electrode; 202 an insulating layer; 200a first contact hole; 200b a second contact hole; 205 patterning the light blocking insulating layer.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Please refer to fig. 1, which is a schematic process diagram of a conventional method for manufacturing a backlight module without a light-shielding layer. The manufacturing method of the backlight module without the shading layer manufactured by the traditional method comprises the following steps:
in step S101, a gate 1012 and a second conductive member 1011 are formed on the same layer on the substrate.
Specifically, a first conductive layer is formed over the entire surface of the substrate, an entire surface photoresist layer covering the first conductive layer is formed, the photoresist layer is exposed to light using a first mask, and the photoresist layer is developed using a developing solution, the first conductive layer not covered with the photoresist layer is etched, and the remaining photoresist layer is removed, so that the gate electrode 1012 and the second conductive member 1011 are obtained, as shown in fig. 1 (a 1).
S102, forming a first insulating layer covering the grid electrode, the second conductive component and the substrate, forming a semiconductor layer on one side of the first insulating layer, which is far away from the substrate, forming a first through hole which penetrates through the first insulating layer and the semiconductor layer and is arranged corresponding to the second conductive component, and forming a second conductive layer in the first through hole and on the semiconductor layer.
Specifically, the first insulating layer 102 covering the gate electrode 1012, the second conductive member 1011, and the substrate is formed by chemical vapor deposition. The first insulating layer 102 is a gate insulating layer. An amorphous silicon layer 1031 and an n-type doped amorphous silicon layer 1032 are sequentially formed to cover the first insulating layer 102.
A photoresist layer is formed on the n-type doped amorphous silicon layer 1032 over the entire surface, the photoresist layer is exposed to a second photomask, and after a developing process using a developing solution, the n-type doped amorphous silicon layer 1032, the amorphous silicon layer 1031, and the first insulating layer 102 corresponding to the second conductive member 1011 are etched to form a first via hole 100a penetrating through the first insulating layer 102, the n-type doped amorphous silicon layer 1032, and the amorphous silicon layer 1031.
A sputter deposition is used to form the entire second conductive layer 104 in the first via 100a and on the n-doped amorphous silicon layer 1032, as shown in fig. 1 (B1).
S103: and patterning the second conductive layer and the semiconductor layer by using a composition process to obtain a first conductive member, a source-drain electrode, an active layer and a first conductive electrode.
Specifically, a whole photoresist layer is formed on the second conductive layer 104, and the photoresist layer is exposed by using a halftone gray-scale mask to define a photoresist complete removal region, a photoresist semi-reserved region, and a photoresist complete reserved region. After the photoresist in the photoresist completely removed region is processed by the developer, the second conductive layer 104, the amorphous silicon layer 1031, and the n-type doped amorphous silicon layer 1032 in the photoresist completely removed region are etched away to obtain a first conductive member 1042 and a first conductive electrode 1041, wherein the first conductive member 1042 is electrically connected to the second conductive member 1011 through the first via hole 100 a; after the photoresist in the photoresist semi-reserved region is processed by the developer, the n-type doped amorphous silicon layer 1032 and the second conductive layer 104 in the photoresist semi-reserved region are etched away to obtain the source/drain electrode 1043 and the active layer, the source/drain electrode 1043 is disposed corresponding to the active layer and electrically connected to the active layer, and the photoresist layer in the photoresist complete reserved region is removed, as shown in fig. 1 (C1).
S104: and forming a second insulating layer which covers the first conductive electrode, the first conductive component, the source and drain electrodes, the active layer and the first insulating layer and is provided with a second through hole and a third through hole.
Forming a second insulating layer 105 covering the first conductive electrode 1041, the first conductive member 1042, the source/drain electrode 1043, the active layer, and the first insulating layer 102 by chemical vapor deposition, forming a photoresist layer on the entire surface of the second insulating layer 105, performing exposure and developing treatment on the photoresist layer by using a fourth photomask, etching the second insulating layer not covered by the photoresist layer, removing the remaining photoresist layer, and forming a second via hole 100b penetrating through the second insulating layer 105 and corresponding to the first conductive member 1042 and a third via hole 100c penetrating through the second insulating layer 105 and corresponding to the first conductive electrode 1041. The second insulating layer 105 is a passivation layer, as shown in (D1) of fig. 1.
S105: a conductive bump 106 is formed on the second via 100b and the second insulating layer 105.
Specifically, a full-surface third conductive layer is formed in the second via hole 100b, the third via hole 100c and the second insulating layer 105, a full-surface photoresist layer is formed on the third conductive layer, the photoresist layer is exposed by using a fifth photomask and developed by using a developing solution, the third conductive layer is etched, the remaining photoresist layer is removed, the first conductive electrode 1041 is exposed, the conductive block 106 is obtained, a flip-chip film (not shown) is bonded on the conductive block 106, and a submillimeter light emitting diode (not shown) is bonded on the first conductive electrode 1041, as shown in fig. 1 (E1). The third conducting layer is made of indium tin oxide. The conductive block 106 is connected to the first conductive member 1042 through the second via 100 b.
From the above steps, the process of manufacturing the backlight module without the light shielding layer by the conventional method needs to use five photomasks, and the light shielding layer can cause the active layer to easily generate the photo-generated current under the action of light, thereby affecting the electrical performance of the thin film transistor of the backlight module.
Please refer to fig. 2, which is a schematic diagram illustrating a process of manufacturing a backlight module including a light-shielding layer by a conventional method. The (a2) - (E2) in fig. 2 are the same as (a1) - (E1) in fig. 1, and are not described in detail here. The difference is that after the conductive block 106 is formed, a third insulating layer 107 is formed to cover the conductive block 106, the second insulating layer 105 and the first conductive electrode 1041, a light-shielding layer 108 is formed on the third insulating layer 107, and after the light-shielding layer 108 is exposed and developed with a developer by using a sixth mask, a portion of the light-shielding layer 108 corresponding to the conductive block 106 and the first conductive electrode 1041 is removed to obtain a patterned light-shielding layer, as shown in (F2) in fig. 2.
Etching the third insulating layer 107 by using the patterned light-shielding layer as an etching barrier layer, and removing the conductive block 106 and the third insulating layer 107 on the first conductive electrode 1041, so that the conductive block 106 and the first conductive electrode 1041 are exposed, the flip-chip on film is bound to the conductive block 106, and the submillimeter light-emitting diode is bound to the first conductive electrode 1041, thereby obtaining the backlight module including the light-shielding layer, as shown in fig. 2 (G2).
As can be seen from the above, the manufacturing process of the conventional backlight module including the light-shielding layer requires six photomasks, the number of photomasks used is large, and the manufacturing process is complicated.
Please refer to fig. 3, which is a flowchart illustrating a method for manufacturing an array substrate according to an embodiment of the present disclosure. The manufacturing method of the array substrate comprises the following steps:
s201, a first patterned conductive layer is formed on a substrate, wherein the first patterned conductive layer comprises a grid electrode.
Specifically, a first conductive layer is formed over a glass substrate, a photoresist layer is formed over the first conductive layer, the photoresist layer is exposed by a first mask and developed by a developer, the first conductive layer not covered by the photoresist layer is etched, and the remaining photoresist layer is removed to obtain a first patterned conductive layer, where the first patterned conductive layer includes a gate 2012, a second conductive member 2011 and a second conductive electrode 2013, and the gate 2012 is located between the second conductive member 2011 and the second conductive electrode 2013, as shown in fig. 4 (a 3).
The first patterned conductive layer is made of a material including at least one of molybdenum (Mo), a molybdenum alloy, copper, aluminum, and silver. For example, the first patterned conductive layer is made of a material including a MoTiNi alloy. Specifically, the first conductive layer comprises a MoTiNi alloy layer, a copper layer and a MoTiNi alloy layer which are sequentially stacked on the substrate, wherein the MoTiNi alloy layer is used for blocking diffusion of the copper layer on one hand, the MoTiNi alloy layer is used for preventing the copper layer from being oxidized on the other hand, and the copper layer is used for improving conductivity.
S202, forming an insulating layer covering the first patterned conductive layer and the substrate.
Specifically, the insulating layer 202 covering the gate 2012, the second conductive member 2011, the second conductive electrode 2013 and the substrate is formed by chemical vapor deposition, as shown in fig. 4 (B3).
The preparation material of the insulating layer is at least one selected from silicon nitride and silicon oxide. The thickness of the insulating layer is 800-6000 angstroms. Specifically, the insulating layer is a gate insulating layer, the thickness of the gate insulating layer is 1500 angstroms, and the gate insulating layer is a silicon nitride layer.
And S203, forming a whole semiconductor layer on one side of the insulating layer, which is far away from the substrate.
Specifically, the entire amorphous silicon layer 2031 and the n-doped amorphous silicon layer 2032 are sequentially formed on the side of the insulating layer 202 away from the substrate. Forming a whole photoresist layer on the n-doped amorphous silicon layer 2032, exposing and developing the photoresist layer with a second photomask, etching a portion of the amorphous silicon layer 2031, the n-doped amorphous silicon layer 2032 and the insulating layer 202 corresponding to the second conductive electrode 2013 and the second conductive member 2011, and removing the remaining photoresist to form a first contact hole 200a and a second contact hole 200b penetrating the insulating layer 202 and the semiconductor layers (2031, 2032), wherein the first contact hole 200a is disposed corresponding to the second conductive electrode 2013 and the second contact hole 200b is disposed corresponding to the second conductive member 2011.
And S204, forming a second conducting layer on the whole surface of one side, far away from the substrate, of the semiconductor layer, and patterning the semiconductor layer and the second conducting layer by adopting a composition process to obtain an active layer, a source drain electrode, a first conducting electrode and a first conducting component, wherein the active layer is arranged corresponding to the grid electrode, and the source drain electrode is arranged corresponding to the active layer and is electrically connected with the active layer.
Specifically, the entire surface of the second conductive layer 204 is formed in the first contact hole 200a, the second contact hole 200B, and the n-type doped amorphous silicon layer 2032, as shown in fig. 4 (B3).
Forming a whole photoresist layer on the second conductive layer 204, performing an exposure process on the photoresist layer by using a halftone gray scale mask to define a photoresist semi-reserved region, a photoresist completely-reserved region and a photoresist completely-removed region, developing the exposed photoresist layer by using a developing solution, removing the photoresist layer in the photoresist completely-removed region, etching the second conductive layer 204, the amorphous silicon layer 2031 and the n-type doped amorphous silicon layer 2032 in the photoresist completely-removed region to obtain a first conductive electrode 2041 and a first conductive member 2042, wherein the first conductive electrode 2041 corresponds to the second conductive electrode 2013, the first conductive member 2042 corresponds to the second conductive member 2011, the first conductive electrode 2041 and the second conductive electrode 2013 are electrically connected through a first contact hole 200a, and the first conductive member 2042 and the second conductive member are electrically connected through a second contact hole 200b 2011. The photoresist layer of the photoresist semi-reserved region is removed, the second conductive layer 204 and the n-type doped amorphous silicon layer 2032 of the photoresist semi-reserved region are etched to obtain the active layer and the source/drain electrode 2043, the photoresist layer of the photoresist fully reserved region is removed, and the source/drain electrode 2043, the first conductive electrode 2041 and the first conductive member 2042 are exposed, as shown in fig. 4 (C3).
In this embodiment, the preparation material of the second conductive layer includes Mo or a Mo alloy. For example, the second conductive layer includes a MoTiNi alloy layer, a copper layer, and a MoTiNi alloy layer sequentially stacked on the n-type doped amorphous silicon layer 2032. The MoTiNi alloy layer has good oxidation resistance and corrosion resistance, and plays a role in preventing the copper layer from being oxidized.
And S205, forming a patterned shading insulating layer which covers the source drain electrode, the active layer and the insulating layer and exposes the first conductive electrode and the first conductive member to obtain the array substrate.
Specifically, a whole light-shielding insulating layer covering the source/drain electrode 2043, the active layer, the insulating layer 202, the first conductive electrode 2041, and the first conductive member 2042 is formed by a coating process or the like, the whole light-shielding insulating layer is exposed by a fourth mask, and the light-shielding insulating layer is developed by a developer to obtain the patterned light-shielding insulating layer 205, as shown in fig. 4 (D3).
In the present embodiment, the material for preparing the patterned light-shielding insulating layer 205 is a black organic photoresist. When the material for preparing the patterned light-shielding insulating layer 205 is a black organic photoresist, the thickness of the patterned light-shielding insulating layer 205 is 1 micron to 2 microns, such as 1.5 microns, 1.2 microns, and 1.8 microns. In other embodiments, the material for preparing the patterned light-shielding insulating layer 205 may also include ink, such as white ink. The patterned light-shielding insulating layer 205 plays a role of shielding light from the active layer and also plays a role of protecting the second patterned conductive layer.
When the array substrate is applied to a backlight module, the submillimeter led is bonded to the first conductive electrode 2041, and the flip chip film is bonded to the first conductive member 2042.
Compared with the prior art, the manufacturing method of the array substrate has the advantages that the patterned shading insulating layer which covers the source-drain electrode, the active layer and the insulating layer and exposes the first conductive electrode and the first conductive member is directly formed, so that the manufacturing and patterning of the passivation layer and the indium tin oxide layer are omitted, the manufacturing process of the array substrate is simplified, one to two photomasks are saved, and four photomasks are used in the whole manufacturing process of the array substrate. And the patterned shading insulating layer prevents the active layer from generating photon-generated carriers, so that the off-state current characteristic of the thin film transistor is improved.
The present application further provides a backlight module, the backlight module includes an array substrate, the array substrate includes:
a substrate;
a first patterned conductive layer formed on the substrate, the first patterned conductive layer including a gate electrode;
an insulating layer covering the first patterned conductive layer and the substrate;
the patterned semiconductor layer is formed on one side, far away from the substrate, of the insulating layer and comprises an active layer;
the second patterned conducting layer is formed on one side, far away from the substrate, of the patterned semiconductor layer and comprises a first conducting component, a source drain electrode and a first conducting electrode, the active layer is arranged corresponding to the grid electrode, and the source drain electrode is arranged corresponding to the active layer and is electrically connected with the active layer; and
and a patterned light-shielding insulating layer covering the source/drain electrodes, the insulating layer, and the active layer and exposing the first conductive electrode and the first conductive member.
In this embodiment, the first patterned conductive layer further includes a second conductive electrode and a second conductive member, the first conductive electrode is disposed corresponding to the second conductive electrode, the first conductive member is disposed corresponding to the second conductive member, the first conductive electrode and the second conductive electrode are electrically connected through a first contact hole penetrating through the patterned semiconductor layer and the insulating layer, and the first conductive member and the second conductive member are electrically connected through a second contact hole penetrating through the patterned semiconductor layer and the insulating layer. The first conductive electrode is electrically connected with the second conductive electrode, so that the conductive performance of the first conductive electrode is improved. The first conductive member is connected with the second conductive member, so that the conductive performance of the first conductive member is improved.
In this embodiment, the material for preparing the patterned light-shielding insulating layer is selected from at least one of a black organic photoresist or an ink. The patterned shading insulating layer plays a role in shading light on one hand, avoids photo-generated carriers generated by the stimulation of light on the active layer, and plays a role in protecting the film layer covered by the patterned shading insulating layer on the other hand.
In this embodiment, the material for preparing the first patterned conductive layer includes a MoTiNi alloy, and the material for preparing the second patterned conductive layer includes a MoTiNi alloy. The MoTiNi alloy has good oxidation resistance and corrosion resistance, and the oxidation resistance and the corrosion resistance of the first patterned conductive layer and the second patterned conductive layer are improved.
In this embodiment, the backlight module further includes a submillimeter led and a flip-chip film, the submillimeter led is bound on the first conductive electrode 2041, and the flip-chip film is bound on the first conductive member 2042.
In this embodiment, the preparation material of the active layer is amorphous silicon or metal oxide.
In this embodiment, the insulating layer is made of a material selected from at least one of silicon nitride and silicon oxide.
The application also provides a display device which comprises the backlight module.
The above description of the embodiments is only for assisting understanding of the technical solutions and the core ideas thereof; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.
Claims (10)
1. A manufacturing method of an array substrate is characterized by comprising the following steps:
forming a first patterned conductive layer on a substrate, the first patterned conductive layer including a gate electrode;
forming an insulating layer covering the first patterned conductive layer and the substrate;
forming a whole semiconductor layer on one side of the insulating layer, which is far away from the substrate;
forming a second whole conductive layer on one side of the semiconductor layer, which is far away from the substrate, and patterning the semiconductor layer and the second conductive layer by adopting a patterning process to obtain an active layer, a source drain electrode, a first conductive electrode and a first conductive member, wherein the active layer is arranged corresponding to the grid electrode, and the source drain electrode is arranged corresponding to the active layer and is electrically connected with the active layer;
and forming a patterned shading insulating layer which covers the source drain electrode, the active layer and the insulating layer and exposes the first conductive electrode and the first conductive member to obtain the array substrate.
2. The method for manufacturing the array substrate according to claim 1, wherein the first patterned conductive layer further comprises a second conductive electrode and a second conductive member, the first conductive electrode is disposed corresponding to the second conductive electrode, and the first conductive member is disposed corresponding to the second conductive member, the method further comprising the steps of:
forming a first contact hole and a second contact hole penetrating through the insulating layer and the semiconductor layer, the first contact hole being disposed corresponding to the second conductive electrode, the second contact hole being disposed corresponding to the second conductive member, the first conductive electrode being electrically connected to the second conductive electrode through the first contact hole, and the first conductive member being electrically connected to the second conductive member through the second contact hole.
3. The method for manufacturing the array substrate according to claim 1, wherein the patterned light-shielding insulating layer is made of at least one material selected from a black organic photoresist and an ink.
4. The method of claim 1, wherein the first patterned conductive layer is made of a material comprising Mo or a Mo alloy, and the second conductive layer is made of a material comprising Mo or a Mo alloy.
5. The method for manufacturing the array substrate according to claim 1 or 4, wherein the first patterned conductive layer is made of a MoTiNi alloy, and the second conductive layer is made of a MoTiNi alloy.
6. An array substrate, comprising:
a substrate;
a first patterned conductive layer formed on the substrate, the first patterned conductive layer including a gate electrode;
an insulating layer covering the first patterned conductive layer and the substrate;
the patterned semiconductor layer is formed on one side, away from the substrate, of the insulating layer and comprises an active layer;
the second patterned conducting layer is formed on one side, far away from the substrate, of the patterned semiconductor layer and comprises a first conducting component, a source electrode, a drain electrode and a first conducting electrode, the active layer is arranged corresponding to the grid electrode, and the source electrode and the drain electrode are arranged corresponding to the active layer and are electrically connected with the active layer; and
and a patterned light-shielding insulating layer covering the source-drain electrode, the insulating layer, and the active layer and exposing the first conductive electrode and the first conductive member.
7. The array substrate of claim 6, wherein the first patterned conductive layer further comprises a second conductive electrode and a second conductive member, the first conductive electrode is disposed corresponding to the second conductive electrode, the first conductive member is disposed corresponding to the second conductive member, the first conductive electrode and the second conductive electrode are electrically connected through a first contact hole penetrating the patterned semiconductor layer and the insulating layer, and the first conductive member and the second conductive member are electrically connected through a second contact hole penetrating the patterned semiconductor layer and the insulating layer.
8. The array substrate of claim 6, wherein the patterned light-shielding insulating layer is made of at least one material selected from a black organic photoresist and an ink.
9. The array substrate of claim 6, wherein the first patterned conductive layer is made of a material comprising a MoTiNi alloy, and the second patterned conductive layer is made of a material comprising a MoTiNi alloy.
10. A display device, comprising a backlight module, wherein the backlight module comprises the array substrate according to any one of claims 6 to 9.
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