CN112420765B - Lamp panel, manufacturing method thereof and display device - Google Patents
Lamp panel, manufacturing method thereof and display device Download PDFInfo
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- CN112420765B CN112420765B CN202011265394.5A CN202011265394A CN112420765B CN 112420765 B CN112420765 B CN 112420765B CN 202011265394 A CN202011265394 A CN 202011265394A CN 112420765 B CN112420765 B CN 112420765B
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- 238000000034 method Methods 0.000 claims description 17
- 238000000059 patterning Methods 0.000 claims description 10
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- 238000005530 etching Methods 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 7
- 239000000463 material Substances 0.000 claims description 6
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 claims description 5
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
- G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
- H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
- H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
- H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body
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Abstract
The application provides a lamp panel, a manufacturing method thereof and a display device, wherein a first halftone mask plate is adopted to pattern a first insulating layer and a semiconductor layer, a second halftone mask plate is adopted to pattern a second conducting layer and a third conducting layer so as to reduce the number of used photomasks, and a third conducting member is formed on the second conducting member so as to avoid oxidation of the second conducting member and avoid the problem of electrical connection failure of the second conducting member, the third conducting member and the first conducting member.
Description
Technical Field
The application relates to the technical field of display, in particular to a lamp panel, a manufacturing method of the lamp panel and a display device.
Background
The miniaturized Light Emitting Diode has been developed as one of the hot spots of the future Display technology, and compared with the current Liquid Crystal Display (LCD) and Organic Light Emitting Diode (OLED) Display devices, the miniaturized Light Emitting Diode has the advantages of fast response, high color gamut, high resolution, low energy consumption, and the like. However, the Micro light emitting diode has many technical difficulties and complex technology, especially the Micro light emitting diode particle becomes the technical bottleneck by the huge transfer technology of the key technology, while the sub-millimeter light emitting diode (Mini-LED) has the characteristics of high contrast, high color rendering performance and the like which are comparable to those of the organic light emitting diode as the product of combining the Micro light emitting diode and the back plate, the cost of the liquid crystal display is slightly higher, the cost is only about six times that of the organic light emitting diode, and the implementation is easier compared with the Micro light emitting diode (Micro-LED) and the organic light emitting diode, so the sub-millimeter light emitting diode becomes the layout hotspot of various large panel manufacturers.
At present, how to reduce the number of light shades used in the sub-millimeter light emitting diode backlight module and ensure the reliability of the sub-millimeter light emitting diode backlight module is a problem to be solved.
Disclosure of Invention
The application aims to provide a lamp panel, a manufacturing method of the lamp panel and a display device, so that the number of light shades used is reduced, and the reliability of the lamp panel is guaranteed.
In order to achieve the purpose, the method for manufacturing the lamp panel comprises the following steps:
forming a first patterned conductive layer on a substrate, wherein the first patterned conductive layer comprises a grid arranged in a first area and a first conductive member arranged in a second area, and the substrate is provided with the first area, the second area and a third area which are mutually spaced;
sequentially forming a first insulating layer and a semiconductor layer which cover the first patterned conductive layer and the substrate, patterning the first insulating layer and the semiconductor layer by adopting a first halftone mask plate, forming via holes which are arranged corresponding to the first conductive members on the first insulating layer and the semiconductor layer and forming a patterned semiconductor layer, wherein the patterned semiconductor layer comprises an active layer which is arranged corresponding to the grid electrode;
forming a second conductive layer in the via hole, on the first insulating layer and on the patterned semiconductor layer, forming a third conductive layer on the second conductive layer, patterning the second conductive layer and the third conductive layer by using a second halftone mask, forming a second patterned conductive layer and forming a third conductive member on the second conductive member, where the second patterned conductive layer includes the second conductive member formed in the second region, a source/drain electrode formed in the first region, and a conductive pad formed in the third region, the second conductive member is electrically connected to the first conductive member through the via hole, and the source/drain electrode is disposed on the active layer;
forming a second insulating layer which covers the first insulating layer, the source-drain electrode and the active layer and exposes the third conductive member and the conductive pad;
and binding the light-emitting element on the conductive pad through a connecting piece to obtain the lamp panel.
In the manufacturing method of the lamp panel, the third conductive member is made of indium tin oxide, the second patterned conductive layer is made of copper, and the connecting member is made of tin.
In the method for manufacturing the lamp panel, the patterning the first insulating layer and the semiconductor layer by using a first halftone mask includes the following steps:
forming a light resistance layer on the semiconductor layer, and exposing the light resistance layer by using a first halftone mask plate to define a first light resistance removing area, a first light resistance semi-reserving area and a first light resistance complete-reserving area; the first photoresistance removing area corresponds to the first conductive component, an area between the first area and the second area and an area between the first area and the third area correspond to the first photoresistance semi-reserved area, and the first area, partial areas of the second area and the third area correspond to the first photoresistance complete-reserved area; developing the exposed photoresist layer by using a developing solution;
etching and removing the semiconductor layer and the first insulating layer in the first photoresist removing area to form the via hole;
and removing the photoresist layer of the first photoresist semi-reserved area, etching to remove the semiconductor layer of the first photoresist semi-reserved area, and removing the photoresist layer of the first photoresist complete reserved area to form the patterned semiconductor layer.
In the method for manufacturing the lamp panel, patterning the second conductive layer and the third conductive layer by using a second halftone mask includes the following steps:
forming a photoresist layer on the third conductive layer, and exposing the photoresist layer by using a second half-tone mask plate to define a second photoresist removing area, a second photoresist semi-reserved area and a second photoresist complete reserved area; the regions between the first region and the second region, between the first region and the third region, and a part of the first region correspond to the second photoresist removal region, the part of the first region and the third region correspond to the second photoresist semi-reserved region, and the second region corresponds to the second photoresist complete-reserved region; developing the exposed photoresist layer by using a developing solution;
etching and removing the third conductive layer and the second conductive layer in the second photoresist removing area;
removing the photoresist layer of the second photoresist semi-reserved area, etching to remove the third conductive layer of the second photoresist semi-reserved area, removing the photoresist layer of the second photoresist complete reserved area, forming the second patterned conductive layer and forming the third conductive member on the second conductive member.
In the method for manufacturing the lamp panel, the light emitting element includes at least one of a sub-millimeter light emitting diode and a micro light emitting diode.
A lamp panel, the lamp panel comprising:
a first patterned conductive layer formed on a substrate, the first patterned conductive layer including a gate and a first conductive member;
a first insulating layer and a patterned semiconductor layer sequentially covering the first patterned conductive layer, wherein via holes corresponding to the first conductive members are formed in the first insulating layer and the patterned semiconductor layer, and the patterned semiconductor layer comprises an active layer corresponding to the gate;
a second patterned conductive layer formed on the patterned semiconductor layer and a third conductive member formed on the second conductive member, wherein the second patterned conductive layer includes the second conductive member, a source/drain electrode and a conductive pad, the second conductive member is electrically connected to the first conductive member through the via hole, and the source/drain electrode is disposed on the active layer;
a second insulating layer covering the first insulating layer, the source/drain electrode, the active layer, and exposing the third conductive member and the conductive pad;
and the light emitting element is bound on the conductive pad through a connector.
In the lamp panel, the third conductive member is made of indium tin oxide, the second patterned conductive layer is made of copper, and the connecting member is made of tin.
In the lamp panel, the first insulating layer is made of at least one of silicon nitride and silicon oxide, and the second insulating layer is made of at least one of silicon nitride and silicon oxide.
In the lamp panel, the light emitting element includes at least one of a sub-millimeter light emitting diode and a micro light emitting diode.
The display device comprises the lamp panel and the display panel, wherein the display panel is located on the light emitting side of the lamp panel.
Has the advantages that: the application provides a lamp panel, a manufacturing method thereof and a display device, wherein a first halftone mask plate is adopted to pattern a first insulating layer and a semiconductor layer, a second halftone mask plate is adopted to pattern a second conducting layer and a third conducting layer so as to reduce the number of used photomasks, and a third conducting member is formed on the second conducting member so as to avoid oxidation of the second conducting member and avoid the problem of electrical connection failure of the second conducting member, the third conducting member and the first conducting member.
Drawings
FIG. 1 is a first schematic view of a conventional backlight module;
FIG. 2 is a second schematic view of a conventional backlight module;
FIG. 3 is a schematic flow chart of a method for manufacturing a lamp panel according to the present application;
fig. 4A-4H are schematic diagrams illustrating a process of manufacturing the lamp panel according to the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Please refer to fig. 1, which is a first schematic diagram of a conventional backlight module. The backlight module includes a substrate 100, a first patterned conductive layer 101, a first insulating layer 102, a patterned semiconductor layer 103, a second patterned conductive layer 104, a second insulating layer 105, and an ito layer 106.
The first patterned conductive layer 101 is formed on the substrate 100, and the first patterned conductive layer 101 includes a gate 1011 and a first conductive member 1012. The first insulating layer 102 covers the first patterned conductive layer 101 and the substrate 100. The patterned semiconductor layer 103 is formed on the first insulating layer 102, the first via 100a disposed corresponding to the first conductive member 1012 is disposed on the patterned semiconductor layer 103 and the first insulating layer 102, and the patterned semiconductor layer 103 includes an active layer 1031 disposed corresponding to the gate electrode 1011. The second patterned conductive layer 104 is formed on the patterned semiconductor layer 103, the second patterned conductive layer 104 includes a second conductive member 1041, a source/drain electrode (1042, 1043) and a conductive pad 1044, the second conductive member 1041 is connected to the first conductive member 1012 through the first via 100a, and the source/drain electrode (1042, 1043) is disposed on the active layer 1031. The second insulating layer 105 covers the first insulating layer 102, the source and drain electrodes (1042, 1043), and the active layer 1031. A second via 100b is disposed on the second insulating layer 105 corresponding to the second conductive member 1041 and exposes the conductive pad 1044. The ito layer 106 is disposed on the second insulating layer 105 and electrically connected to the second conductive member 1041 through the second via 100 b.
The conventional backlight module shown in fig. 1 is prepared by using 5 photomasks, and the ito layer 106 has a large self-resistance and is easy to age, and the ito layer 106 is connected to the second conductive member 1041 through the second via hole 100b, which is likely to cause electrical connection failure, resulting in a lamp failure in the lighting process of the light emitting element bound on the conductive pad 1044, and thus seriously affecting the yield.
Please refer to fig. 2, which is a second schematic diagram of a conventional backlight module. The backlight module includes a substrate 200, a first patterned conductive layer 201, a first insulating layer 202, a patterned semiconductor layer 203, a second patterned conductive layer 204, a second insulating layer 205, and an ito layer 206.
The first patterned conductive layer 201 is formed on the substrate 200, and the first patterned conductive layer 201 includes a gate 2011 and a first conductive member 2012. The first insulating layer 202 covers the first patterned conductive layer 201 and the substrate 200. The patterned semiconductor layer 203 is formed on the first insulating layer 202, and the patterned semiconductor layer 203 includes an active layer 2031 disposed corresponding to the gate electrode 2011. The second patterned conductive layer 204 is formed on the patterned semiconductor layer 203, the second patterned conductive layer 204 includes a second conductive member 2041, source and drain electrodes (2042, 2043) and a conductive pad 2044, and the source and drain electrodes (2042, 2043) are disposed on the active layer 2031. The second insulating layer 205 covers the second patterned conductive layer 204, the first insulating layer 202, and the active layer 2031 and exposes the conductive pad 2044. An ito layer 206 is formed on the second insulating layer 205. The ito layer 206 is connected to the second conductive member 2041 through a first via hole 206a in the second insulating layer 205, and is connected to the first conductive member 2012 through a second via hole 206b in communication with the first insulating layer 202 and the second insulating layer 205.
The backlight module shown in fig. 2 is prepared by using 4 photomasks, and since the ito layer 206 has a relatively large resistance and is easily aged, the ito layer 206 bridges the first conductive member 2012 and the second conductive member 2041, which is easily failed, resulting in a dead light condition occurring during the lighting process of the light emitting element bound on the conductive pad 2044, which seriously affects the yield.
Please refer to fig. 3, which is a flowchart illustrating a method for manufacturing a lamp panel according to the present application. The manufacturing method of the lamp panel comprises the following steps:
s100: the method comprises the steps of forming a first patterned conductive layer on a substrate, wherein the first patterned conductive layer comprises a grid electrode arranged in a first area and a first conductive member arranged in a second area, and the substrate is provided with the first area, the second area and a third area which are mutually spaced.
Specifically, a substrate 300 is provided, a first conductive layer is formed over the substrate 300, a photoresist layer is formed over the first conductive layer, the photoresist layer is exposed by a first mask, and the first conductive layer is developed and etched by a developer, so that a gate 3011 is formed in the first region 300a, and a first conductive member 3012 is formed in the second region 300b, as shown in fig. 4A. The first region 300a is located between the second region 300b and the third region 300c, with a space between the first region 300a and the second region 300b, and a space between the first region 300a and the third region 300 c. The first conductive layer is made of a material including at least one of molybdenum, aluminum, titanium, and copper.
S101: and sequentially forming a first insulating layer and a semiconductor layer which cover the first patterned conductive layer and the substrate, patterning the first insulating layer and the semiconductor layer by adopting a first halftone mask plate, forming via holes which are arranged corresponding to the first conductive members on the first insulating layer and the semiconductor layer and forming the patterned semiconductor layer, wherein the patterned semiconductor layer comprises an active layer which is arranged corresponding to the grid electrode.
First, a first insulating layer 302 covering the first patterned conductive layer and the substrate is formed by chemical vapor deposition. The first insulating layer 302 is at least one of a silicon nitride layer and a silicon oxide layer.
Next, a semiconductor layer is formed over the first insulating layer 302, the semiconductor layer including a first semiconductor layer 3031 and a second semiconductor layer 3032 sequentially stacked over the first insulating layer 302, the first semiconductor layer 3031 being an amorphous silicon (α -Si) layer, and the second semiconductor layer 3032 being an N-doped amorphous silicon (N + α -Si) layer.
Then, a first photoresist layer 304 is formed on the second semiconductor layer 3032, and the first photoresist layer 304 is exposed by using a first halftone mask to define a first photoresist removing region, a first photoresist semi-reserving region and a first photoresist fully-reserving region, wherein the first photoresist removing region corresponds to the first conductive component 3012, a region between the first region 300a and the second region 300b, a region between the first region 300a and the third region 300c corresponds to the first photoresist semi-reserving region, and a partial region of the first region 300a and the second region 300b, and the third region 300c corresponds to the first photoresist fully-reserving region.
Next, the exposed first photoresist layer 304 is developed with a developing solution to remove the first photoresist layer in the first photoresist removing region, as shown in fig. 4B. After the developing solution develops the first photoresist layer 304, the thickness of the first photoresist layer in the first photoresist semi-reserved area is smaller than that in the first photoresist full-reserved area.
Removing the semiconductor layers (3031, 3032) and the first insulating layer 302 of the first photoresist removal region by dry etching to form a via hole 300d; removing the first photoresist layer in the first photoresist semi-reserved region, removing the semiconductor layer in the first photoresist semi-reserved region by dry etching, and removing the first photoresist layer in the first photoresist complete reserved region to form a patterned semiconductor layer, as shown in fig. 4C, the patterned semiconductor layer includes an active layer 30311, and the active layer 30311 is the first semiconductor layer 3031 located in the first region 300 a.
S102: forming a second conductive layer in the via hole, on the first insulating layer and on the patterned semiconductor layer, forming a third conductive layer on the second conductive layer, patterning the second conductive layer and the third conductive layer by using a second halftone mask, forming a second patterned conductive layer and forming a third conductive member on the second conductive member.
First, a second conductive layer 305 is formed in the via hole 300d, on the first insulating layer 302 and on the patterned semiconductor layer by sputtering deposition, wherein the second conductive layer 305 includes a copper layer; a third conductive layer 306 is formed on the second conductive layer 305 by sputtering deposition, and the third conductive layer 306 is an ito layer.
Then, a second photoresist layer 307 is formed on the third conductive layer 306, and the second photoresist layer 307 is exposed by using a second halftone mask to define a second photoresist removing region, a second photoresist half-retaining region and a second photoresist complete-retaining region; the area between the first area 300a and the second area 300b, the area between the first area 300a and the third area 300c, and a part of the area of the first area 300a correspond to the second photoresist removing area, the part of the area 300a and the third area 300c correspond to the second photoresist half-retaining area, the second area 300b corresponds to the second photoresist full-retaining area, the exposed second photoresist layer is developed by using a developing solution, the second photoresist layer of the second photoresist removing area is completely removed, and the thickness of the second photoresist layer of the second photoresist half-retaining area is smaller than that of the second photoresist full-retaining area, as shown in fig. 4D.
Removing the third conductive layer 306 and the second conductive layer 305 in the second photoresist removal region by wet etching, as shown in fig. 4E; the second semiconductor layer 3032 is further dry-etched in a partial region of the first region 300a, so that the active layer 30311 forms a channel, as shown in fig. 4F; removing the second photoresist layer in the second photoresist semi-reserved area, and removing the third conductive layer 306 in the second photoresist semi-reserved area by wet etching, as shown in fig. 4G; the photoresist layer of the second photoresist complete remaining region is removed, a second patterned conductive layer is formed, and a third conductive member 3061 is formed on the second conductive member 3051, the second patterned conductive layer includes a second conductive member 3051 formed in the second region 300b, source and drain electrodes (3052, 3053) formed in the first region 300a, and a conductive pad 3054 formed in the third region 300c, the second conductive member 3051 is electrically connected to the first conductive member 3012 through the via 300d, and the source and drain electrodes (3052, 3053) are disposed on the active layer 30311.
S103: and forming a second insulating layer which covers the first insulating layer, the source-drain electrode and the active layer and exposes the third conductive member and the conductive pad.
Specifically, the second insulating layer 308 covering the first insulating layer 302, the third conductive member 3061, the source/drain electrodes (3052, 3053), and the conductive pad 3054 is formed by chemical sputtering deposition, a photoresist layer is formed on the second insulating layer 308, the photoresist layer is exposed to light using a second mask and developed by a developing solution, and the second insulating layer 308 in the second region 300b and the third region 300c is dry-etched to expose the third conductive member 3061 and the conductive pad 3054.
S104: and binding the light-emitting element on the conductive pad through the connecting piece to obtain the lamp panel.
Specifically, the connection member 310 is made of a material including tin, the light emitting element 309 is a sub-millimeter light emitting diode, and the light emitting element 309 is bound to the conductive pad 3054 using a tin paste, which has a good adhesion to copper since the conductive pad 3054 is made of copper, so that the light emitting element 309 can be firmly fixed to the conductive pad 3054, as shown in fig. 4H. Since the third conductive member 3061 is formed on the second conductive member 3051, the failure of the electrical connection between the third conductive member 3061 and the second conductive member 3051 can be avoided, and the electrical connection between the second conductive member 3051 and the first conductive member 3012 through the via 300d can be ensured to be good.
In this step, a flip chip film (not shown) is also bonded to the third conductive member 3061.
The lamp panel is prepared by adopting a first photomask, a second photomask, a first halftone mask plate and a second halftone mask plate, and the method for preparing the lamp panel by using the 4-photomask (mask) is provided. The first conductive member, the second conductive member and the third conductive member are not electrically connected to fail while the light emitting element is firmly fixed on the conductive pad, so that the light emitting element can normally emit light.
The application further provides a display device, which comprises a lamp panel and a display panel, wherein the display panel is located on the light emitting side of the lamp panel, and the display panel is a liquid crystal display panel. The lamp plate includes:
a first patterned conductive layer formed on the substrate, the first patterned conductive layer including a gate and a first conductive member;
the first insulating layer and the patterned semiconductor layer sequentially cover the first patterned conductive layer, through holes arranged corresponding to the first conductive members are formed in the first insulating layer and the patterned semiconductor layer, and the patterned semiconductor layer comprises an active layer arranged corresponding to the grid electrode;
a second patterned conductive layer formed on the patterned semiconductor layer and a third conductive member formed on the second conductive member, the second patterned conductive layer including a second conductive member, a source/drain electrode and a conductive pad, the second conductive member being electrically connected to the first conductive member through the via hole, the source/drain electrode being disposed on the active layer;
a second insulating layer covering the first insulating layer, the source/drain electrode, and the active layer and exposing the third conductive member and the conductive pad;
and a light emitting element bound to the conductive pad through a connector.
In this embodiment, the third conductive member is made of indium tin oxide, the second patterned conductive layer is made of copper, and the connecting member is made of tin.
In this embodiment, the first insulating layer is made of at least one material selected from silicon nitride and silicon oxide, and the second insulating layer is made of at least one material selected from silicon nitride and silicon oxide.
In this embodiment, the light emitting element includes at least one of a sub-millimeter light emitting diode and a micro light emitting diode.
The third conductive member of this application display device's lamp plate forms and can avoid the oxidation of second conductive member on the second conductive member, avoids the problem that second conductive member, third conductive member and first conductive member electric connection became invalid, guarantees that light emitting component can be normal luminous for the lamp plate can send even light.
The above description of the embodiments is only for assisting understanding of the technical solutions and the core ideas thereof; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.
Claims (10)
1. A method for manufacturing a lamp panel is characterized by comprising the following steps:
forming a first patterned conductive layer on a substrate, wherein the first patterned conductive layer comprises a grid arranged in a first area and a first conductive member arranged in a second area, and the substrate is provided with the first area, the second area and a third area which are mutually spaced;
sequentially forming a first insulating layer and a semiconductor layer which cover the first patterned conductive layer and the substrate, patterning the first insulating layer and the semiconductor layer by adopting a first halftone mask plate, forming via holes which are arranged corresponding to the first conductive members on the first insulating layer and the semiconductor layer and forming a patterned semiconductor layer, wherein the patterned semiconductor layer comprises an active layer which is arranged corresponding to the grid electrode;
forming a second conductive layer in the via hole, on the first insulating layer and on the patterned semiconductor layer, forming a third conductive layer on the second conductive layer, patterning the second conductive layer and the third conductive layer by using a second halftone mask to form a second patterned conductive layer and a third conductive member on the second conductive member, wherein the second patterned conductive layer includes the second conductive member formed in the second region, a source/drain electrode formed in the first region, and a conductive pad formed in the third region, the second conductive member is electrically connected to the first conductive member through the via hole, and the source/drain electrode is disposed on the active layer;
forming a second insulating layer which covers the first insulating layer, the source-drain electrode and the active layer and exposes the third conductive member and the conductive pad;
and binding the light-emitting element on the conductive pad through a connecting piece to obtain the lamp panel.
2. The method for manufacturing the lamp panel according to claim 1, wherein the third conductive member is made of indium tin oxide, the second patterned conductive layer is made of copper, and the connecting member is made of tin.
3. The method for manufacturing the lamp panel according to claim 1, wherein the patterning the first insulating layer and the semiconductor layer by using a first halftone mask comprises:
forming a light resistance layer on the semiconductor layer, and exposing the light resistance layer by using a first halftone mask plate to define a first light resistance removing area, a first light resistance semi-reserving area and a first light resistance complete-reserving area; the first photoresist removing area corresponds to the first conductive member, an area between the first area and the second area, an area between the first area and the third area correspond to the first photoresist semi-reserved area, and a partial area of the first area, the second area and the third area correspond to the first photoresist complete-reserved area; developing the exposed photoresist layer by using a developing solution;
etching and removing the semiconductor layer and the first insulating layer in the first photoresist removing area to form the via hole;
and removing the light resistance layer of the first light resistance semi-reserved area, etching to remove the semiconductor layer of the first light resistance semi-reserved area, and removing the light resistance layer of the first light resistance complete reserved area to form the patterned semiconductor layer.
4. The method for manufacturing a lamp panel according to claim 3, wherein the step of patterning the second conductive layer and the third conductive layer by using a second halftone mask comprises the steps of:
forming a photoresist layer on the third conductive layer, and exposing the photoresist layer by using a second half-tone mask plate to define a second photoresist removing area, a second photoresist semi-reserving area and a second photoresist complete-reserving area; the regions between the first region and the second region, between the first region and the third region, and a part of the first region correspond to the second photoresist removal region, the part of the first region and the third region correspond to the second photoresist semi-reserved region, and the second region corresponds to the second photoresist complete-reserved region; developing the exposed photoresist layer by using a developing solution;
etching and removing the third conductive layer and the second conductive layer in the second photoresist removing area;
removing the photoresist layer of the second photoresist semi-reserved area, etching to remove the third conductive layer of the second photoresist semi-reserved area, removing the photoresist layer of the second photoresist complete reserved area, forming the second patterned conductive layer and forming the third conductive member on the second conductive member.
5. The method for manufacturing a lamp panel according to claim 1, wherein the light emitting element includes at least one of a sub-millimeter light emitting diode and a micro light emitting diode.
6. A lamp panel manufactured by the method of any one of claims 1 to 5, the lamp panel comprising:
a first patterned conductive layer formed on a substrate, the first patterned conductive layer including a gate and a first conductive member;
a first insulating layer and a patterned semiconductor layer sequentially covering the first patterned conductive layer, wherein via holes corresponding to the first conductive members are formed in the first insulating layer and the patterned semiconductor layer, and the patterned semiconductor layer comprises an active layer corresponding to the gate;
a second patterned conductive layer formed on the patterned semiconductor layer and a third conductive member formed on the second conductive member, wherein the second patterned conductive layer includes the second conductive member, a source/drain electrode and a conductive pad, the second conductive member is electrically connected to the first conductive member through the via hole, and the source/drain electrode is disposed on the active layer;
a second insulating layer covering the first insulating layer, the source/drain electrode, the active layer, and exposing the third conductive member and the conductive pad;
and a light emitting element bound to the conductive pad through a connector.
7. The lamp panel of claim 6, wherein the third conductive member is made of indium tin oxide, the second patterned conductive layer is made of copper, and the connector is made of tin.
8. The lamp panel of claim 6, wherein the first insulating layer is made of at least one material selected from silicon nitride and silicon oxide, and the second insulating layer is made of at least one material selected from silicon nitride and silicon oxide.
9. The light panel of claim 6, wherein the light emitting elements comprise at least one of sub-millimeter light emitting diodes and micro light emitting diodes.
10. A display device, characterized in that the display device comprises the lamp panel according to any one of claims 6 to 9 and a display panel, and the display panel is located on the light-emitting side of the lamp panel.
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| US20050112790A1 (en) * | 2003-11-26 | 2005-05-26 | Chih-Chieh Lan | Method of manufacturing liquid crystal display |
| US20090047749A1 (en) * | 2007-08-13 | 2009-02-19 | Au Optronics Corp. | Methods of manufacturing thin film transistor and display device |
| CN102566179A (en) * | 2010-11-26 | 2012-07-11 | 乐金显示有限公司 | Method for fabricating liquid crystal display device |
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