CN111584512B - Array substrate, manufacturing method thereof and display device - Google Patents
Array substrate, manufacturing method thereof and display device Download PDFInfo
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- CN111584512B CN111584512B CN202010407095.4A CN202010407095A CN111584512B CN 111584512 B CN111584512 B CN 111584512B CN 202010407095 A CN202010407095 A CN 202010407095A CN 111584512 B CN111584512 B CN 111584512B
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- 239000000758 substrate Substances 0.000 title claims abstract description 87
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 35
- 239000004065 semiconductor Substances 0.000 claims abstract description 35
- 238000000034 method Methods 0.000 claims abstract description 17
- 238000000059 patterning Methods 0.000 claims abstract description 16
- 230000008569 process Effects 0.000 claims abstract description 10
- 229920002120 photoresistant polymer Polymers 0.000 claims description 55
- 239000000463 material Substances 0.000 claims description 19
- 229910045601 alloy Inorganic materials 0.000 claims description 18
- 239000000956 alloy Substances 0.000 claims description 18
- 230000000149 penetrating effect Effects 0.000 claims description 13
- 229910001182 Mo alloy Inorganic materials 0.000 claims description 6
- 229910052750 molybdenum Inorganic materials 0.000 claims description 6
- 229910021417 amorphous silicon Inorganic materials 0.000 description 24
- 238000002360 preparation method Methods 0.000 description 11
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 238000007796 conventional method Methods 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 6
- 239000010949 copper Substances 0.000 description 6
- 239000010408 film Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 4
- 238000002161 passivation Methods 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000005260 corrosion Methods 0.000 description 3
- 230000007797 corrosion Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 239000000969 carrier Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- 239000011733 molybdenum Substances 0.000 description 1
- 238000009877 rendering Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000000638 stimulation Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
- G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Theoretical Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
The application provides an array substrate, a manufacturing method thereof and a display device, wherein the manufacturing method comprises the following steps: forming a first patterned conductive layer on a substrate, wherein the first patterned conductive layer comprises a grid electrode; forming an insulating layer covering the first patterned conductive layer and the substrate; forming a semiconductor layer on one side of the insulating layer away from the substrate; forming a second conductive layer on the whole surface of the semiconductor layer, which is far away from the substrate, and patterning the semiconductor layer and the second conductive layer by adopting a patterning process to obtain an active layer, a source-drain electrode, a first conductive electrode and a first conductive member, wherein the active layer is arranged corresponding to the grid electrode, and the source-drain electrode is electrically connected with the active layer; and forming a patterned shading insulating layer which covers the source and drain electrodes, the active layer and the insulating layer and exposes the first conductive electrode and the first conductive member to obtain the array substrate. Compared with the prior art, the light shielding layer is formed, the manufacturing process is simplified, and the number of the light shields is reduced.
Description
Technical Field
The application relates to the technical field of display, in particular to an array substrate, a manufacturing method thereof and a display device.
Background
As a product of combining a miniaturized light-emitting diode (Mini-LED) with a backboard, the submillimeter light-emitting diode (Mini-LED) backboard has the characteristics of high contrast, high color rendering performance and the like which are comparable with those of an organic light-emitting diode, the cost is only about 60 percent of that of the organic light-emitting diode, and the submillimeter light-emitting diode backboard is easier to implement than the organic light-emitting diode, so that the submillimeter light-emitting diode backboard becomes a current research hot spot.
However, the conventional fabrication process of the sub-millimeter led back plate has the problems of complex process and more masks.
Disclosure of Invention
The invention provides an array substrate, a manufacturing method thereof and a display device, which are used for simplifying the manufacturing process of the array substrate and reducing the number of photomasks used in the manufacturing process of the array substrate.
In order to achieve the above object, the present application provides a method for manufacturing an array substrate, the method comprising the steps of:
forming a first patterned conductive layer on a substrate, wherein the first patterned conductive layer comprises a grid electrode;
forming an insulating layer covering the first patterned conductive layer and the substrate;
forming a semiconductor layer on the whole surface of one side of the insulating layer far away from the substrate;
forming a second conductive layer on the whole surface of one side, far away from the substrate, of the semiconductor layer, and patterning the semiconductor layer and the second conductive layer by adopting a patterning process to obtain an active layer, a source-drain electrode, a first conductive electrode and a first conductive member, wherein the active layer is arranged corresponding to the grid electrode, and the source-drain electrode is arranged corresponding to the active layer and is electrically connected with the active layer;
and forming a patterned shading insulating layer which covers the source electrode, the drain electrode, the active layer and the insulating layer and exposes the first conductive electrode and the first conductive member, so as to obtain the array substrate.
In the above array substrate, the first patterned conductive layer further includes a second conductive electrode and a second conductive member, the first conductive electrode is disposed corresponding to the second conductive electrode, and the first conductive member is disposed corresponding to the second conductive member, and the manufacturing method further includes the following steps:
and forming a first contact hole and a second contact hole penetrating through the insulating layer and the semiconductor layer, wherein the first contact hole is arranged corresponding to the second conductive electrode, the second contact hole is arranged corresponding to the second conductive member, the first conductive electrode and the second conductive electrode are electrically connected through the first contact hole, and the first conductive member and the second conductive member are electrically connected through the second contact hole.
In the above array substrate, the preparation material of the patterned light-shielding insulating layer is at least one selected from black organic photoresist or ink.
In the above array substrate, the preparation material of the first patterned conductive layer includes Mo or Mo alloy, and the preparation material of the second conductive layer includes Mo or Mo alloy.
In the above array substrate, the preparation material of the first patterned conductive layer includes a MoTiNi alloy, and the preparation material of the second conductive layer includes a MoTiNi alloy.
An array substrate, the array substrate comprising:
a substrate;
a first patterned conductive layer formed on the substrate, the first patterned conductive layer including a gate electrode;
an insulating layer covering the first patterned conductive layer and the substrate;
a patterned semiconductor layer formed on a side of the insulating layer away from the substrate, the patterned semiconductor layer including an active layer;
the second patterned conductive layer is formed on one side of the patterned semiconductor layer far away from the substrate, and comprises a first conductive member, a source electrode, a drain electrode and a first conductive electrode, wherein the source electrode and the drain electrode are arranged corresponding to the active layer and are electrically connected with the active layer; and
and a patterned light shielding insulating layer covering the source and drain electrodes, the insulating layer, and the active layer and exposing the first conductive electrode and the first conductive member.
In the above array substrate, the first patterned conductive layer further includes a second conductive electrode and a second conductive member, the first conductive electrode is disposed corresponding to the second conductive electrode, the first conductive member is disposed corresponding to the second conductive member, the first conductive electrode and the second conductive electrode are electrically connected through a first contact hole penetrating through the patterned semiconductor layer and the insulating layer, and the first conductive member and the second conductive member are electrically connected through a second contact hole penetrating through the patterned semiconductor layer and the insulating layer.
In the above array substrate, the preparation material of the patterned light-shielding insulating layer is at least one selected from black organic photoresist or ink.
In the above array substrate, the preparation material of the first patterned conductive layer includes a MoTiNi alloy, and the preparation material of the second patterned conductive layer includes a MoTiNi alloy.
A display device comprises a backlight module, wherein the backlight module comprises the array substrate.
The beneficial effects are that: the application provides an array substrate, a manufacturing method thereof and a display device, wherein the manufacturing method comprises the following steps: forming a first patterned conductive layer on a substrate, wherein the first patterned conductive layer comprises a grid electrode; forming an insulating layer covering the first patterned conductive layer and the substrate; forming a semiconductor layer on one side of the insulating layer away from the substrate; forming a second conductive layer on the whole surface of the semiconductor layer, which is far away from the substrate, and patterning the semiconductor layer and the second conductive layer by adopting a patterning process to obtain an active layer, a source-drain electrode, a first conductive electrode and a first conductive member, wherein the active layer is arranged corresponding to the grid electrode, and the source-drain electrode is electrically connected with the active layer; and forming a patterned shading insulating layer which covers the source and drain electrodes, the active layer and the insulating layer and exposes part of the first conductive electrode and the first conductive member to obtain the array substrate. Compared with the prior art, the patterning shading insulating layer which covers the source and drain electrodes, the active layer and the insulating layer and exposes the first conductive electrode and the first conductive member is formed, the shading layer is formed to avoid the generation of photo-generated current by the active layer, meanwhile, the passivation layer, the indium tin oxide and other conductive layers are not required to be formed, the photomask is not required to be increased to pattern the passivation layer and the indium tin oxide layer, the manufacturing process is simplified, and the use number of the photomask is reduced.
Drawings
FIG. 1 is a schematic diagram of a conventional method for manufacturing a backlight module without a light shielding layer;
FIG. 2 is a schematic diagram of a conventional method for manufacturing a backlight module including a light shielding layer;
FIG. 3 is a schematic flow chart of a method for manufacturing an array substrate according to an embodiment of the present disclosure;
fig. 4 is a schematic diagram of a process for manufacturing an array substrate according to the flow chart shown in fig. 3.
The drawings are as follows:
1011 2011 a second conductive member; 1012 2012 gate; 102 a first insulating layer; 1031 2031 an amorphous silicon layer; 1032 A 2032 n-type doped amorphous silicon layer; 100a first via; 104 A second conductive layer 204; 1041 a first conductive electrode; 1042 a first conductive member; 1043 2043 source-drain electrodes; 100b second vias; 100c a third via; 105 a second insulating layer; 106 conductive blocks; 107 a third insulating layer; 108 a light shielding layer; 2013 a second conductive electrode; 202 an insulating layer; 200a first contact holes; 200b second contact holes; 205 patterning the light shielding insulating layer.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
Fig. 1 is a schematic diagram of a conventional method for manufacturing a backlight module without a light shielding layer. The conventional method for manufacturing the backlight module without the shading layer comprises the following steps:
s101, forming a grid 1012 and a second conductive member 1011 which are arranged on the same layer on the substrate.
Specifically, a first conductive layer is formed over the substrate, a photoresist layer is formed over the first conductive layer, the photoresist layer is exposed using a first mask, and the photoresist layer is developed using a developer, the first conductive layer not covered by the photoresist layer is etched, and the remaining photoresist layer is removed to obtain a gate electrode 1012 and a second conductive member 1011, as shown in fig. 1 (A1).
S102, forming a first insulating layer covering the grid electrode, the second conductive member and the substrate, forming a semiconductor layer on one side of the first insulating layer far away from the substrate, forming a first via hole penetrating the first insulating layer and the semiconductor layer and arranged corresponding to the second conductive member, and forming a second conductive layer in the first via hole and on the semiconductor layer.
Specifically, a first insulating layer 102 covering the gate electrode 1012, the second conductive member 1011, and the substrate is formed using chemical vapor deposition. The first insulating layer 102 is a gate insulating layer. An amorphous silicon layer 1031 is then formed overlying the first insulating layer 102, and an n-doped amorphous silicon layer 1032 is formed.
A photoresist layer is formed over the n-type doped amorphous silicon layer 1032, the photoresist layer is exposed by a second photomask, and after developing treatment with a developing solution, the n-type doped amorphous silicon layer 1032, the amorphous silicon layer 1031 and the first insulating layer 102 corresponding to the second conductive member 1011 are etched to form a first via hole 100a penetrating the first insulating layer 102, the n-type doped amorphous silicon layer 1032 and the amorphous silicon layer 1031.
An entire second conductive layer 104 is formed in the first via hole 100a and on the n-type doped amorphous silicon layer 1032 by sputtering, as shown in (B1) of fig. 1.
S103: patterning the second conductive layer and the semiconductor layer by using a patterning process to obtain a first conductive member, a source drain electrode, an active layer and a first conductive electrode.
Specifically, a photoresist layer is formed on the second conductive layer 104, and the photoresist layer is exposed by using a halftone gray-scale mask plate to define a photoresist complete removal region, a photoresist half-reserved region and a photoresist complete reserved region. After the photoresist in the photoresist complete removal region is treated by the developing solution, etching to remove the second conductive layer 104, the amorphous silicon layer 1031 and the n-type doped amorphous silicon layer 1032 in the photoresist complete removal region, thereby obtaining a first conductive member 1042 and a first conductive electrode 1041, wherein the first conductive member 1042 is electrically connected with the second conductive member 1011 through the first via hole 100 a; after the photoresist in the photoresist half-reserved area is treated by the developing solution, the n-type doped amorphous silicon layer 1032 and the second conductive layer 104 in the photoresist half-reserved area are etched and removed, so as to obtain a source drain electrode 1043 and an active layer, the source drain electrode 1043 is arranged corresponding to the active layer and is electrically connected with the active layer, and the photoresist layer in the photoresist full-reserved area is removed, as shown in (C1) in fig. 1.
S104: a second insulating layer is formed to cover the first conductive electrode, the first conductive member, the source-drain electrode, the active layer, and the first insulating layer and to have a second via hole and a third via hole.
The second insulating layer 105 covering the first conductive electrode 1041, the first conductive member 1042, the source drain electrode 1043, the active layer and the first insulating layer 102 is formed by chemical vapor deposition, a photoresist layer is formed on the second insulating layer 105 in whole, the photoresist layer is exposed by a fourth photomask and developed by developing solution, the second insulating layer uncovered by the photoresist layer is etched, the remaining photoresist layer is removed, and a second via hole 100b penetrating the second insulating layer 105 and corresponding to the first conductive member 1042 and a third via hole 100c penetrating the second insulating layer 105 and corresponding to the first conductive electrode 1041 are formed. The second insulating layer 105 is a passivation layer, as shown in (D1) of fig. 1.
S105: a conductive block 106 is formed on the second via hole 100b and the second insulating layer 105.
Specifically, a third conductive layer is formed on the second via hole 100b, the third via hole 100c, and the second insulating layer 105, a photoresist layer is formed on the third conductive layer, the photoresist layer is exposed and developed by using a fifth photomask, the third conductive layer is etched, the remaining photoresist layer is removed, the first conductive electrode 1041 is exposed, the conductive block 106 is obtained, the flip chip film (not shown) is bound to the conductive block 106, and the submillimeter light emitting diode (not shown) is bound to the first conductive electrode 1041, as shown in (E1) in fig. 1. The third conductive layer is made of indium tin oxide. The conductive block 106 is connected to the first conductive member 1042 through the second via 100 b.
As can be seen from the above steps, the conventional method needs to use five masks in the process of manufacturing the backlight module without the light shielding layer, which can cause the active layer to easily generate light-generating current under the effect of light, thereby affecting the electrical performance of the thin film transistor of the backlight module.
Fig. 2 is a schematic diagram of a conventional method for manufacturing a backlight module including a light shielding layer. The items (A2) - (E2) in fig. 2 are identical to the items (A1) - (E1) in fig. 1, and are not described in detail here. The difference is that after the conductive block 106 is formed, a third insulating layer 107 is formed to cover the conductive block 106, the second insulating layer 105 and the first conductive electrode 1041, a light shielding layer 108 is formed on the third insulating layer 107, and after the light shielding layer 108 is exposed by a sixth photomask and developed by a developing solution, a portion of the light shielding layer 108 corresponding to the conductive block 106 and the first conductive electrode 1041 is removed, so as to obtain a patterned light shielding layer, as shown in (F2) in fig. 2.
The third insulating layer 107 is etched with the patterned light-shielding layer as an etching barrier layer, and the third insulating layer 107 on the conductive block 106 and the first conductive electrode 1041 is removed, so that the conductive block 106 and the first conductive electrode 1041 are exposed, the flip chip film is bound to the conductive block 106, and the submillimeter light-emitting diode is bound to the first conductive electrode 1041, so as to obtain a backlight module including the light-shielding layer, as shown in (G2) of fig. 2.
As can be seen from the above, the conventional manufacturing process of the backlight module including the light shielding layer requires six masks, the number of masks used is large, and the manufacturing process is complex.
Please refer to fig. 3, which is a flowchart illustrating a manufacturing method of an array substrate according to an embodiment of the present disclosure. The manufacturing method of the array substrate comprises the following steps:
s201, forming a first patterned conductive layer on a substrate, wherein the first patterned conductive layer comprises a grid electrode.
Specifically, a first conductive layer is formed on a glass substrate, a photoresist layer is formed on the first conductive layer, the photoresist layer is exposed by a first photomask and developed by a developing solution, the first conductive layer uncovered by the photoresist layer is etched, and the remaining photoresist layer is removed to obtain a first patterned conductive layer, wherein the first patterned conductive layer includes a gate 2012, a second conductive member 2011 and a second conductive electrode 2013, and the gate 2012 is located between the second conductive member 2011 and the second conductive electrode 2013, as shown in (A3) in fig. 4.
The first patterned conductive layer may be made of at least one of molybdenum (Mo), molybdenum alloy, copper, aluminum, and silver. For example, the first patterned conductive layer may be made of a material including a MoTiNi alloy. Specifically, the first conductive layer comprises a MoTiNi alloy layer, a copper layer and a MoTiNi alloy layer which are sequentially stacked on the substrate, wherein the MoTiNi alloy layer is used for blocking diffusion of the copper layer on one hand, preventing oxidation of the copper layer on the other hand, and improving conductivity.
S202, forming an insulating layer covering the first patterned conductive layer and the substrate.
Specifically, the insulating layer 202 covering the gate 2012, the second conductive member 2011, the second conductive electrode 2013, and the substrate is formed by chemical vapor deposition, as shown in (B3) of fig. 4.
The insulating layer is made of at least one material selected from silicon nitride and silicon oxide. The thickness of the insulating layer is 800-6000 angstroms. Specifically, the insulating layer is a gate insulating layer, the thickness of the gate insulating layer is 1500 angstroms, and the gate insulating layer is a silicon nitride layer.
And S203, forming a semiconductor layer on the whole surface of the insulating layer at the side far away from the substrate.
Specifically, an entire amorphous silicon layer 2031 and an n-type doped amorphous silicon layer 2032 are sequentially formed on the side of the insulating layer 202 away from the substrate. A photoresist layer is formed on the n-doped amorphous silicon layer 2032, the photoresist layer is exposed by a second photomask and developed by a developing solution, a part of the amorphous silicon layer 2031, the n-doped amorphous silicon layer 2032 and the insulating layer 202 corresponding to the second conductive electrode 2013 and the second conductive member 2011 are etched, the remaining photoresist is removed, and a first contact hole 200a and a second contact hole 200b penetrating the insulating layer 202 and the semiconductor layers (2031, 2032) are formed, the first contact hole 200a is arranged corresponding to the second conductive electrode 2013, and the second contact hole 200b is arranged corresponding to the second conductive member 2011.
And S204, forming a second conductive layer on the whole surface of one side of the semiconductor layer, which is far away from the substrate, and patterning the semiconductor layer and the second conductive layer by adopting a patterning process to obtain an active layer, a source-drain electrode, a first conductive electrode and a first conductive component, wherein the active layer is arranged corresponding to the grid electrode, and the source-drain electrode is arranged corresponding to the active layer and is electrically connected with the active layer.
Specifically, an entire second conductive layer 204 is formed in the first contact hole 200a, in the second contact hole 200B, and on the n-type doped amorphous silicon layer 2032, as shown in (B3) of fig. 4.
Forming a photoresist layer on the second conductive layer 204, exposing the photoresist layer with a halftone gray-scale mask to define a photoresist half-reserved region, a photoresist full-reserved region and a photoresist full-removed region, developing the exposed photoresist layer with a developing solution to remove the photoresist layer in the photoresist full-removed region, etching the second conductive layer 204, the amorphous silicon layer 2031 and the n-type doped amorphous silicon layer 2032 in the photoresist full-removed region to obtain a first conductive electrode 2041 and a first conductive member 2042, wherein the first conductive electrode 2041 is disposed corresponding to the second conductive electrode 2013, the first conductive member 2042 is disposed corresponding to the second conductive member 2011, the first conductive electrode 2041 is electrically connected with the second conductive electrode 2013 through the first contact hole 200a, and the first conductive member 2042 is electrically connected with the second conductive member 2011 through the second contact hole 200 b. The photoresist layer of the photoresist half-reserved area is removed, the second conductive layer 204 and the n-type doped amorphous silicon layer 2032 of the photoresist half-reserved area are etched to obtain an active layer and a source drain electrode 2043, the photoresist layer of the photoresist full-reserved area is removed, and the source drain electrode 2043, the first conductive electrode 2041 and the first conductive member 2042 are exposed, as shown in (C3) of fig. 4.
In this embodiment, the second conductive layer is made of Mo or Mo alloy. For example, the second conductive layer includes a MoTiNi alloy layer, a copper layer, and a MoTiNi alloy layer sequentially stacked on the n-type doped amorphous silicon layer 2032. The MoTiNi alloy layer has good oxidation resistance and corrosion resistance, and plays a role in preventing the oxidation of the copper layer.
And S205, forming a patterned shading insulating layer which covers the source and drain electrodes, the active layer and the insulating layer and exposes the first conductive electrode and the first conductive member to obtain the array substrate.
Specifically, a coating process or the like is used to form a whole light-shielding insulating layer covering the source/drain electrode 2043, the active layer, the insulating layer 202, the first conductive electrode 2041, and the first conductive member 2042, and a fourth photomask is used to expose the whole light-shielding insulating layer, and a developer is used to develop the light-shielding insulating layer, so as to obtain a patterned light-shielding insulating layer 205, as shown in (D3) of fig. 4.
In this embodiment, the patterned light shielding insulating layer 205 is made of a black organic photoresist. When the patterned light-shielding insulating layer 205 is made of a black organic photoresist, the thickness of the patterned light-shielding insulating layer 205 is 1 micron to 2 microns, for example, 1.5 microns, 1.2 microns, and 1.8 microns. In other embodiments, the material of which the patterned light shielding insulating layer 205 is made may also include an ink, such as a white ink. The patterned light shielding insulating layer 205 plays a role in shielding light from the active layer and also plays a role in protecting the second patterned conductive layer.
When the array substrate is applied to the backlight module, the submillimeter light emitting diode is bound on the first conductive electrode 2041, and the flip chip film is bound on the first conductive member 2042.
Compared with the prior art, the manufacturing method of the array substrate has the advantages that the patterning shading insulating layer which covers the source electrode, the drain electrode, the active layer and the insulating layer and exposes the first conductive electrode and the first conductive component is directly formed, so that the manufacturing and patterning of the passivation layer and the indium tin oxide layer are omitted, the manufacturing process of the array substrate is simplified, one to two photomasks are saved, and four photomasks are used in the whole manufacturing process of the array substrate. And the patterned shading insulating layer prevents the active layer from generating photo-generated carriers, thereby improving the off-state current characteristic of the thin film transistor.
The application also provides a backlight module, the backlight module includes array substrate, and array substrate includes:
a substrate;
a first patterned conductive layer formed on the substrate, the first patterned conductive layer including a gate;
an insulating layer covering the first patterned conductive layer and the substrate;
the patterned semiconductor layer is formed on one side of the insulating layer far away from the substrate and comprises an active layer;
the second patterned conductive layer comprises a first conductive member, a source electrode, a drain electrode and a first conductive electrode, wherein the active layer is arranged corresponding to the grid electrode, and the source electrode and the drain electrode are arranged corresponding to the active layer and are electrically connected with the active layer; and
and a patterned light shielding insulating layer covering the source/drain electrode, the insulating layer and the active layer and exposing the first conductive electrode and the first conductive member.
In this embodiment, the first patterned conductive layer further includes a second conductive electrode and a second conductive member, the first conductive electrode is disposed corresponding to the second conductive electrode, the first conductive member is disposed corresponding to the second conductive member, the first conductive electrode and the second conductive electrode are electrically connected through a first contact hole penetrating through the patterned semiconductor layer and the insulating layer, and the first conductive member and the second conductive member are electrically connected through a second contact hole penetrating through the patterned semiconductor layer and the insulating layer. The first conductive electrode is electrically connected with the second conductive electrode, so that the conductivity of the first conductive electrode is improved. The first conductive member is connected with the second conductive member, and the conductivity of the first conductive member is improved.
In this embodiment, the preparation material of the patterned light-shielding insulating layer is selected from at least one of a black organic photoresist or an ink. The patterned shading insulating layer plays a role in shading on one hand, and can prevent the active layer from generating photo-generated carriers under the stimulation of light, and on the other hand, plays a role in protecting the film layer covered by the patterned shading insulating layer.
In this embodiment, the preparation material of the first patterned conductive layer includes a MoTiNi alloy, and the preparation material of the second patterned conductive layer includes a MoTiNi alloy. The MoTiNi alloy has good oxidation resistance and corrosion resistance, and improves the oxidation resistance and corrosion resistance of the first patterned conductive layer and the second patterned conductive layer.
In this embodiment, the backlight module further includes a submillimeter light emitting diode and a flip chip film, the submillimeter light emitting diode is bound on the first conductive electrode 2041, and the flip chip film is bound on the first conductive member 2042.
In this embodiment, the active layer is made of amorphous silicon or metal oxide.
In this embodiment, the insulating layer is made of at least one material selected from silicon nitride and silicon oxide.
The application also provides a display device, which comprises the backlight module.
The above description of the embodiments is only for helping to understand the technical solution of the present application and its core ideas; those of ordinary skill in the art will appreciate that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.
Claims (10)
1. A method for manufacturing an array substrate, the method comprising the steps of:
forming a first patterned conductive layer on a substrate, wherein the first patterned conductive layer comprises a grid electrode;
forming an insulating layer covering the first patterned conductive layer and the substrate;
forming a semiconductor layer on the whole surface of one side of the insulating layer far away from the substrate;
forming a second conductive layer on the whole surface of one side, far away from the substrate, of the semiconductor layer, and patterning the semiconductor layer and the second conductive layer by adopting a patterning process to obtain an active layer, a source-drain electrode, a first conductive electrode and a first conductive member, wherein the active layer is arranged corresponding to the grid electrode, and the source-drain electrode is arranged corresponding to the active layer and is electrically connected with the active layer;
and forming a patterned shading insulating layer which covers the source and drain electrodes, the active layer and the insulating layer and exposes the first conductive electrode and the first conductive member, wherein the patterned shading insulating layer is at least in contact with the source and drain electrodes, so that the array substrate is obtained.
2. The method of manufacturing an array substrate according to claim 1, wherein the first patterned conductive layer further includes a second conductive electrode and a second conductive member, the first conductive electrode being disposed corresponding to the second conductive electrode, the first conductive member being disposed corresponding to the second conductive member, the method further comprising the steps of:
and forming a first contact hole and a second contact hole penetrating through the insulating layer and the semiconductor layer, wherein the first contact hole is arranged corresponding to the second conductive electrode, the second contact hole is arranged corresponding to the second conductive member, the first conductive electrode and the second conductive electrode are electrically connected through the first contact hole, and the first conductive member and the second conductive member are electrically connected through the second contact hole.
3. The method according to claim 1, wherein the patterned light-shielding insulating layer is made of at least one material selected from a black organic photoresist and an ink.
4. The method of manufacturing an array substrate according to claim 1, wherein the first patterned conductive layer is made of Mo or Mo alloy, and the second patterned conductive layer is made of Mo or Mo alloy.
5. The method of manufacturing an array substrate according to claim 1 or 4, wherein the first patterned conductive layer is made of a material including a MoTiNi alloy, and the second patterned conductive layer is made of a material including a MoTiNi alloy.
6. An array substrate, characterized in that the array substrate comprises:
a substrate;
a first patterned conductive layer formed on the substrate, the first patterned conductive layer including a gate electrode;
an insulating layer covering the first patterned conductive layer and the substrate;
a patterned semiconductor layer formed on a side of the insulating layer away from the substrate, the patterned semiconductor layer including an active layer;
the second patterned conductive layer is formed on one side of the patterned semiconductor layer far away from the substrate, and comprises a first conductive member, a source electrode, a drain electrode and a first conductive electrode, wherein the active layer is arranged corresponding to the grid electrode, and the source electrode and the drain electrode are arranged corresponding to the active layer and are electrically connected with the active layer; and
and a patterned light shielding insulating layer covering the source and drain electrodes, the insulating layer, and the active layer and exposing the first conductive electrode and the first conductive member, the patterned light shielding insulating layer being in contact with at least the source and drain electrodes.
7. The array substrate of claim 6, wherein the first patterned conductive layer further comprises a second conductive electrode and a second conductive member, a first conductive electrode is disposed corresponding to the second conductive electrode, the first conductive member is disposed corresponding to the second conductive member, the first conductive electrode and the second conductive electrode are electrically connected through a first contact hole penetrating the patterned semiconductor layer and the insulating layer, and the first conductive member and the second conductive member are electrically connected through a second contact hole penetrating the patterned semiconductor layer and the insulating layer.
8. The array substrate of claim 6, wherein the patterned light-shielding insulating layer is made of at least one material selected from a black organic photoresist and an ink.
9. The array substrate of claim 6, wherein the first patterned conductive layer comprises a MoTiNi alloy and the second patterned conductive layer comprises a MoTiNi alloy.
10. A display device, characterized in that the display device comprises a backlight module comprising the array substrate according to any one of claims 6-9.
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| CN112309967B (en) * | 2020-10-16 | 2022-03-08 | 深圳市华星光电半导体显示技术有限公司 | Backlight module and manufacturing method thereof |
| CN112310118A (en) * | 2020-10-16 | 2021-02-02 | 深圳市华星光电半导体显示技术有限公司 | Driving circuit board and manufacturing method thereof |
| CN112838051B (en) * | 2021-01-05 | 2024-04-05 | 深圳市华星光电半导体显示技术有限公司 | Manufacturing method of driving circuit board |
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| KR101192750B1 (en) * | 2005-12-30 | 2012-10-18 | 엘지디스플레이 주식회사 | Thin Film Transistor Array Substrate And Method For Fabricating The Same |
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| CN1797159A (en) * | 2004-12-30 | 2006-07-05 | Lg.菲利浦Lcd株式会社 | Thin-film transistor array substrate and its manufacturing method |
| CN101241911A (en) * | 2008-03-21 | 2008-08-13 | 友达光电股份有限公司 | Grid driving circuit integrated on display panel and its making method |
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