CN111584492B - Semiconductor structure and method for determining manufacturing parameters thereof - Google Patents

Semiconductor structure and method for determining manufacturing parameters thereof Download PDF

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CN111584492B
CN111584492B CN202010437632.XA CN202010437632A CN111584492B CN 111584492 B CN111584492 B CN 111584492B CN 202010437632 A CN202010437632 A CN 202010437632A CN 111584492 B CN111584492 B CN 111584492B
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semiconductor structure
etching
parameter
mask layer
stacked structure
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CN111584492A (en
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陈琳
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region

Abstract

The embodiment of the invention provides a semiconductor structure and a method for determining manufacturing parameters thereof; the method comprises the following steps: detecting a first parameter corresponding to the first semiconductor structure; the first semiconductor structure comprises at least a first stacked structure; the first stacked structure comprises a plurality of layers of first grid electrodes arranged at intervals; etching the first stacked structure to form a first step region on the first gate; the first step area is provided with a first contact area; the first parameter characterizes a position of each first contact region in the plurality of first contact regions at a respective first step region; adjusting a second parameter based on the detected first parameter so that a second grid electrode with the thickness meeting a first preset thickness condition exists around each second contact area in the second semiconductor structure; the second semiconductor structure comprises at least a second stacked structure; the second parameter represents an etching parameter of the mask layer for etching the second stacked structure to form the second step region.

Description

Semiconductor structure and method for determining manufacturing parameters thereof
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor structure and a method for determining manufacturing parameters of the semiconductor structure.
Background
With the continuous increase of the demands of various electronic devices on integration level and data storage density, it is more and more difficult for a common two-dimensional memory device to meet the demands, and under such a situation, a three-dimensional memory is produced. The three-dimensional memory mainly includes a vertical channel layer, and a plurality of horizontally stacked gates disposed outside the channel layer. Each of the plurality of horizontally stacked gates generally has a step region, so that each gate is electrically connected to a vertical Contact hole (CT) through the corresponding step region, thereby implementing an addressing operation of a corresponding memory cell of each gate.
However, the step regions manufactured according to the related art three-dimensional memory step region manufacturing process may cause a failure in the addressing operation of the memory cells corresponding to the gates of some layers.
Disclosure of Invention
In order to solve the related technical problems, embodiments of the present invention provide a semiconductor structure and a method for determining manufacturing parameters thereof, where a step region manufactured by using the parameters determined by the method for determining parameters of a semiconductor structure can ensure the success of an addressing operation of a memory cell corresponding to each layer of gate.
The embodiment of the invention provides a method for determining manufacturing parameters of a semiconductor structure, which comprises the following steps:
detecting a first parameter corresponding to the first semiconductor structure; the first semiconductor structure comprises at least a first stacked structure; the first stacked structure comprises a plurality of layers of first grid electrodes arranged at intervals; etching the first stacked structure to form a first step area on the first grid electrodes arranged at intervals; the first step area is provided with a first contact area; the first parameter characterizes a position of each of a plurality of first contact regions at a respective first step region;
adjusting a second parameter based on the detected first parameter so that a second grid electrode with the thickness meeting a first preset thickness condition exists around each second contact area in the second semiconductor structure; the second semiconductor structure comprises at least a second stacked structure; the second stacked structure comprises a plurality of layers of second grid electrodes arranged at intervals; etching the second stacked structure to form a second step area on the plurality of layers of second grid electrodes arranged at intervals; the second parameter represents an etching parameter for etching the second stacked structure to form a mask layer of the second step area.
In the above scheme, the first parameter includes a thickness of the first gate around the first contact region;
the adjusting a second parameter based on the detected first parameter includes:
making a difference between the thickness of the first grid electrode around the first contact area and a first preset thickness;
determining the size of the corresponding step area in the manufacture of the semiconductor structure according to the difference result;
and determining the etching parameters for etching the corresponding mask layer in the manufacture of the semiconductor structure according to the size of the corresponding step area.
In the foregoing solution, determining an etching parameter for etching a corresponding mask layer in manufacturing a semiconductor structure according to the size of the corresponding step region includes:
determining the size of etching the corresponding mask layer in the manufacture of the semiconductor structure according to the size of the corresponding step area;
and determining the duration of etching the corresponding mask layer in the semiconductor structure manufacturing according to the size of etching the corresponding mask layer in the semiconductor structure manufacturing.
In the foregoing solution, the detecting a first parameter corresponding to a first semiconductor structure includes:
the position of each first contact region in the plurality of first contact regions in the corresponding first step region is detected by a Scanning Electron Microscope (SEM) in combination with an image processing algorithm.
In the foregoing, before the inspecting the first semiconductor structure by using SEM, the method further includes:
and carrying out slicing processing on the first semiconductor structure.
In the above scheme, the sizes of the corresponding second step regions on the second gates of different layers are not completely the same.
In the above scheme, the material of the first mask layer includes a Photoresist (PR).
An embodiment of the present invention further provides a semiconductor structure, including:
a second stacked structure; the second stacked structure comprises a plurality of layers of second grid electrodes arranged at intervals;
a plurality of layers of second grids which are arranged at intervals are provided with second step areas; the sizes of corresponding second step areas on the second gates of different layers are not completely the same;
and a second contact area is arranged in the second step area, and a second grid electrode with the thickness meeting a first preset thickness condition exists around the second contact area.
In the above scheme, the size of the corresponding second step region on the second gate at the bottommost layer is wider than the size of the corresponding second step region on the second gate at the topmost layer.
In the above scheme, the size of the corresponding second step region on the second gate electrode becomes wider as the layer height at which the second gate electrode is located decreases.
The semiconductor structure and the method for determining the manufacturing parameters thereof provided by the embodiment of the invention detect the first parameters corresponding to the first semiconductor structure; the first semiconductor structure comprises at least a first stacked structure; the first stacked structure comprises a plurality of layers of first grid electrodes arranged at intervals; etching the first stacked structure to form a first step area on the first grid electrodes arranged at intervals; the first step area is provided with a first contact area; the first parameter characterizes a position of each of a plurality of first contact regions at a respective first step region; adjusting a second parameter based on the detected first parameter so that a second grid electrode with the thickness meeting a first preset thickness condition exists around each second contact area in the second semiconductor structure; the second semiconductor structure comprises at least a second stacked structure; the second stacked structure comprises a plurality of layers of second grid electrodes arranged at intervals; etching the second stacked structure to form a second step area on the plurality of layers of second grid electrodes arranged at intervals; the second parameter represents an etching parameter for etching the second stacked structure to form a mask layer of the second step area. . In the embodiment of the invention, a first semiconductor structure is formed by using initial manufacturing parameters, and the position of each first contact region (the part of the CT penetrating through the corresponding first step region) in the first semiconductor structure is detected; then, based on the detection result, adjusting the etching parameters of the mask layer for forming the step area in the manufacture of the semiconductor structure; and forming a second semiconductor structure by using the adjusted manufacturing parameters so that a second grid electrode with the thickness meeting the first preset thickness condition exists around each second contact area in the second semiconductor structure. That is to say, the step region of each layer of gate manufactured by using the adjusted parameters can be electrically connected with the corresponding CT on the step region, so that the success of the addressing operation of the corresponding memory cell of each layer of gate can be ensured.
Drawings
FIGS. 1 a-1 g are schematic cross-sectional views illustrating a device structure during formation of a step region of a three-dimensional memory in the related art;
FIG. 2 is a cross-sectional view of a device structure with a step region formed in a related art;
FIGS. 3 a-3 c are schematic cross-sectional views of a device structure during formation of a CT on a step region of a three-dimensional memory according to the related art;
FIG. 4 is a cross-sectional view of a device structure in which the landing positions of CT on the corresponding step surfaces are shifted in the related art;
fig. 5 is a schematic flow chart illustrating an implementation of a parameter determination method according to an embodiment of the present invention;
fig. 6a to fig. 6f are schematic cross-sectional views of device structures in an implementation process of a parameter determination method according to an embodiment of the present invention.
Description of reference numerals:
10-a stacked structure; 20-an initial mask layer corresponding to the step structure; 21-a first trim mask layer; 22-a second trim mask layer; 23-a third trim mask layer; 12-a step area; 30-a dielectric layer; a mask layer corresponding to 40-CT; 50-CT.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the following describes specific technical solutions of the present invention in further detail with reference to the accompanying drawings in the embodiments of the present invention.
In order to more clearly illustrate the embodiments of the present invention, a process of forming a step region of a three-dimensional memory in the related art will be described first. In the related art, when manufacturing a three-dimensional memory step region, the widths of the boundaries of two adjacent step regions in the step direction are generally set to be equal (hereinafter, the equal value is simply referred to as D), so that the process parameters for manufacturing the step region can be simplified. Fig. 1 a-1 g are schematic cross-sectional views of device structures during formation of a three-dimensional memory step region.
First, refer to fig. 1 a. Providing a three-dimensional memory structure to be etched to form a step area, wherein the three-dimensional memory structure comprises: a substrate (not shown in fig. 1 a-1 g), a stacked structure 10 on said substrate. And an initial mask layer 20 (i.e., an initial mask layer corresponding to the step structure) on the stacked structure 10; the stacked structure 10 includes a plurality of sacrificial layers and insulating layers alternately arranged. In practice, the material of the initial masking layer 20 may comprise photoresist. Here, the sacrificial layer may be removed in a subsequent process, and a gate material (e.g., metal tungsten (W)) may be filled at the removed position, and after the gate material is filled, the corresponding position of the sacrificial layer is referred to as a gate.
Next, refer to fig. 1 b. Performing a step (1st TRIM) of trimming the size of the initial mask layer 20 for the first time, so that the trimmed mask layer, i.e., the first TRIM mask layer 21, exposes more surfaces of the stacked structure 20 than before trimming; in practice, the TRIM size in this TRIM step (TRIM CD) is equal to D. Here, trimming of the mask layer is also substantially achieved by etching the mask layer.
Next, refer to fig. 1 c. And (3) performing first etching (1st ETCH) by using the first trimming mask layer 21 as a mask, wherein the thickness of a gate is reduced by one layer in the whole area which is not covered by the first mask layer 21 in the stacked structure.
Next, refer to fig. 1 d. Performing a second trimming of the size of the initial mask layer 20 (2st TRIM) so that the trimmed mask layer, i.e., the second trimming mask layer 22, exposes more of the surface of the stacked structure 20 than before trimming (the first trimming mask layer 21); in practice, the TRIM size in this TRIM step (TRIM CD) is equal to D.
Next, refer to fig. 1 e. And performing second etching (2st ETCH) by using the second trimming mask layer 22 as a mask, wherein the thickness of a gate is reduced by one layer in the whole area which is not covered by the second trimming mask layer 22 in the stacked structure.
Next, reference is made to fig. 1f to 1 g. The step of trimming the size of the initial mask layer 20 and the step of performing etching with the trimmed mask layer as a mask are repeated, for example, 3st TRIM-3 st ETCH-4 st TRIM-4 st ETCH (here, the trimming times and the etching times are related to the specific number of steps, and only 3st TRIM (third TRIM mask layer 23) and 3st ETCH are shown in fig. 1 f-1 g) are performed, so as to form a corresponding step region in each layer of gate, and a schematic diagram of the formed step region 12 can be referred to fig. 2.
Next, a process of forming a CT on a step region of a three-dimensional memory in the related art will be described. Fig. 3 a-3 c are schematic cross-sectional views of the device structure during the formation of a CT on the step region of the three-dimensional memory.
First, refer to fig. 3 a. A dielectric layer 30 is formed on the stacked structure where the stepped region 12 is formed. In practical applications, the material of the dielectric layer 30 may include TEOS.
Next, refer to fig. 3 b. Forming a mask layer 40 corresponding to the CT on the dielectric layer 30; in practice, the material of the mask layer 40 may include PR.
Next, refer to fig. 3 c. Etching the dielectric layer 30 and part of the step region 12 according to the mask layer 40 to form a CT 50; the CT 50 penetrates through the dielectric layer and the corresponding step region.
As can be seen from fig. 3c, there is a gate on both the left and right sides of each CT. In the subsequent process, a conductive material is inserted into the CT, so that each layer of gate is conductively connected with the CT through the corresponding step region.
However, in practice, the CT is formed with a topography that is not perpendicular like that shown in FIG. 3 c. In an actual manufacturing process, due to a combined action of various reasons, a landing position of the CT on a corresponding step region (where the landing position can be understood as a position where the CT penetrates through the corresponding step region) is shifted, referring to fig. 4, the landing position is shifted more and more seriously, a thickness of a gate on the right side of a part of the CT is gradually reduced, even thicknesses of gates on the left side and the right side of the part of the CT are all zero, and at this time, the CT cannot be in normal conductive connection with the corresponding step. That is to say, the manufacturing process of the equal-width step region in the related art does not fully consider the actual process condition of the CT formation, that is, the CT is difficult to land perfectly at the middle position of the corresponding step region in the actual process condition, and even there is a possibility of landing on the wrong step region. Here, the various reasons include: with the continuous increase of the storage capacity of the three-dimensional memory, the number of layers of the stacked structure is increased, on one hand, the alignment (OVL) offset of the CT is more and more serious due to the Local pressure (english can be expressed as Local Stress) between the dielectric layer and the stacked structure; on the other hand, the inclination and distortion of deep hole etching are more obvious. In the related art, although the risk that the CT cannot be normally and electrically connected with the corresponding step can be reduced by reducing the OVL offset of the CT and the inclination and distortion of the deep hole etching, in practical application, the reduction of the OVL offset of the CT and the inclination and distortion of the deep hole etching is not easy to realize.
Based on this, in various embodiments of the present invention, first a first semiconductor structure is formed using initial manufacturing parameters, and a position of each first contact region (a portion of the CT that penetrates through a corresponding first step region) in the first semiconductor structure at the corresponding first step region is detected; then, based on the detection result, adjusting the etching parameters of the mask layer for forming the step area in the manufacture of the semiconductor structure; and forming a second semiconductor structure by using the adjusted manufacturing parameters so that a second grid electrode with the thickness meeting the first preset thickness condition exists around each second contact area in the second semiconductor structure. That is to say, in the embodiment of the present invention, the size of the step region corresponding to each layer of gate in all the gates is not set to be the same, but an appropriate step region size is set in combination with the landing position of the CT in the corresponding step region in practical application, so that a gate having a thickness meeting the predetermined thickness condition exists around each CT. That is to say, the step region of each layer of gate manufactured by the adjusted parameters can be electrically connected with the corresponding CT on the step region, so that the step region manufactured by the parameter determination method in the embodiment of the present invention can ensure the success of the addressing operation of the memory cell corresponding to each layer of gate.
An embodiment of the present invention provides a method for determining a semiconductor structure manufacturing parameter, and fig. 5 is a schematic flow chart illustrating an implementation of the method for determining a semiconductor structure manufacturing parameter according to the embodiment of the present invention. As shown in fig. 5, the method comprises the steps of:
step 501: detecting a first parameter corresponding to the first semiconductor structure; the first semiconductor structure comprises at least a first stacked structure; the first stacked structure comprises a plurality of layers of first grid electrodes arranged at intervals; etching the first stacked structure to form a first step area on the first grid electrodes arranged at intervals; the first step area is provided with a first contact area; the first parameter characterizes a position of each of a plurality of first contact regions at a respective first step region;
step 502: adjusting a second parameter based on the detected first parameter so that a second grid electrode with the thickness meeting a first preset thickness condition exists around each second contact area in the second semiconductor structure; the second semiconductor structure comprises at least a second stacked structure; the second stacked structure comprises a plurality of layers of second grid electrodes arranged at intervals; etching the second stacked structure to form a second step area on the plurality of layers of second grid electrodes arranged at intervals; the second parameter represents an etching parameter for etching the second stacked structure to form a mask layer of the second step area.
Here, the first semiconductor structure refers to a semiconductor structure manufactured by a manufacturing process using parameters before adjustment; the second semiconductor structure refers to a corresponding semiconductor structure manufactured by the manufacturing process using the adjusted parameter (i.e., the second parameter).
In step 501, the main purpose is to measure the landing position of each of the plurality of first contact regions in the first semiconductor structure on the corresponding step region, so as to obtain the thickness of the gate on the left and right sides of each contact region. Here, the first contact region refers to a portion of the first CT that penetrates the corresponding first step region.
The first semiconductor structure is a semiconductor structure that has been formed using current manufacturing parameters. Here, the first semiconductor structure may refer to fig. 6b, the first semiconductor structure includes at least a first stacked structure; the first stacked structure comprises a plurality of layers of first grid electrodes arranged at intervals; each layer of grid electrode in the plurality of layers of first grid electrodes arranged at intervals is provided with a first step area; the first step region is provided with a first contact region. The sizes, i.e., widths, of the corresponding first step regions on the first gates of different layers are identical.
In practical applications, the specific forming method of the first semiconductor structure may refer to fig. 1a to 1g and fig. 3a to 3c, which are not described herein again. A dielectric layer (also referred to as an insulating layer) is further disposed between the adjacent first gates, and the dielectric layer is a non-conductive material and is used for separating the adjacent first gates.
In practical applications, there are various specific ways to detect the first parameter corresponding to the first semiconductor structure, and in some embodiments, the detecting the first parameter corresponding to the first semiconductor structure includes:
detecting, by the SEM in combination with an image processing algorithm, a position of each of the plurality of first contact areas at the corresponding first step area.
In practical application, a cross-sectional image of the first semiconductor structure similar to that in fig. 6b may be obtained through an SEM, then, the outline of each first contact region and the corresponding first step region of the first contact region is determined according to an image processing algorithm, and then, the position of each first contact region in the image at the corresponding first step region, that is, the first parameter is obtained by combining a proportional relationship between the image size and the actual size of the first semiconductor structure.
In practical applications, in order to obtain a cross-sectional image of the first semiconductor structure by using SEM, the first semiconductor structure needs to be sliced.
In some embodiments, prior to inspecting the first semiconductor structure with the SEM, the method further comprises:
and carrying out slicing processing on the first semiconductor structure.
In step 502, after knowing the landing position of each of the plurality of first contact regions in the first semiconductor structure at the corresponding step region, the deviation of the actual manufacturing process of the semiconductor structure is indirectly obtained, and based on this, the landing position can be utilized to set the proper step region size, thereby realizing the compensation of the deviation of the actual manufacturing process.
Here, the second parameter may be understood as a set of multiple etching parameters corresponding to multiple times of trimming an initial mask layer corresponding to a step structure in a process of forming a step region in a semiconductor structure.
Here, the second contact region refers to a portion of the second CT that penetrates the corresponding second step region. The second gate electrode with the thickness meeting the first preset thickness condition exists around each second contact region in the second semiconductor structure, and it can be understood that each second contact region lands on the correct step region, and the second gate electrode with a certain thickness exists on two sides of each second contact region. The first predetermined thickness condition may be satisfied, specifically, that the second gates around the second contact region are all greater than the first predetermined thickness. Here, the first predetermined thickness is set in such a way that when a gate electrode of the first predetermined thickness is present on both the left and right sides of each contact region, the contact region is ensured to be conductively connected to the corresponding step region. In practical application, the first preset thickness can be adjusted according to practical situations. In some embodiments, the width of the first step region (denoted as l) and the diameter of the first CT (denoted as d) may be obtained, while the first preset thickness may be set to be slightly larger than 1/2(l-d) in consideration that the bottom dimension of the first CT is larger than the top dimension.
In some embodiments, the first parameter comprises a thickness of the first gate around the first contact region;
the adjusting a second parameter based on the detected first parameter includes:
making a difference between the thickness of the first grid electrode around the first contact area and a first preset thickness;
determining the size of the corresponding step area in the manufacture of the semiconductor structure according to the difference result;
and determining the etching parameters for etching the corresponding mask layer in the manufacture of the semiconductor structure according to the size of the corresponding step area.
In practical application, the thickness conditions of the first grid electrodes on the left side and the right side of the first contact area are known after the first parameters are obtained; then, the thickness of the side with the smaller thickness in the two sides of the first contact region may be subtracted from a first preset thickness (which may be understood as a reference thickness to be reserved), and an optimized size of the step region corresponding to each layer of the gate electrode is determined according to a subtraction result (in practical application, when the subtraction result is a negative value, it indicates that the reserved thickness of the first contact region in the toilet is not enough, and the step width needs to be adjusted, and at this time, the difference result or the thickness slightly greater than the difference result may be used as the width of the corresponding step region that needs to be optimized); and then, the optimized size is used as the target size of a step area required to be formed in the semiconductor structure manufacturing, and the etching parameters for etching the mask layer when the step area is formed in the semiconductor structure manufacturing can be adjusted according to the target size. Conversely, in practical applications, the trimming size (TRIM CD) of the mask layer can be adjusted by adjusting the parameters for etching the mask layer, so as to adjust the width of the corresponding step region.
In practical application, when the mask layer is etched, the adjustable etching parameters include: etching duration, etching cavity air pressure, radio frequency power, etching gas concentration, etching speed and the like.
In an embodiment, the determining, according to the size of the corresponding step region, an etching parameter for etching a corresponding mask layer in manufacturing a semiconductor structure includes:
determining the size of etching the corresponding mask layer in the manufacture of the semiconductor structure according to the size of the corresponding step area;
and determining the duration of etching the corresponding mask layer in the semiconductor structure manufacturing according to the size of etching the corresponding mask layer in the semiconductor structure manufacturing.
The following illustrates how the duration of the etch is adjusted. Referring to fig. 6a, fig. 6a is a step region of a semiconductor structure formed by using current manufacturing parameters, at this time, referring to fig. 6b, a positional relationship between a CT and a corresponding step region, where a CT landing position identified in fig. 6b is not good, and a CT on a gate of a lowest layer is not even landed on a correct step region, based on which it is determined that at least the step region corresponding to the identified CT needs to be increased rightward by a certain width, the increased width may be determined according to a first preset thickness, and under the condition that the increased width is determined, a trim size of a mask layer when the step region is formed may be correspondingly decreased, and in order to achieve a decrease in the trim size of the mask layer, an etching duration when the mask layer is etched may be decreased. Thus, the optimization adjustment of the mask layer etching parameter, namely the second parameter, is completed once.
In practical application, the optimized mask layer etching parameters can be utilized to manufacture the second semiconductor structure so as to obtain a step region with a proper size, and a second gate with a thickness meeting a first preset thickness condition exists around each second CT in the manufactured second semiconductor structure.
The step region adjustment is performed separately for each step region corresponding to each layer of gate. That is to say, the size of the second step region corresponding to each layer of the second gate in the second gates is a result of adjustment according to actual conditions, and the sizes of the corresponding second step regions on the second gates of different layers are not completely the same. That is, the sizes of the corresponding second step regions on the second gates of different layers may be the same or different, and the same or different sizes are determined based on whether the widths of the corresponding step regions are adjusted.
The second semiconductor structure is fabricated in a manner similar to the first semiconductor structure, i.e., the fabrication parameters are the same except for the second parameter.
In practical application, when the second parameter is optimized and adjusted once, and the landing position of the CT of the semiconductor structure obtained by using the adjusted second parameter on the corresponding step region does not reach the ideal state yet, the above process may be repeated to optimize and adjust the second parameter many times to obtain the optimal second parameter. The process of multiple optimization adjustments can be referred to herein in fig. 6a-6 f. Specifically, the dashed lines in the step areas in fig. 6c and 6e indicate that when the width of the step area is not adjusted in fig. 6a, the width position of the corresponding step area indicates that the landing position of the CT on the corresponding step area gradually reaches the ideal state from fig. 6b to fig. 6d, and then from fig. 6d to fig. 6f, that is, the landing position of the CT on the corresponding step area is closer to the middle position of the corresponding step area. After the optimal second parameters are obtained, the optimal second parameters may be cured and used directly in the subsequent fabrication process of the semiconductor structure.
The embodiment of the invention provides a method for determining manufacturing parameters of a semiconductor structure, which comprises the steps of detecting a first parameter corresponding to a first semiconductor structure; the first semiconductor structure comprises at least a first stacked structure; the first stacked structure comprises a plurality of layers of first grid electrodes arranged at intervals; etching the first stacked structure to form a first step area on the first grid electrodes arranged at intervals; the first step area is provided with a first contact area; the first parameter characterizes a position of each of a plurality of first contact regions at a respective first step region; adjusting a second parameter based on the detected first parameter so that a second grid electrode with the thickness meeting a first preset thickness condition exists around each second contact area in the second semiconductor structure; the second semiconductor structure comprises at least a second stacked structure; the second stacked structure comprises a plurality of layers of second grid electrodes arranged at intervals; etching the second stacked structure to form a second step area on the plurality of layers of second grid electrodes arranged at intervals; the second parameter represents an etching parameter for etching the second stacked structure to form a mask layer of the second step area. In the embodiment of the invention, a first semiconductor structure is formed by using initial manufacturing parameters, and the position of each first contact region (the part of the CT penetrating through the corresponding first step region) in the first semiconductor structure is detected; then, based on the detection result, adjusting the etching parameters of the mask layer for forming the step area in the manufacture of the semiconductor structure; and forming a second semiconductor structure by using the adjusted manufacturing parameters so that a second grid electrode with the thickness meeting the first preset thickness condition exists around each second contact area in the second semiconductor structure. That is to say, the step region of each layer of gate manufactured by using the adjusted parameters can be electrically connected with the corresponding CT on the step region, so that the success of the addressing operation of the corresponding memory cell of each layer of gate can be ensured.
Meanwhile, after the parameter adjusting method provided by the embodiment of the invention is used, on one hand, the requirements on OVL (over-the-horizon) deviation indexes of CT (computed tomography) and inclination and distortion indexes of deep hole etching in the manufacturing process of the three-dimensional memory can be reduced, so that the corresponding process window is enlarged, and the yield of the three-dimensional memory is further improved; on the other hand, when the success of the addressing operation of the memory cell corresponding to each layer of grid electrode is ensured, the effective storage area of the three-dimensional memory can be increased.
Based on the above method for determining the semiconductor manufacturing parameters, the semiconductor manufacturing is performed by using the determined parameters, and with reference to fig. 6e and 6f, an embodiment of the present invention further provides a semiconductor structure, where the semiconductor structure includes:
a second stacked structure; the second stacked structure comprises a plurality of layers of second grid electrodes arranged at intervals;
a plurality of layers of second grids which are arranged at intervals are provided with second step areas; the sizes of corresponding second step areas on the second gates of different layers are not completely the same;
and a second contact area is arranged in the second step area, and a second grid electrode with the thickness meeting a first preset thickness condition exists around the second contact area.
In one embodiment, the size of the corresponding second step region on the second gate electrode at the bottom layer is wider than that on the second gate electrode at the top layer.
In practice, as shown in FIG. 6e, |6I.e. the size of the corresponding second step region on the second gate at the lowermost layer,/1I.e. the size of the corresponding second step region on the second gate at the topmost layer. It will be appreciated that in practical applications, as shown in fig. 6f, the size l of the corresponding second step region on the topmost second gate electrode1Not adjusted (i.e. | in FIG. 6 e)2、l3、l4、l5、l6The width and/of the respective step region shown by the dashed line in the corresponding second step region1The same), as the CT etching depth increases, the deviation of the actual landing position of the second contact region in the corresponding second step region from the ideal position becomes more and more serious, that is, the width of the corresponding second step region on the second gate at the bottom layer is increased to the greatest extent.
In one embodiment, the size of the corresponding second step region on the second gate electrode becomes wider as the layer height at which the second gate electrode is located decreases.
In practical application, as shown in fig. 6e, the size l of the corresponding second step region on the second gate electrode1、l2、l3、l4、l5、l6The layer height is lower and lower, and1、l2、l3、l4、l5、l6are increasingly wider.
In practical applications, the semiconductor structure can be applied to a three-dimensional memory.
It should be noted that: "first," "second," and the like are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order.
In addition, the technical solutions described in the embodiments of the present invention may be arbitrarily combined without conflict.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention.

Claims (7)

1. A method for determining manufacturing parameters of a semiconductor structure, the method comprising:
detecting a first parameter corresponding to the first semiconductor structure; the first semiconductor structure comprises at least a first stacked structure; the first stacked structure comprises a plurality of layers of first grid electrodes arranged at intervals; etching the first stacked structure to form a first step area on the first grid electrodes arranged at intervals; the first step area is provided with a first contact area; the first parameter characterizes a position of each of a plurality of first contact regions at a respective first step region;
adjusting a second parameter based on the detected first parameter so that a second grid electrode with the thickness meeting a first preset thickness condition exists around each second contact area in the second semiconductor structure; the second semiconductor structure comprises at least a second stacked structure; the second stacked structure comprises a plurality of layers of second grid electrodes arranged at intervals; etching the second stacked structure to form a second step area on the plurality of layers of second grid electrodes arranged at intervals; the second parameter represents an etching parameter for etching the second stacked structure to form a mask layer of the second step area.
2. The method of claim 1, wherein the first parameter comprises a thickness of the first gate around the first contact region;
the adjusting a second parameter based on the detected first parameter includes:
making a difference between the thickness of the first grid electrode around the first contact area and a first preset thickness;
determining the size of the corresponding step area in the manufacture of the semiconductor structure according to the difference result;
and determining the etching parameters for etching the corresponding mask layer in the manufacture of the semiconductor structure according to the size of the corresponding step area.
3. The method of claim 2, wherein determining the etching parameters for etching the corresponding mask layer in the semiconductor structure fabrication according to the size of the corresponding step region comprises:
determining the size of etching the corresponding mask layer in the manufacture of the semiconductor structure according to the size of the corresponding step area;
and determining the duration of etching the corresponding mask layer in the semiconductor structure manufacturing according to the size of etching the corresponding mask layer in the semiconductor structure manufacturing.
4. The method of claim 1, wherein detecting the first parameter corresponding to the first semiconductor structure comprises:
detecting, by an electron scanning electron microscope SEM in combination with an image processing algorithm, a position of each of the plurality of first contact areas at the corresponding first step area.
5. The method of claim 4, wherein prior to inspecting the first semiconductor structure with the SEM, the method further comprises:
and carrying out slicing processing on the first semiconductor structure.
6. The method of claim 1, wherein the sizes of the corresponding second step regions on the second gates of different layers are not all the same.
7. The method of claim 1, wherein the material of the mask layer comprises photoresist.
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107039457A (en) * 2016-01-08 2017-08-11 三星电子株式会社 Three-dimensional semiconductor memory device and its manufacture method
CN109473433A (en) * 2018-11-09 2019-03-15 长江存储科技有限责任公司 Three-dimensional storage and preparation method thereof
CN109935595A (en) * 2019-03-29 2019-06-25 长江存储科技有限责任公司 A kind of 3D nand memory part and its manufacturing method

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Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107039457A (en) * 2016-01-08 2017-08-11 三星电子株式会社 Three-dimensional semiconductor memory device and its manufacture method
CN109473433A (en) * 2018-11-09 2019-03-15 长江存储科技有限责任公司 Three-dimensional storage and preparation method thereof
CN109935595A (en) * 2019-03-29 2019-06-25 长江存储科技有限责任公司 A kind of 3D nand memory part and its manufacturing method

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