CN113838849B - Dynamic random access memory and manufacturing method thereof - Google Patents

Dynamic random access memory and manufacturing method thereof Download PDF

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Publication number
CN113838849B
CN113838849B CN202010511356.7A CN202010511356A CN113838849B CN 113838849 B CN113838849 B CN 113838849B CN 202010511356 A CN202010511356 A CN 202010511356A CN 113838849 B CN113838849 B CN 113838849B
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Prior art keywords
bit line
line contact
substrate
contact structure
word line
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CN113838849A (en
Inventor
柯婷婷
曾健旭
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Winbond Electronics Corp
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Winbond Electronics Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/50—Peripheral circuit region structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines

Abstract

The invention provides a dynamic random access memory and a manufacturing method thereof. The DRAM includes a buried word line, a first dielectric layer, a bit line and a bit line contact structure. The buried word line is formed in the word line trench of the substrate and extends along the first direction. The first dielectric layer is formed in the word line trench. The first dielectric layer is located above the buried word line and directly contacts the buried word line. The bit line is formed on the substrate and extends along a second direction perpendicular to the first direction. The bit line contact structure is formed on the substrate and is located between the bit line and the substrate. The bottom surface of the bit line contact structure is higher than the top surface of the first dielectric layer. The dynamic random access memory provided by the invention can accurately control the position and the size of the bit line contact structure, and can obviously improve the yield of the memory device.

Description

Dynamic random access memory and manufacturing method thereof
Technical Field
The present invention relates to a memory device, and more particularly, to a dynamic random access memory and a method for fabricating the same.
Background
With the trend of miniaturization of electronic products, there is a demand for miniaturization of memory devices. However, with miniaturization of memory devices, it becomes more difficult to improve the yield of memory devices.
For example, in a dynamic random access memory (dynamic random access memory, DRAM) having buried word lines, bit line contact structures are typically formed between adjacent buried word lines that are electrically connected to bit lines. In the photolithography process of forming the bit line contact hole, if the size of the bit line contact hole is too small, it may not be completely exposed. Therefore, the bit line contact structure cannot be formed or fails. In this way, the yield of the memory device is reduced. On the other hand, if the size of the bit line contact hole is too large, adjacent bit line contact holes may be connected to each other to cause a short circuit. In this way, the yield of the memory device is also reduced. Furthermore, the location of the failure or short circuit of the bit line contact structure is not expected. Therefore, when the critical dimension is small, the prior art photolithographic process for forming the bit line contact holes becomes very difficult to control, and the complexity and cost of the process are high. The above problems become more serious with miniaturization of the memory device.
Accordingly, there remains a need in the art for a high yield DRAM and a method of forming the same.
Disclosure of Invention
The embodiment of the invention provides a dynamic random access memory and a manufacturing method thereof, which can reduce the complexity of the manufacturing process and the production cost and improve the yield of a memory device.
An embodiment of the invention discloses a dynamic random access memory, comprising: a buried word line formed in the word line trench of the substrate, wherein the buried word line extends along a first direction; a first dielectric layer formed in the word line trench, wherein the first dielectric layer is located over and directly contacts the buried word line; bit lines formed on the substrate, wherein the bit lines extend along a second direction perpendicular to the first direction; and the bit line contact structure is formed on the substrate, wherein the bit line contact structure is positioned between the bit line and the substrate, and the bottom surface of the bit line contact structure is higher than the top surface of the first dielectric layer.
An embodiment of the invention discloses a method for manufacturing a dynamic random access memory, which comprises the following steps: forming a buried word line in a word line trench of a substrate, wherein the buried word line extends along a first direction; forming a first dielectric layer in the word line trench, wherein the first dielectric layer is located above and directly contacts the buried word line; forming a bit line on the substrate, wherein the bit line extends along a second direction perpendicular to the first direction; a bit line contact structure is formed on the substrate, wherein the bit line contact structure is located between the bit line and the substrate, and wherein a bottom surface of the bit line contact structure is higher than a top surface of the first dielectric layer.
In the method for manufacturing the dynamic random access memory provided by the embodiment of the invention, a plurality of parallel bit line contact grooves are formed, and then the bit line contact structure is formed in a self-aligned manner at the intersection position of the bit line contact grooves and the bit lines. Compared with the formation of the hole-shaped bit line contact hole, the manufacturing method of the dynamic random access memory provided by the embodiment of the invention can reduce the use of a photomask and can avoid the position deviation or the size variation of the bit line contact hole in the exposure step. Furthermore, the DRAM provided by the embodiment of the invention can accurately control the position and the size of the bit line contact structure. Therefore, the yield of the memory device can be significantly improved.
Drawings
FIG. 1 is a schematic top view of a DRAM according to some embodiments of the present invention;
fig. 2A, fig. 2B, fig. 3A, fig. 3B, fig. 4A, fig. 4B, fig. 5A, fig. 5B, fig. 6A, fig. 6B, fig. 7A, fig. 7B, fig. 8A, fig. 8B, fig. 9A, fig. 9B, fig. 10A, and fig. 10B are schematic cross-sectional views of a dram according to some embodiments of the present invention at various stages of a manufacturing process.
Symbol description
100 DRAM
102 substrate
104 isolation structure
105 active region
106 first dielectric layer
108 first insulating layer
110 buried word line
110A first conductive layer
110B second conductive layer
112 protective layer
114 first photomask layer
115 bit line contact trench
116 a first photoresist layer
122 bit line contact structure
122 first conductive material
132 bit line
132A third conductive layer
132B fourth conductive layer
134 second dielectric layer
142 second photomask layer
144 second photoresist layer
145 groove
152 insulating liner
154 second insulating layer
155 concave portion
162 sidewall spacers
164 gap filling layer
Detailed Description
The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of preferred embodiments, as illustrated in the accompanying drawings. Furthermore, repeated reference characters and/or words may be used in various examples of the invention. These repeated symbols or words are for simplicity and clarity and are not intended to limit the relationship between the various embodiments and/or the appearance structures.
The terms "about" and "approximately" herein generally mean within 20%, preferably within 10%, and more preferably within 5% of a given value or range. The numbers given herein are about numbers, meaning that "about" may still be implied without specific recitation.
The present invention provides a memory device and a method for manufacturing the same, and fig. 1 is a schematic top view of a dram 100 according to some embodiments of the present invention. Fig. 2A, 3A, 4A, 5A, 6A, 7A, 8A, 9A and 10A are schematic cross-sectional views drawn along a sectional line AA' of fig. 1. Fig. 2B, 3B, 4B, 5B, 6B, 7B, 8B, 9B, and 10B are schematic cross-sectional views drawn along a sectional line BB' of fig. 1.
Referring to fig. 1, fig. 2A and fig. 2B, an isolation structure 104 is formed in the substrate 102. In the present embodiment, the substrate 102 is a silicon substrate. Other structures may be formed in the substrate 102. For example, a p-type well, an n-type well, or a conductive region (not shown) may be formed in the substrate 102 by an implantation process. The isolation structures 104 may be formed using a suitable method. In the present embodiment, the isolation structure 104 is a shallow trench isolation structure of silicon oxide formed by thermal oxidation.
Referring to fig. 2B, a buried word line 110 is formed in the substrate 102. In detail, a photomask layer (not shown) may be formed overlying the substrate 102, and the photomask layer and the substrate 102 may be patterned to form word line trenches in the substrate 102. Next, the first conductive layer 110A is conformally formed in the word line trench. Next, a second conductive layer 110B is formed to fill the word line trench. Next, the first conductive layer 110A and the second conductive layer 110B are etched to a desired thickness by an etching-back process, as shown in fig. 2B. In this specification, the first conductive layer 110A and the second conductive layer 110B are collectively referred to as "buried word line 110". The material of the first conductive layer 110A may include titanium, titanium nitride, tungsten nitride, tantalum or tantalum nitride, other suitable conductive materials, or a combination thereof. The material of the second conductive layer 110B may include tungsten, aluminum, copper, gold, silver, alloys thereof, other suitable metallic materials, or combinations thereof. In the present embodiment, the first conductive layer 110A is titanium nitride, and the second conductive layer 110B is tungsten.
Referring to fig. 2B, a dielectric material is filled into the word line trench, and the excess dielectric material is removed by a planarization process to form a first dielectric layer 106 in the word line trench. The first dielectric layer 106 is located on the buried word line 110 and directly contacts the buried word line 110. The material of the first dielectric layer 106 may include an oxide, nitride, oxynitride, other suitable dielectric material, or a combination thereof. In this embodiment, the first dielectric layer 106 is silicon nitride.
Referring to fig. 1, fig. 2A and fig. 2B, a first insulating layer 108, a protective layer 112, a first photomask layer 114 and a first photoresist layer 116 are sequentially formed to cover the substrate 102. Next, the first photoresist layer 116 is patterned to define the bit line contact trench 115.
Referring to fig. 1, 3A and 3B, a first patterning process is performed to partially remove the first insulating layer 108 and the protective layer 112 by using the patterned first photoresist layer 116 as a photomask. After the first patterning process, the bit line contact trench 115 is formed in the first insulating layer 108 and the protective layer 112, and the first photomask layer 114 is completely removed. The first patterning process may be an anisotropic dry etch process. Fig. 2B and 3B are drawn along a sectional line BB' of fig. 1. In other words, fig. 2B and 3B are positions corresponding to the bit line contact trench 115. Therefore, after the first patterning process, the first photomask layer 114, the passivation layer 112 and the first insulating layer 108 are removed, exposing the substrate 102 and the first dielectric layer 106, as shown in fig. 3B.
In the first patterning process, the protection layer 112 can prevent the first insulating layer 108 from being over etched, which can lead to widening of the width of the bit line contact trench 115. If the width of the bit line contact trench 115 is too wide, it may cause adjacent bit line contacts to be shorted, thereby reducing the yield of the memory device. The materials of the first insulating layer 108 and the protective layer 112 may each independently include oxides, nitrides, oxynitrides, carbides, other suitable insulating materials, or combinations thereof. To avoid widening the width of the bit line contact trench 115, the material of the protective layer 112 is different from that of the first insulating layer 108. In this embodiment, the first insulating layer 108 is silicon nitride, and the protective layer 112 is silicon oxide. The first photomask layer 114 and the first photoresist layer 116 may each be formed using a suitable photomask material and photoresist material, which will not be described in detail herein.
Referring to fig. 1, fig. 4A and fig. 4B, a first conductive material 122 is formed on the substrate 102 and fills the bit line contact trench 115. Then, a planarization process (e.g., a cmp process) may be performed as needed to adjust the thickness of the first conductive material 122 and to make the first conductive material 122 have a flat top surface. The first conductive material 122 may comprise doped polysilicon, other suitable conductive materials, or a combination thereof. In this embodiment, the first conductive material 122 is polysilicon doped with arsenic.
Referring to fig. 1, fig. 5A and fig. 5B, an etching process is performed to remove the protection layer 112 and further reduce the thickness of the first conductive material 122. As shown in fig. 5A, after this etching process is performed, the first insulating layer 108 is exposed. As shown in fig. 5A, after the etching process, the top surface of the first conductive material 122 is lower than the top surface of the first insulating layer 108. In other words, after this etching process, the first conductive material 122 is only present in the bit line contact trench 115.
Referring to fig. 1, fig. 6A and fig. 6B, a third conductive layer 132A, a fourth conductive layer 132B, a second dielectric layer 134, a second photomask layer 142 and a second photoresist layer 144 are sequentially formed to cover the substrate 102. The second photoresist layer 144 is patterned to define trenches 145. The second dielectric layer 134 may have a single layer structure formed of a single material or a multi-layer structure formed of a plurality of different materials. The material of the second dielectric layer 134 may be the same as or similar to the material of the first dielectric layer 106. In this embodiment, the second dielectric layer 134 is a single layer structure formed of silicon nitride. In other embodiments, the second dielectric layer 134 is a three-layer structure formed by three kinds of silicon nitride, and the three kinds of silicon nitride are formed by different methods (e.g., chemical vapor deposition, low pressure chemical vapor deposition, and atomic layer deposition). The second photomask layer 142 and the second photoresist layer 144 may each use a suitable photomask material and photoresist material, which will not be described in detail herein.
Referring to fig. 1, fig. 7A and fig. 7B, a second patterning process is performed using the patterned second photoresist layer 144 as a photomask to partially remove the first conductive material 122, the third conductive layer 132A, the fourth conductive layer 132B, the second dielectric layer 134 and the second photomask layer 142. After the second patterning process, a plurality of bit lines 132 are formed in parallel with each other, and bit line contact structures 122 are formed at locations where the bit line contact trenches 115 meet the bit lines 132, as shown in fig. 1. More specifically, the bit line 132 is formed by the third conductive layer 132A and the fourth conductive layer 132B directly under the second photoresist layer 144. Furthermore, the bit line contact structure 122 is formed of a first conductive material 122 in the bit line contact trench 115 and directly under the bit line 132.
In this specification, the third conductive layer 132A and the fourth conductive layer 132B are collectively referred to as "bit line 132". The material of the third conductive layer 132A may be the same as or similar to the material of the first conductive layer 110A. The material of the fourth conductive layer 132B may be the same as or similar to the material of the second conductive layer 110B. The material of the third conductive layer may be different from the first conductive material 122. In the present embodiment, the third conductive layer 132A is titanium nitride, and the fourth conductive layer 132B is tungsten.
The second patterning process may be an anisotropic dry etch process. In the second patterning process, the removal rate of the first conductive material 122 is much greater than the removal rate of the first insulating layer 108 and the removal rate of the substrate 102. Therefore, the first conductive material 122 not covered by the second photoresist layer 144 can be completely removed while maintaining the shapes of the first insulating layer 108 and the substrate 102.
Furthermore, to avoid shorting, the second patterning process is etched to a depth deeper than the bit line contact structure 122. Referring to fig. 7A, after the second patterning process, a recess 155 is formed in the substrate adjacent to the bit line 132. The recess 155 has a stepped cross-sectional profile, and a bottom surface of the recess 155 is lower than a bottom surface of the bit line contact structure 122. Referring to fig. 7B, after the second patterning process, the top surface of the first dielectric layer 106 is lower than the top surface of the substrate 102, and the bottom surface of the bit line contact structure 122 is higher than the top surface of the first dielectric layer 106. In this way, it is ensured that adjacent bit line contact structures 122 are completely separated from each other without shorting.
Referring to fig. 1, 8A and 8B, an insulating liner 152 is conformally formed overlying the substrate 102, the bit line contact structures 122, the bit lines 132 and the second dielectric layer 134. Then, a second insulating layer 154 is conformally formed over the insulating liner 152 and fills the recess 155. The materials of the insulating liner 152 and the second insulating layer 154 may each independently comprise an oxide, nitride, oxynitride, carbide, other suitable insulating material, or a combination thereof. In this embodiment, the insulating liner 152 is silicon oxynitride and the second insulating layer 154 is silicon nitride.
Referring to fig. 1, 9A and 9B, an etching process is performed to remove a portion of the second insulating layer 154 and expose the insulating liner 152. In this etching process, the removal rate of the second insulating layer 154 is much greater than the removal rate of the insulating liner 152. Accordingly, the second insulating layer 154 outside the recess 155 can be removed while maintaining the shape of the insulating liner 152. After this etching process, the second insulating layer 154 still fills the recesses 155 to ensure that adjacent bit line contact structures 122 are insulated from each other.
Referring to fig. 1, 10A and 10B, an etching back process is performed to remove the first insulating layer 108 and remove portions of the insulating liner 152 and the second insulating layer 154. After this etch-back process, the second dielectric layer 134 is exposed and a portion of the second insulating layer 154 protrudes upward from the recess 155. Sidewall spacers 162 are then conformally formed on the sidewalls of the insulating liner 152. Next, a gap filling layer 164 is formed to cover the substrate 102 and fill the gap (or trench) between the insulating liner layers 152. Next, a planarization process is performed to level the top surfaces of the insulating liner 152, the sidewall spacers 162, and the gap fill layer 164 with each other.
The sidewall spacer 162 may be a single layer structure formed of a single material or a multi-layer structure formed of a plurality of different materials. The material of the sidewall spacers 162 may include oxide, nitride, oxynitride, other suitable dielectric material, or a combination thereof. In the present embodiment, the sidewall spacer 162 is a single-layer structure formed of silicon oxide. The spin-on fabrication process may be used to apply a relatively fluid precursor to the substrate 102. Thereafter, the precursor is cured using light or heat energy to form the gap-fill layer 164. The material of gap fill layer 164 may include an oxide, other suitable dielectric material, or a combination thereof. In this embodiment, the gap filling layer 164 is spin-on glass. Thereafter, other prior art manufacturing processes may be performed to complete the DRAM 100, which will not be described in detail herein.
In the method for manufacturing the dram 100 provided in the present embodiment, a plurality of parallel bit line contact trenches are formed, and then the bit line contact structures are formed in a self-aligned manner at the intersection positions of the bit line contact trenches and the bit lines. Such a method can significantly improve the yield of the memory device and can reduce the complexity of the manufacturing process and the production cost.
More particularly, in some prior art methods, a plurality of discontinuous bit line contact holes are typically formed at predetermined locations, and then a conductive material is filled into the bit line contact holes to form a bit line contact structure. However, the bit line contact holes are small in size and densely arranged. Positional deviation or dimensional variation of the bit line contact holes easily occurs in the exposure step of the photolithography manufacturing process. If the size of the bit line contact hole is too large, adjacent bit line contact holes are easily connected to each other. This results in shorting between adjacent bit line contact structures, thereby reducing the yield of the memory device. On the other hand, if the size of the bit line contact hole is too small to be fully exposed, the bit line contact structure may not be formed, or the formed bit line contact structure may not directly contact the active region of the substrate (i.e., the bit line contact structure fails), which also reduces the yield of the memory device. In other words, if such a conventional method is adopted, the yield of the memory device is easily reduced.
In other conventional methods, a plurality of discontinuous bit line contact holes are formed by using a double exposure method. More specifically, in this conventional method, a first exposure step is performed first to form a first trench extending along a first direction. Then, a second exposure is performed to a second trench extending along a second direction (e.g., the second direction is generally perpendicular to the first direction). And then, performing an etching manufacturing process to form a bit line contact hole at the intersection position of the first groove and the second groove. However, this prior art method requires at least two photomasks to form a plurality of discrete bit line contact holes. Therefore, compared with the method for manufacturing the DRAM according to the embodiment of the present invention, if the conventional method is adopted, at least one photomask must be added. In this way, the complexity of the manufacturing process and the production cost will be increased.
In the method for fabricating the DRAM according to the embodiment of the present invention, a plurality of parallel bit line contact trenches 115 are formed, and the first conductive material 122 is filled into the bit line contact trenches 115. The position and size of the bit line contact trench 115 are easier to control accurately than the hole-shaped bit line contact hole. Furthermore, it is easier to fill the first conductive material 122 in the bit line contact trench 115 than in the hole-shaped bit line contact hole. Therefore, the position and size of the first conductive material 122 can be precisely controlled. Thus, the above-mentioned problems of short circuit or failure can be avoided. In other words, the method for manufacturing the dynamic random access memory provided by the embodiment of the invention can obviously improve the yield of the memory device.
In addition, in the method for manufacturing the dram according to the embodiment of the present invention, the second conductive material (i.e., the third conductive layer 132A and/or the fourth conductive layer 132B of the bit line 132) is formed on the first conductive material 122 having the specific shape (i.e., the shape corresponding to the bit line contact trench 115), and then the first conductive material and the second conductive material are etched simultaneously in the second patterning process. In other words, the method for manufacturing the DRAM according to the present embodiment of the invention can simultaneously form the bit line 132 and the bit line contact structure 122 by using only one photomask. Therefore, compared with the prior art, the method for manufacturing the dynamic random access memory provided by the embodiment of the invention can reduce the use of one photomask, thereby reducing the complexity of the manufacturing process and the production cost.
Referring to fig. 1, 10A and 10B, in some embodiments, a dynamic random access memory 100 is provided. The DRAM 100 includes a buried word line 110, a first dielectric layer 106, a bit line 132, and a bit line contact structure 122. The buried word line 110 and the first dielectric layer 106 are formed in the word line trench of the substrate 102. The first dielectric layer 106 is formed over the buried word line 110 and directly contacts the buried word line 110. Bit lines 132 are formed on the substrate 102. The bit line contact structure 122 is formed on the substrate 102 and is located between the bit line 132 and the substrate 102. The top surface of the first dielectric layer 106 is lower than the top surface of the substrate 102, and the bottom surface of the bit line contact structure 122 is higher than the top surface of the first dielectric layer 106.
Referring to fig. 3B, after the first patterning process, the top surface of the first dielectric layer 106 is lower than the top surface of the substrate 102. I.e., the surface of the substrate 102 is exposed. This allows the subsequently formed bit line contact structure 122 to directly contact the active region 105 of the substrate 102, thereby further improving the yield of the memory device.
Fig. 1 is a schematic top view of a dram 100 according to some embodiments of the present invention. To simplify the drawing, only the active region 105, the buried word line 110, the bit line contact trench 115, the bit line 132, and the bit line contact structure 122 are illustrated in fig. 1. In fig. 1, the active region 105 is substantially a partial region of the substrate 102 (e.g., a region doped with P-type dopants or N-type dopants), and thus the active region 105 is depicted in dashed lines. In fig. 1, the bit line contact trench 115 does not exist in the structure of fig. 10A or 10B, and therefore, the bit line contact trench 115 is also drawn in dotted lines. In fig. 1, the bit line contact structure 122 is sandwiched between the bit line 132 and the substrate 102, and thus, in order to easily identify the bit line contact structure 122, the position and shape of the bit line contact structure 122 are indicated by dotted lines.
Referring to fig. 1, a plurality of buried word lines 110 are parallel to each other and extend along a first direction (e.g., in a vertical direction in fig. 1). The plurality of bit lines 132 are parallel to each other and extend along a second direction perpendicular to the first direction. The plurality of bit line contact trenches 115 are parallel to each other and extend along the third direction. The third direction is different from the first direction and the second direction. Accordingly, the bit line contact structure 122 is parallelogram in the upper view, as depicted in fig. 1. The plurality of active regions 105 are parallel to each other and extend along the fourth direction. The fourth direction is different from the first direction, the second direction and the third direction. In order to increase the arrangement density of the bit line contact structures 122, an angle between the third direction and the second direction may be set to a proper range. In some embodiments, the third direction and the second direction include an included angle therebetween, and the included angle is an acute angle of 10 degrees to 80 degrees. In other embodiments, the included angle is an acute angle of 30 degrees to 60 degrees.
In summary, in the method for manufacturing the dynamic random access memory according to the embodiment of the invention, the position and the size of the bit line contact trench 115 can be precisely controlled, so that the short circuit or the failure of the bit line contact structure can be avoided. Therefore, the manufacturing method of the dynamic random access memory provided by the embodiment of the invention can obviously improve the yield of the memory device. In addition, in the method for manufacturing the dynamic random access memory provided by the embodiment of the invention, the bit line and the bit line contact structure can be formed simultaneously in the same patterning manufacturing process. Therefore, the use of one photomask can be reduced, and the complexity of the manufacturing process and the production cost are further reduced. In addition, the manufacturing method of the DRAM according to the embodiment of the present invention can be easily integrated into the existing manufacturing process without additional replacement or modification of the production equipment.
Although the present invention has been described with respect to the preferred embodiments, it should be understood by those skilled in the art that the present invention is not limited thereto, and that various changes and modifications may be made without departing from the spirit and scope of the present invention as defined by the appended claims.

Claims (10)

1. A dynamic random access memory, comprising:
a buried word line formed in a word line trench of a substrate, wherein the buried word line extends along a first direction;
a first dielectric layer formed in the word line trench, wherein the first dielectric layer is located over the buried word line and directly contacts the buried word line;
a bit line formed on the substrate, wherein the bit line extends along a second direction perpendicular to the first direction;
a bit line contact structure formed on the substrate, wherein the bit line contact structure is located between the bit line and the substrate, wherein a bottom surface of the bit line contact structure is higher than a top surface of the first dielectric layer;
the top surface of the first dielectric layer is lower than a top surface of the substrate.
2. The dynamic random access memory of claim 1, wherein the bit line contact structure is parallelogram in top view.
3. The dynamic random access memory of claim 1, further comprising:
a recess formed in the substrate and adjacent to the bit line, wherein the recess has a stepped cross-sectional profile; and
and a second insulating layer filled in the concave part.
4. The dynamic random access memory of claim 3, wherein a bottom surface of said recess is lower than said bottom surface of said bit line contact structure.
5. A method of manufacturing a dynamic random access memory, comprising:
forming an embedded word line in a word line trench of a substrate, wherein the embedded word line extends along a first direction;
forming a first dielectric layer in the word line trench, wherein the first dielectric layer is located over the buried word line and directly contacts the buried word line;
forming a bit line on the substrate, wherein the bit line extends along a second direction perpendicular to the first direction;
forming a bit line contact structure on the substrate, wherein the bit line contact structure is located between the bit line and the substrate, and wherein a bottom surface of the bit line contact structure is higher than a top surface of the first dielectric layer;
the top surface of the first dielectric layer is lower than a top surface of the substrate.
6. The method of claim 5, wherein forming the bit line contact structure comprises:
forming a first insulating layer on the substrate;
forming a protective layer on the first insulating layer;
performing a first patterning process to form a bit line contact trench in the first insulating layer and the protective layer, wherein the bit line contact trench extends along a third direction, and the third direction is different from the first direction and the second direction;
forming a first conductive material on the substrate and filling the bit line contact trench; and
a second patterning process is performed to partially remove the first conductive material and form the bit line contact structure at a location where the bit line contact trench meets the bit line.
7. The method of manufacturing a dynamic random access memory of claim 6, further comprising:
forming a second conductive material over the first conductive material; and
the second patterning process is performed to simultaneously form the bit line and the bit line contact structure, wherein the bit line comprises the second conductive material and the bit line contact structure comprises the first conductive material.
8. The method of claim 6, wherein the third direction and the second direction include an included angle therebetween, and the included angle is an acute angle of 10 degrees to 80 degrees.
9. The method of manufacturing a dynamic random access memory of claim 6, further comprising:
after forming the first conductive material, performing an etching manufacturing process to remove a portion of the first conductive material;
wherein a top surface of the first conductive material is lower than a top surface of the first insulating layer after the etching process is performed.
10. The method of manufacturing a dynamic random access memory of claim 6, further comprising:
forming a recess in the substrate adjacent to the bit line after performing the second patterning process, wherein the recess has a stepped profile; and
forming a second insulating layer to fill the recess.
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