CN111584346B - GaN device with heat sink structure and preparation method thereof - Google Patents

GaN device with heat sink structure and preparation method thereof Download PDF

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CN111584346B
CN111584346B CN202010469000.1A CN202010469000A CN111584346B CN 111584346 B CN111584346 B CN 111584346B CN 202010469000 A CN202010469000 A CN 202010469000A CN 111584346 B CN111584346 B CN 111584346B
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layer
heat sink
sic substrate
gan device
sink structure
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CN111584346A (en
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莫炯炯
王志宇
陈华
刘家瑞
郁发新
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Zhejiang University ZJU
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Zhejiang University ZJU
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02378—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3736—Metallic materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface

Abstract

The invention provides a GaN device with a heat sink structure and a preparation method thereof, wherein the device sequentially comprises: the device comprises a Cu heat sink substrate, a CuIn intermetallic compound layer, a seed layer, an adhesion layer, a SiC substrate layer and a functional layer. Through a cracking process, a defect layer is formed in the SiC substrate layer through ion implantation, then the SiC substrate layer is cracked at the defect layer under the stress action of the stress induction generation layer, the SiC substrate can be recycled while the substrate thinning effect is achieved, the process cost is saved, the thinning thickness of the SiC substrate layer can be determined through the energy and the dosage of the ion implantation, the process is simple, and impurity particles introduced in the existing grinding process thinning process are avoided; in addition, the Cu/In alloy bonding is utilized, the risk of functional layer cracking In the bonding process of the heat sink structure is relieved, and the process reliability is high.

Description

GaN device with heat sink structure and preparation method thereof
Technical Field
The invention belongs to the technical field of semiconductor devices, and particularly relates to a GaN device with a heat sink structure and a preparation method thereof.
Background
As a prominent representative of the third generation of semiconductors, GaN (gallium nitride) has a forbidden band width at room temperature of 3.45eV, which is much larger than those of Si and GaAs, so that the breakdown strength ratio of the electric field is an order of magnitude larger, and the GaN (gallium nitride) is very suitable for manufacturing high-voltage and high-power devices. Besides the advantage of large forbidden band width, GaN also has high electronic saturation velocity and thermal conductivity, so that the GaN is very suitable for the occasions of microwave/millimeter wave high-power application. GaN power electronic switching devices, AlGaN/GaN heterojunction high electron mobility transistors HEMTs and GaN MMIC Monolithic Microwave Integrated Circuits (MMICs) have shown unique advantages in high temperature devices and high power Microwave devices, and pursuing high frequency, high voltage, and high power of the devices has attracted much research.
However, the temperature rise during the operation of GaN devices can affect the device performance, especially for high power GaN HEMT devices, the self-heating effect can cause heat to rapidly accumulate in the center of the active region of the device, causing the device performance to deteriorate and fail. It is therefore important to dissipate heat in a timely manner. In order to improve the high-temperature reliability of the device and reduce the thermal resistance of the device, the high-power GaN device usually adopts a back thinning structure and then is additionally provided with a high-thermal-conductivity heat sink structure to reduce the thermal resistance of the device, and a substrate needs to be thinned in the preparation process.
Disclosure of Invention
In view of the above drawbacks of the prior art, an object of the present invention is to provide a GaN device with a heat sink structure and a method for manufacturing the same, which are used to solve the problems of high cost and material waste of the CMP process for thinning a substrate when forming the heat sink structure of the GaN device in the prior art.
To achieve the above and other related objects, the present invention provides a method for fabricating a GaN device having a heat sink structure, the method comprising:
providing a GaN device structure, wherein the GaN device structure sequentially comprises a SiC substrate layer and a functional layer;
providing a temporary bonding sheet and bonding the functional layer with the temporary bonding sheet;
performing ion implantation on the back of the SiC substrate layer to form a defect layer in the SiC substrate layer;
depositing a stress induction generating layer on the back of the SiC substrate layer, stopping the deposition of the stress induction generating layer when the stress generated by the stress induction generating layer causes the SiC substrate layer to split from the defect layer and generate a splitting opening, and then inserting a spacer from the splitting opening to finish the thinning of the SiC substrate layer;
carrying out planarization treatment on the back of the thinned SiC substrate layer;
forming an adhesion layer, a seed layer and a Cu layer on the back of the SiC substrate layer after the planarization treatment in sequence;
providing a Cu heat sink substrate, and forming an In layer on the Cu heat sink substrate;
and bonding the In layer of the Cu heat sink substrate and the Cu layer of the SiC substrate layer, and forming a CuIn intermetallic compound layer on a bonding surface, thereby forming the GaN device with a heat sink structure.
Optionally, the functional layer is a HEMT device layer; the step of removing the temporary bonding sheet is further included after the GaN device with the heat sink structure is formed.
Optionally, the implanted ions adopted when ion implantation is performed on the back surface of the SiC substrate layer are protons.
Optionally, the specific step of depositing the stress-inducing generation layer on the back surface of the SiC substrate layer includes:
depositing a Ti layer and a first Ni layer on the back of the SiC substrate layer by adopting a sputtering process;
and depositing a second Ni layer on the first Ni layer by adopting an electroplating process, and stopping the deposition of the second Ni layer when the SiC substrate layer is split from the defect layer to generate the splitting gap.
Optionally, a sputtering process is adopted to form the adhesion layer and the seed layer, the material of the adhesion layer is Ti, and the material of the seed layer is Au or Cu; and forming the Cu layer by adopting an electroplating process.
Optionally, the thickness of the adhesion layer is between 10nm and 50nm, the thickness of the seed layer is between 50nm and 200nm, and the thickness of the Cu layer is between 45 μm and 55 μm.
Optionally, before the In layer is formed on the Cu heat sink substrate, a step of performing an electropolishing process on the Cu heat sink substrate is further included, so that the surface roughness of the Cu heat sink substrate is between 100nm and 200 nm.
Optionally, forming the In layer by using a thermal evaporation process; the specific steps of bonding the In layer and the Cu layer comprise bonding the Cu layer and the melted In layer for 5-10 min at the temperature of 200-250 ℃, and then cooling to 145-155 ℃ for bonding for 70-90 min.
The invention also provides a GaN device with a heat sink structure, the device comprising in order: the device comprises a Cu heat sink substrate, a CuIn intermetallic compound layer, a seed layer, an adhesion layer, a SiC substrate layer and a functional layer.
Optionally, the CuIn intermetallic compound layer comprises Cu11In9Intermetallic compound layer and Cu9In4An intermetallic compound layer.
As described above, according to the GaN device with a heat sink structure and the preparation method thereof, the defect layer is formed in the SiC substrate layer by ion implantation through the cracking process, and then the SiC substrate layer is cracked at the defect layer under the stress action of the stress induction generation layer, so that the effect of substrate thinning is achieved, and the SiC substrate can be recovered, thereby saving the process cost, the thickness of the thinned SiC substrate layer can be determined by the energy and dosage of ion implantation, the process is simple, and the impurity particles introduced in the existing thinning process adopting the grinding process are avoided; in addition, the Cu/In alloy bonding is utilized, the risk of functional layer cracking In the bonding process of the heat sink structure is relieved, and the process reliability is high.
Drawings
Fig. 1 is a process flow diagram of a method for manufacturing a GaN device with a heat sink structure according to a first embodiment of the present invention.
Fig. 2 is a schematic structural diagram of step S1 in the method for manufacturing a GaN device with a heat sink structure according to the first embodiment of the present invention.
Fig. 3 is a schematic structural diagram of step S2 in the method for manufacturing a GaN device with a heat sink structure according to the first embodiment of the present invention.
Fig. 4 is a schematic structural view showing the ion implantation direction in step S3 in the method for manufacturing a GaN device with a heat sink structure according to the first embodiment of the present invention.
Fig. 5 is a schematic structural view showing the formation of a defect layer in step S3 in the method for manufacturing a GaN device having a heat sink structure according to the first embodiment of the present invention.
Fig. 6 is a schematic structural view illustrating the formation of cracks in step S4 in the method for manufacturing a GaN device with a heat sink structure according to the first embodiment of the present invention.
Fig. 7 is a schematic structural view showing the spacer insertion step in step S4 in the method for manufacturing a GaN device with a heat sink structure according to the first embodiment of the present invention.
Fig. 8 is a schematic structural view of the step S6 in the method for manufacturing a GaN device with a heat sink structure according to the first embodiment of the present invention.
Fig. 9 is a schematic structural view showing the step S7 in the method for manufacturing a GaN device with a heat sink structure according to the first embodiment of the present invention.
Fig. 10 is a schematic structural view showing a bonding between the In layer and the Cu layer In step S8 In the method for manufacturing a GaN device having a heat sink structure according to the first embodiment of the present invention.
Fig. 11 is a schematic structural view showing a structure formed by bonding an In layer and a Cu layer In step S8 In the method for manufacturing a GaN device with a heat sink structure according to the first embodiment of the present invention, and fig. 11 is a schematic structural view showing a CuIn intermetallic compound layer formed after bonding the In layer and the Cu layer, where fig. 11 also shows a GaN device with a heat sink structure according to the second embodiment of the present invention.
Description of the element reference numerals
100 GaN device structure
101 SiC substrate layer
102 functional layer
103 temporary bonding sheet
104 defective layer
105 stress induction generating layer
106 Ti layer
107 first Ni layer
108 second Ni layer
109 split mouth
110 spacer
111 adhesive layer
112 seed layer
113 Cu layer
114 Cu heat sink substrate
115 In layer
116 CuIn intermetallic compound layer
S1-S8
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 11. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
Example one
The embodiment provides a preparation method of a GaN device with a heat sink structure, which comprises the steps of forming a defect layer in a SiC substrate layer by ion implantation through a cracking process, then cracking the SiC substrate layer at the defect layer under the stress action of a stress induction generation layer, achieving the effect of substrate thinning, and simultaneously recovering the SiC substrate, so that the process cost is saved, the thickness of the thinned SiC substrate layer can be determined by the energy and the dosage of ion implantation, the process is simple, and impurity particles introduced in the thinning process of the existing grinding process are avoided; in addition, the Cu/In alloy bonding is utilized, the risk of functional layer cracking In the bonding process of the heat sink structure is relieved, and the process reliability is high.
As shown in fig. 1 to 11, the preparation method includes the steps of:
as shown in fig. 1 and 2, step S1 is performed first to provide a GaN device structure 100, where the GaN device structure 100 includes a SiC substrate layer 101 and a functional layer 102 in this order.
As an example, the functional layer 102 is a device layer formed on the SiC substrate layer 101, and has a certain electrical function, and the functional layer 102 may be any existing functional device layer, especially a high-heat-production functional device with high power, high mobility, and the like. These high power, high mobility, and other functional devices generally need to form a heat dissipation structure to ensure the performance of the device. In this embodiment, the functional layer 102 is selected to be a HEMT device structure completed by a conventional process, and includes a source electrode, a gate electrode and a drain electrode (not shown in the figure).
As shown in fig. 1 and 3, step S2 is then performed to provide a temporary bonding sheet 103, and bond the functional layer 102 and the temporary bonding sheet 103.
The temporary bonding sheet 103 is used for temporarily fixing the functional layer 102 and the SiC substrate layer 101 during a process of forming a heat sink structure, so as to prevent the functional layer 102 from being damaged during the process of forming the heat sink structure. The temporary bonding pad 103 may be made of any suitable temporary bonding material, such as glass, sapphire, etc. The thickness of the temporary bond sheet 103 may be set according to specific needs. After the functional layer 102 is bonded with the temporary bonding sheet 103, the functional layer 102 is fixed, the back surface of the SiC substrate layer 101 is exposed, and then the formation of a heat sink structure can be realized by performing processes such as thinning and bonding on the back surface of the SiC substrate layer 101.
As shown in fig. 1, 4 and 5, step S3 is performed to implant ions into the back surface of the SiC substrate layer 101 (as shown in fig. 4, the arrows indicate the direction of the ion implantation) so as to form a defect layer 104 in the SiC substrate layer 101 (as shown in fig. 5).
As an example, any suitable ion implantation on the back side of SiC substrate layer 101 can be usedThe implantation of ions in the SiC substrate layer 101 may be performed as long as the defect layer 104 can be formed in the SiC substrate layer, and parameters such as the ion implantation energy and the ion implantation dose may be determined according to requirements such as the depth of the defect layer 104 to be formed. In this embodiment, protons are selected as the implanted ions in the ion implantation process, the energy of the ion implantation is 1MeV, and the dose of the ion implantation is 1 × 1017cm-2The formation of the defect layer 104 under these parameters ensures that the subsequently formed stress-inducing generation layer causes the SiC substrate layer 101 to split at the defect layer 104.
As shown in fig. 1, 6 and 7, step S4 is performed to deposit a stress-inducing layer 105 on the back surface of the SiC substrate layer 101, and when the stress generated by the stress-inducing layer 105 causes the SiC substrate layer 101 to split from the defect layer 104 to generate a split opening 109 (as shown in fig. 6), the deposition of the stress-inducing layer 105 is stopped, and then a spacer 110 is inserted from the split opening 109 to complete the thinning of the SiC substrate layer 101 (as shown in fig. 7).
The stress induction generation layer 105 generates tensile stress, the tensile stress generated in the process of depositing and forming the stress induction generation layer 105 is gradually increased, when the tensile stress is increased to a certain value, the crack starts at the edge of the defect layer 104 to generate a crack opening 109, at this time, the deposition of the stress induction generation layer 105 is stopped, and the spacer 110 is inserted into the crack opening 109 by means of external force, namely the spacer 110 made of a harder material, so as to complete the crack of the whole defect layer. The thinning of the SiC substrate layer 101 is realized, the process is simple, the thinned thickness of the SiC substrate layer 101 can be determined by the energy and the dosage of ion implantation, the process control is convenient, and impurity particles introduced in the conventional grinding process thinning process can be avoided; in addition, the separated SiC substrate layer 101 can be recycled, and the process cost is saved.
In this embodiment, the stress-inducing layer 105 is selected as a composite layer, and the deposition step specifically includes:
depositing a Ti layer 106 and a first Ni layer 107 on the back surface of the SiC substrate layer 101 by adopting a sputtering process;
depositing a second Ni layer 108 on the first Ni layer 107 by an electroplating process, and stopping the deposition of the second Ni layer 108 when the SiC substrate layer 101 is split from the defect layer 104 to generate the splitting gap 109.
As an example, the spacer 110 serves to split the defect layer 104 through the splitting gap 109, so the material of the spacer 110 may be selected according to specific needs as long as the defect layer 104 can be split, for example, the spacer 110 may be a semiconductor material, a sapphire material, or the like.
As shown in fig. 1, step S5 is performed next, and planarization processing is performed on the back surface of the thinned SiC substrate layer 101. To improve the surface flatness of the SiC substrate layer 101. In this embodiment, a CMP process is selected to perform planarization processing on the back surface of the SiC substrate layer 101, so as to remove at least a residual defect layer on the back surface of the SiC substrate layer 101.
As shown in fig. 1 and 8, step S6 is performed to sequentially form an adhesion layer 111, a seed layer 112, and a Cu layer 113 on the back surface of the SiC substrate layer 101 after the planarization process. The adhesion layer 111 is used for improving the adhesion performance between the SiC substrate layer 101 and the seed layer 112, and the seed layer 112 is used for improving the growth quality of the Cu layer 113. On one hand, the Cu layer 113 formed on the back surface of the SiC substrate layer 101 can improve the mechanical strength of the whole structure connected with the Cu layer, so that the damage of subsequent bonding pressure to the functional layer 102 is reduced; on the other hand, the Cu layer 113 can ensure high thermal conductivity of bonding, copper-indium bonding can not only improve heat dissipation, but also resist functional layer damage caused by mismatch of thermal expansion (CTE) of the functional layer at a higher operating temperature through compressive stress generated during bonding, thereby improving reliability of the functional layer, and in the absence of the Cu layer 113, wrinkles and cracks are likely to occur in the functional layer after a subsequent bonding process, and the cracks are due to a large stress gradient existing in a stack of the grown functional layer.
As an example, a sputtering process is adopted to form the adhesion layer 111 and the seed layer 112, the material of the adhesion layer 111 is Ti, and the material of the seed layer 112 is Au or Cu; the Cu layer 113 is formed using an electroplating process. In this embodiment, the thickness of the adhesion layer 111 is selected to be between 10nm and 50nm, the thickness of the seed layer 112 is selected to be between 50nm and 200nm, and the thickness of the Cu layer 113 is selected to be between 45 μm and 55 μm.
As shown In fig. 1 and 9, step S7 is performed to provide a Cu heat sink substrate 114, and an In layer 115 is formed on the Cu heat sink substrate 114.
By way of example, the Cu heat sink substrate 114 is typically selected to have a thickness of about 2mm, and the Cu heat sink substrate 114 is planarized, for example, by electropolishing the Cu heat sink substrate 114 using CMP, to reduce the surface roughness from about 20 μm to between 100nm and 200 nm.
As an example, the In layer 115 may be deposited using a thermal evaporation process. The deposition thickness of the In layer 115 is about 1 μm.
As shown In fig. 1, 10 and 11, step S8 is finally performed, In which the In layer 115 of the Cu heatsink substrate 114 is bonded to the Cu layer 113 of the SiC substrate layer 101 (as shown In fig. 10), and a CuIn intermetallic compound layer 116 is formed on the bonding surface (as shown In fig. 11), thereby forming a GaN device with a heatsink structure.
As an example, the specific step of bonding and forming the CuIn intermetallic compound layer 116 includes first bonding the Cu layer 113 of the SiC substrate layer 101 to the Cu heat sink substrate 114 through the melted In layer 115, under the condition that the Cu layer 113 and the melted In layer 115 are bonded for 5min to 10min at a temperature between 200 ℃ and 250 ℃; then, the temperature is reduced to 145-155 ℃, and the bonding is continued for 70-90 min, so that the Cu layer 113 and the In layer 115 form a metal alloy layer, i.e., a CuIn intermetallic compound layer 116. Firstly adopting high-temperature bonding and then adopting low-temperature bonding, because Cu is formed when the bonding temperature is between 200 and 250 DEG C11In9The melting point of the alloy will be higher, being 310 c, for the intermetallic layer. In addition, low temperature annealing for 70-90 min will produce Cu rich in Cu9In4The compound is more beneficial to heat dissipation.
As an example, the temporary bonding sheet 103 may be removed as needed after the GaN device having the heat sink structure is formed.
Example two
This embodiment provides a GaN device with a heat sink structure, which can be fabricated by the fabrication method of the first embodiment, but is not limited to the fabrication method of the first embodiment, as long as the GaN device with a heat sink structure can be formed. For the beneficial effects of the GaN device with the heat sink structure, please refer to embodiment one, which will not be described in detail below.
As shown in fig. 11, the GaN device having a heat sink structure includes: a Cu heatsink substrate 114, a CuIn intermetallic compound layer 116, a seed layer 112, an adhesion layer 111, a SiC substrate layer 101, and a functional layer 102.
As an example, the CuIn intermetallic layer 116 includes Cu11In9Intermetallic compound layer and Cu9In4An intermetallic compound layer.
In summary, the invention provides a GaN device with a heat sink structure and a preparation method thereof, wherein a defect layer is formed in a SiC substrate layer by ion implantation through a cracking process, and then the SiC substrate layer is cracked at the defect layer under the stress action of a stress induction generation layer, so that the effect of substrate thinning is achieved, and the SiC substrate can be recovered, thereby saving the process cost, the thickness of the thinned SiC substrate layer can be determined by the energy and dosage of ion implantation, the process is simple, and the impurity particles introduced in the existing thinning process by adopting a grinding process are avoided; in addition, the Cu/In alloy bonding is utilized, the risk of functional layer cracking In the bonding process of the heat sink structure is relieved, and the process reliability is high. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (8)

1. A preparation method of a GaN device with a heat sink structure is characterized by comprising the following steps:
providing a GaN device structure, wherein the GaN device structure sequentially comprises a SiC substrate layer and a functional layer;
providing a temporary bonding sheet and bonding the functional layer with the temporary bonding sheet;
performing ion implantation on the back of the SiC substrate layer to form a defect layer in the SiC substrate layer;
depositing a stress induction generating layer on the back of the SiC substrate layer, stopping the deposition of the stress induction generating layer when the stress generated by the stress induction generating layer causes the SiC substrate layer to split from the defect layer and generate a splitting opening, and then inserting a spacer from the splitting opening to finish the thinning of the SiC substrate layer;
carrying out planarization treatment on the back of the thinned SiC substrate layer;
forming an adhesion layer, a seed layer and a Cu layer on the back of the SiC substrate layer after the planarization treatment in sequence;
providing a Cu heat sink substrate, and forming an In layer on the Cu heat sink substrate;
and bonding the In layer of the Cu heat sink substrate and the Cu layer of the SiC substrate layer, and forming a CuIn intermetallic compound layer on a bonding surface, thereby forming the GaN device with a heat sink structure.
2. The method of claim 1, wherein the GaN device has a heat sink structure, the method comprises: the functional layer is an HEMT device layer; the step of removing the temporary bonding sheet is further included after the GaN device with the heat sink structure is formed.
3. The method of claim 1, wherein the GaN device has a heat sink structure, the method comprises: and the injected ions adopted when ion injection is carried out on the back surface of the SiC substrate layer are protons.
4. The method of claim 1, wherein the step of depositing the stress-inducing generation layer on the back of the SiC substrate layer comprises:
depositing a Ti layer and a first Ni layer on the back of the SiC substrate layer by adopting a sputtering process;
and depositing a second Ni layer on the first Ni layer by adopting an electroplating process, and stopping the deposition of the second Ni layer when the SiC substrate layer is split from the defect layer to generate the splitting gap.
5. The method of claim 1, wherein the GaN device has a heat sink structure, the method comprises: forming the adhesion layer and the seed layer by adopting a sputtering process, wherein the material of the adhesion layer is Ti, and the material of the seed layer is Au or Cu; and forming the Cu layer by adopting an electroplating process.
6. The method of claim 5, wherein the GaN device has a heat sink structure, the method comprises: the thickness of the adhesion layer is between 10nm and 50nm, the thickness of the seed layer is between 50nm and 200nm, and the thickness of the Cu layer is between 45 mu m and 55 mu m.
7. The method of claim 1, wherein the GaN device has a heat sink structure, the method comprises: before the In layer is formed on the Cu heat sink substrate, the method also comprises the step of carrying out electropolishing treatment on the Cu heat sink substrate so as to ensure that the surface roughness of the Cu heat sink substrate is between 100nm and 200 nm.
8. The method of claim 1, wherein the GaN device has a heat sink structure, the method comprises: forming the In layer by adopting a thermal evaporation process; the specific steps of bonding the In layer and the Cu layer comprise bonding the Cu layer and the melted In layer for 5-10 min at the temperature of 200-250 ℃, and then cooling to 145-155 ℃ for bonding for 70-90 min.
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