CN117690792A - GaN power device and preparation method thereof - Google Patents
GaN power device and preparation method thereof Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 91
- 239000000463 material Substances 0.000 claims abstract description 71
- 229910052594 sapphire Inorganic materials 0.000 claims abstract description 33
- 239000010980 sapphire Substances 0.000 claims abstract description 33
- 230000005496 eutectics Effects 0.000 claims abstract description 12
- 238000007731 hot pressing Methods 0.000 claims abstract description 8
- 238000002161 passivation Methods 0.000 claims description 79
- 229910052751 metal Inorganic materials 0.000 claims description 57
- 239000002184 metal Substances 0.000 claims description 57
- 238000000151 deposition Methods 0.000 claims description 34
- 238000003466 welding Methods 0.000 claims description 30
- 239000011368 organic material Substances 0.000 claims description 29
- 238000000034 method Methods 0.000 claims description 26
- 229910002704 AlGaN Inorganic materials 0.000 claims description 24
- 230000004888 barrier function Effects 0.000 claims description 24
- 238000005530 etching Methods 0.000 claims description 22
- 238000004519 manufacturing process Methods 0.000 claims description 20
- 238000004140 cleaning Methods 0.000 claims description 9
- 229910000859 α-Fe Inorganic materials 0.000 claims description 9
- 238000002955 isolation Methods 0.000 claims description 7
- 229910000679 solder Inorganic materials 0.000 claims description 7
- 229910052709 silver Inorganic materials 0.000 claims description 6
- 239000011248 coating agent Substances 0.000 claims description 5
- 238000000576 coating method Methods 0.000 claims description 5
- 229920002120 photoresistant polymer Polymers 0.000 claims description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- QJVKUMXDEUEQLH-UHFFFAOYSA-N [B].[Fe].[Nd] Chemical compound [B].[Fe].[Nd] QJVKUMXDEUEQLH-UHFFFAOYSA-N 0.000 claims description 3
- SFBMLGJOOALENT-UHFFFAOYSA-N [Co].[Ni].[Nd] Chemical compound [Co].[Ni].[Nd] SFBMLGJOOALENT-UHFFFAOYSA-N 0.000 claims description 3
- 229910052799 carbon Inorganic materials 0.000 claims description 3
- KPLQYGBQNPPQGA-UHFFFAOYSA-N cobalt samarium Chemical compound [Co].[Sm] KPLQYGBQNPPQGA-UHFFFAOYSA-N 0.000 claims description 3
- 229910003460 diamond Inorganic materials 0.000 claims description 3
- 239000010432 diamond Substances 0.000 claims description 3
- 229910052738 indium Inorganic materials 0.000 claims description 3
- 229910001172 neodymium magnet Inorganic materials 0.000 claims description 3
- 239000012188 paraffin wax Substances 0.000 claims description 3
- 229920005989 resin Polymers 0.000 claims description 3
- 239000011347 resin Substances 0.000 claims description 3
- 229910000938 samarium–cobalt magnet Inorganic materials 0.000 claims description 3
- 229920005992 thermoplastic resin Polymers 0.000 claims description 3
- 229920001187 thermosetting polymer Polymers 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- LKJPSUCKSLORMF-UHFFFAOYSA-N Monolinuron Chemical compound CON(C)C(=O)NC1=CC=C(Cl)C=C1 LKJPSUCKSLORMF-UHFFFAOYSA-N 0.000 claims description 2
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 2
- 238000001746 injection moulding Methods 0.000 claims description 2
- 238000009825 accumulation Methods 0.000 abstract description 6
- 230000005540 biological transmission Effects 0.000 abstract description 5
- 238000000926 separation method Methods 0.000 abstract description 4
- 230000001678 irradiating effect Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 9
- 238000000231 atomic layer deposition Methods 0.000 description 6
- 238000000407 epitaxy Methods 0.000 description 6
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 6
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- 230000009471 action Effects 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 239000000243 solution Substances 0.000 description 4
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 3
- 238000005566 electron beam evaporation Methods 0.000 description 3
- 230000017525 heat dissipation Effects 0.000 description 3
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000004299 exfoliation Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 230000005012 migration Effects 0.000 description 2
- 238000013508 migration Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 230000002238 attenuated effect Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000000861 blow drying Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 239000008367 deionised water Substances 0.000 description 1
- 229910021641 deionized water Inorganic materials 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 238000001534 heteroepitaxy Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000005533 two-dimensional electron gas Effects 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Abstract
The invention discloses a preparation method of a GaN power device, which comprises the steps of transferring a sapphire substrate GaN power device wafer onto a magnetic substrate, irradiating a stripping layer between the sapphire and a GaN material in a laser stripping mode to enable low-damage separation between the sapphire and the GaN material, bonding a high-heat-conductivity substrate onto the wafer in a vacuum hot-pressing eutectic mode in a eutectic bonding mode, and finally removing the magnetic substrate in a thermal sliding mode. The preparation method of the GaN power device provided by the invention can increase the heat transmission capacity in the chip, solve the heat accumulation of the GaN near junction region and improve the high-power characteristic and the reliability of the device.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a preparation method of a GaN power device and the GaN power device.
Background
At present, a GaN-based HEMT device with a transverse conducting structure of a Si substrate still faces the factors that restrict the expansion of the application range of a GaN power device, such as high device manufacturing cost, reliability problems and the like. For example, the epitaxy cost is high, gaN epitaxy needs to meet the requirements of large area and low dislocation density, and GaN heteroepitaxy on a Si substrate needs GaN to reach a certain thickness, so that dislocations annihilate each other, and the time cost of epitaxy is increased. For another example, the yield of GaN devices is low, defects exist in the devices due to lattice and thermal expansion coefficient mismatch, unintended doping, damage to materials in the device preparation process and other reasons in the epitaxial GaN process on the Si substrate, the defects of the devices evolve under different working conditions, and hidden hazards of device performance change, namely the reliability problem of the devices, exist. In order to solve the above problems, a sapphire substrate GaN-based HEMT power device becomes another alternative technical route.
The sapphire substrate has high crystal quality, low device preparation cost, suitability for high-voltage power environment and low cost. Compared with a Si substrate, the lattice mismatch of the sapphire and GaN is smaller, the quality of GaN crystals obtained by epitaxy is higher, the thickness of a required stress buffer layer is thinner, the time required by epitaxy is reduced to a great extent, the efficiency of GaN material epitaxy is improved, and the preparation cost of a device is reduced. Although sapphire substrate GaN-based HEMT power devices possess many excellent characteristics, the heat dissipation problem of the devices is still facing. The sapphire substrate has a thermal conductivity much smaller than that of the Si substrate, and the sapphire substrate GaN device has a thermal dissipation capability much smaller than that of the Si substrate GaN device, resulting in degradation of performance and device failure of the power device due to thermal effects in use.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a preparation method of a GaN power device, which can increase the heat transmission capacity of the inside of a chip, solve the heat accumulation of a GaN near junction region and improve the high power characteristic and the reliability of the device.
In order to solve the above problems, the present invention provides a method for manufacturing a GaN power device, comprising the steps of:
s1, sequentially growing a stripping layer, a GaN high-resistance buffer layer, a GaN channel layer, an AlGaN barrier layer and a P-type GaN layer on a sapphire substrate;
s2, etching a mesa isolation structure and a grid mesa structure, and exposing part of the AlGaN barrier layer and the GaN high-resistance buffer layer;
s3, preparing a source electrode and a drain electrode on the surface of the AlGaN barrier layer, depositing a field plate metal layer on the source electrode and the drain electrode to form a metal field plate structure, depositing a gate electrode above the P-type GaN layer, and depositing a welding electrode metal layer on the gate electrode and the metal field plate structure;
s4, coating an organic material buffer layer, and stacking a magnetic substrate on the organic material buffer layer;
s5, stripping the sapphire substrate by laser, and cleaning and removing the exposed stripping layer to expose the GaN high-resistance buffer layer;
s6, depositing a welding material layer on one side of the GaN high-resistance buffer layer, and stacking a high-heat-conductivity substrate on the welding material layer;
s7, removing the magnetic substrate and the organic material buffer layer to obtain a finished product.
In one embodiment, the method comprises the steps of:
sequentially growing a stripping layer, a GaN high-resistance buffer layer, a GaN channel layer, an AlGaN barrier layer and a P-type GaN layer on a sapphire substrate to obtain a first epitaxial wafer;
etching a mesa isolation structure and a grid mesa structure on the first epitaxial wafer to expose part of the AlGaN barrier layer and the GaN high-resistance buffer layer to obtain a second epitaxial wafer;
depositing a first passivation layer on the surface of the second epitaxial wafer to obtain a third epitaxial wafer;
etching part of the first passivation layer until the AlGaN barrier layer is exposed, and depositing a source electrode and a drain electrode on the AlGaN barrier layer to obtain a fourth epitaxial wafer;
depositing a second passivation layer on the surface of the fourth epitaxial wafer to obtain a fifth epitaxial wafer;
etching part of the second passivation layer until the first passivation layer on the gate mesa structure is exposed, and depositing a gate electrode on the first passivation layer to obtain a sixth epitaxial wafer;
depositing a third passivation layer on the surface of the sixth epitaxial wafer to obtain a seventh epitaxial wafer;
etching the second passivation layer and the third passivation layer above the source electrode and the drain electrode to expose the source electrode and the drain electrode, depositing a field plate metal layer on the source electrode and the drain electrode to form a metal field plate structure, and obtaining an eighth epitaxial wafer;
depositing a fourth passivation layer on the surface of the eighth epitaxial wafer to obtain a ninth epitaxial wafer;
etching the third passivation layer, the field plate metal layer and the fourth passivation layer above the gate electrode to expose the gate electrode, etching the fourth passivation layer above the metal field plate structure to expose the metal field plate structure, and depositing a welding electrode metal layer on the gate electrode and the metal field plate structure to obtain a tenth epitaxial wafer;
coating an organic material buffer layer on the tenth epitaxial wafer, and stacking a magnetic substrate on the organic material buffer layer to obtain an eleventh epitaxial wafer;
the sapphire substrate of the eleventh epitaxial wafer is stripped by laser, the exposed stripping layer is cleaned and removed, and the GaN high-resistance buffer layer is exposed, so that a twelfth epitaxial wafer is obtained;
depositing a welding material layer on one side of the GaN high-resistance buffer layer of the twelfth epitaxial wafer, and stacking a high-heat-conductivity substrate on the welding material layer to obtain a thirteenth epitaxial wafer;
and removing the magnetic substrate and the organic material buffer layer on the thirteenth epitaxial wafer to obtain a finished product.
In one embodiment, the material of the organic material buffer layer is selected from one of paraffin, thermosetting resin, thermoplastic resin, and photoresist;
the thickness of the organic material buffer layer is 1-10 mu m;
the material of the magnetic substrate is selected from one of neodymium iron boron, samarium cobalt, neodymium nickel cobalt, sintered ferrite, bonded ferrite and injection molding ferrite;
the thickness of the magnetic substrate is 0.3 mm-1 mm.
In one embodiment, the material of the solder material layer is selected from one of Ti, al, au, ni, sn, cu, ag and AuSn;
the thickness of the welding material layer is 1-10 mu m;
the material of the high heat conduction substrate is selected from Si, siC, al 2 O 3 One of AlN and diamond;
the thickness of the high heat conduction substrate is 0.3 mm-1 mm;
in one embodiment, the high heat conduction substrate is closely stacked on the welding material layer in a hot-pressing eutectic mode;
the welding temperature of the hot-pressing eutectic is 200-400 ℃ and the pressure is 800-10000 KG;
and removing the magnetic substrate and the organic material buffer layer in a thermal sliding manner.
In one embodiment, the exfoliation layer is an a-doped GaN layer, a being one or more of In, si, mg, and C;
the thickness of the stripping layer is 1 nm-200 nm.
In one embodiment, the source electrode or the drain electrode is made of one or more materials selected from Ti, ni, al, au, pt, ag, W, cu, tiW and TiN;
the thickness of the source electrode or the drain electrode is 0.2-1 mu m;
the material of the gate electrode is one or more selected from Ti, ni, cr, au, pt, sn, al, cu and Ag;
the thickness of the gate electrode is 0.1 μm to 1 μm.
In one embodiment, the material of the field plate metal layer is selected from one or more of Ti, ni, cr, au, pt, sn, al, cu and Ag;
the thickness of the field plate metal layer is 0.2-2 mu m;
the welding electrode metal layer is made of one or more materials selected from Ti, ni, cr, au, pt, sn, fe, co, ni, al, cu, ag and AuSn;
the thickness of the welding electrode metal layer is 0.2-2 mu m.
In one embodiment, the materials of the first passivation layer, the second passivation layer, the third passivation layer and the fourth passivation layer are SiN, siO 2 And SiO x N y One or more of the following;
the thickness of the first passivation layer is 5 nm-200 nm;
the thickness of the second passivation layer is 5 nm-500 nm;
the thickness of the third passivation layer is 0.2-1.5 mu m;
the thickness of the fourth passivation layer is 0.3-1.5 μm.
Correspondingly, the invention also provides a GaN power device, which is prepared by adopting the preparation method of the GaN power device.
The implementation of the invention has the following beneficial effects:
according to the preparation method of the GaN power device, the wafer of the GaN power device with the sapphire substrate is transferred onto the magnetic substrate, and then the peeling layer between the sapphire and the GaN material is irradiated in a laser peeling mode, so that low-damage separation can be performed between the sapphire and the GaN material, then the high-heat-conductivity substrate is bonded onto the wafer in a vacuum hot-pressing eutectic mode in a eutectic bonding mode, and finally the magnetic substrate is removed in a thermal sliding mode.
The invention realizes the transfer of the GaN-based device film from the sapphire substrate with low heat conductivity to the heterogeneous substrate with high heat conductivity, thereby breaking the constraint and limitation of the low heat conduction substrate on the thermal management and leakage current of the GaN-based power device and breaking through the heat dissipation bottleneck of the GaN-based power device. According to the invention, through the introduction of the heterogeneous substrate with high heat conductivity, the heat transmission capacity inside the chip is increased, the heat accumulation of the GaN near junction area is solved, and the high-power characteristic and the reliability of the device are improved. In addition, in the aspect of an epitaxial structure, the stripping layer structure can enable the GaN material to be decomposed more efficiently and rapidly under the action of laser, so that impact on the GaN material in the laser stripping process is reduced, and the reliability of a GaN device is ensured.
Drawings
Fig. 1 is a schematic structural diagram of a first epitaxial wafer in a method for manufacturing a GaN power device according to the present invention;
fig. 2 is a schematic structural diagram of a first epitaxial wafer in the method for manufacturing a GaN power device according to the present invention;
fig. 3 is a schematic structural diagram of a third epitaxial wafer or a fourth epitaxial wafer in the method for manufacturing a GaN power device according to the present invention;
fig. 4 is a schematic structural diagram of a fifth epitaxial wafer or a sixth epitaxial wafer in the method for manufacturing a GaN power device according to the present invention;
fig. 5 is a schematic structural diagram of a seventh epitaxial wafer or an eighth epitaxial wafer in the method for manufacturing a GaN power device according to the present invention;
fig. 6 is a schematic structural diagram of a ninth epitaxial wafer or a tenth epitaxial wafer in the method for manufacturing a GaN power device according to the present invention;
fig. 7 is a schematic structural diagram of an eleventh epitaxial wafer or a twelfth epitaxial wafer in the method for manufacturing a GaN power device according to the present invention;
fig. 8 is a schematic structural diagram of a thirteenth epitaxial wafer in the method for manufacturing a GaN power device according to the present invention;
fig. 9 is a schematic structural diagram of a GaN power device according to the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings, for the purpose of making the objects, technical solutions and advantages of the present invention more apparent.
In order to solve the above problems, the present invention provides a method for manufacturing a GaN power device, comprising the steps of:
s1, sequentially growing a stripping layer 106, a GaN high-resistance buffer layer 102, a GaN channel layer 103, an AlGaN barrier layer 104 and a P-type GaN layer 105 on a sapphire substrate 101;
s2, etching a mesa isolation structure and a gate mesa structure, and exposing part of the AlGaN barrier layer 104 and the GaN high-resistance buffer layer 102;
s3, preparing a source electrode 202B and a drain electrode 202A on the surface of the AlGaN barrier layer 104, depositing a field plate metal layer 206 on the source electrode 202B and the drain electrode 202A to form a metal field plate structure, depositing a gate electrode 204 on the P-type GaN layer 105, and depositing a welding electrode metal layer 208 on the gate electrode 204 and the metal field plate structure;
s4, coating an organic material buffer layer 209, and stacking a magnetic substrate 210 on the organic material buffer layer 209;
s5, stripping the sapphire substrate 101 by laser, and cleaning and removing the exposed stripping layer 106 to expose the GaN high-resistance buffer layer 102;
s6, depositing a welding material layer 211 on one side of the GaN high-resistance buffer layer 102, and stacking a high-heat-conductivity substrate 212 on the welding material layer 211;
and S7, removing the magnetic substrate 210 and the organic material buffer layer 209 to obtain a finished product.
According to the preparation method of the GaN power device, the wafer of the GaN power device with the sapphire substrate is transferred onto the magnetic substrate, and then the peeling layer between the sapphire and the GaN material is irradiated in a laser peeling mode, so that low-damage separation can be performed between the sapphire and the GaN material, then the high-heat-conductivity substrate is bonded onto the wafer in a vacuum hot-pressing eutectic mode in a eutectic bonding mode, and finally the magnetic substrate is removed in a thermal sliding mode.
The invention realizes the transfer of the GaN-based device film from the sapphire substrate with low heat conductivity to the heterogeneous substrate with high heat conductivity, thereby breaking the constraint and limitation of the low heat conduction substrate on the thermal management and leakage current of the GaN-based power device and breaking through the heat dissipation bottleneck of the GaN-based power device. According to the invention, through the introduction of the heterogeneous substrate with high heat conductivity, the heat transmission capacity inside the chip is increased, the heat accumulation of the GaN near junction area is solved, and the high-power characteristic and the reliability of the device are improved.
Specifically, in one embodiment, the invention provides a method for preparing a GaN power device, which comprises the following steps:
(1) As shown in fig. 1, a lift-off layer 106, a GaN high-resistance buffer layer 102, a GaN channel layer 103, an AlGaN barrier layer 104, and a P-type GaN layer 105 are sequentially grown on a sapphire substrate 101 to obtain a first epitaxial wafer;
in one embodiment, the sapphire substrate 101 has a thickness of 100 μm to 1000 μm; exemplary thicknesses of the sapphire substrate 101 are 200 μm, 300 μm, 400 μm, 500 μm, 600 μm, 700 μm, 800 μm, 900 μm, but are not limited thereto.
In one embodiment, the exfoliation layer 106 is an a-doped GaN layer, a being one or more of In, si, mg, and C;
the thickness of the peeling layer 106 is 1nm to 200nm; exemplary thicknesses of the release layer 106 are 10nm, 30nm, 50nm, 70nm, 90nm, 100nm, 110nm, 130nm, 150nm, 170nm, 190nm, but are not limited thereto.
In the aspect of epitaxial structure, the structure of the peeling layer 106 can enable the GaN material to be decomposed more efficiently and rapidly under the action of laser, so that the impact on the GaN material in the laser peeling process is reduced, and the reliability of the GaN device is ensured.
In one embodiment, the GaN high-resistance buffer layer 102 has a thickness of 1 μm to 4 μm; exemplary thicknesses of the GaN high-resistance buffer layer 102 are 2 μm, 3 μm, but are not limited thereto.
In one embodiment, the GaN channel layer 103 has a thickness of 0.1 μm to 1 μm; exemplary thicknesses of the GaN channel layer 103 are 0.2 μm, 0.3 μm, 0.4 μm, 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm, but are not limited thereto.
In one embodiment, the AlGaN barrier layer 104 has a thickness of 0.01 μm to 0.5 μm; exemplary thicknesses of the AlGaN barrier layer 104 are, but not limited to, 0.05 μm, 0.1 μm, 0.2 μm, 0.3 μm, 0.4 μm.
In one embodiment, the thickness of the P-type GaN layer 105 is 0.01 μm to 0.5 μm; exemplary thicknesses of the P-type GaN layer 105 are 0.05 μm, 0.1 μm, 0.2 μm, 0.3 μm, 0.4 μm, but are not limited thereto.
(2) As shown in fig. 2, etching a mesa isolation structure and a gate mesa structure on the first epitaxial wafer to expose a portion of the AlGaN barrier layer 104 and the GaN high-resistance buffer layer 102, thereby obtaining a second epitaxial wafer;
in one embodiment, acetone solution and H are used separately 2 SO 4 And H 2 O 2 Cleaning the surface of epitaxial wafer with solution to remove organic residue and ion pollution, cleaning with flowing deionized water, and cleaning with N 2 And (5) blow-drying. Then, plasma etching ICP is adopted to start etching from the surface of the P-type GaN layer 105 until part of the GaN high-resistance buffer layer 102 is etched, so that a mesa isolation structure is formed, and independent small units are formed between chips. The etching gas may be BCl 3 、Cl 2 、Ar、N 2 One or more of the following. The partial region of the P-type GaN layer 105 is protected by photoetching and patterning, the rest of the P-type GaN layer 105 is continuously etched by adopting a plasma etching ICP mode to expose the AlGaN barrier layer 104, an independent P-type GaN grid mesa structure is formed, and etching gas can be BCl 3 、Cl 2 、Ar、O 2 、N 2 One or more of the following.
(3) As shown in fig. 3, a first passivation layer 201 is deposited on the surface of the second epitaxial wafer, so as to obtain a third epitaxial wafer;
in one embodiment, the material of the first passivation layer 201 is SiN, siO 2 And SiO x N y One or more of the following; the thickness of the first passivation layer 201 is 5 nm-200 nm; exemplary thicknesses of the first passivation layer 201 are 10nm, 30nm, 50nm, 70nm, 90nm, 100nm, 110nm, 130nm, 150nm, 170nm, 190nm, but is not limited thereto.
And depositing a compact passivation layer on the surface of the wafer by means of plasma enhanced chemical vapor deposition PECVD, low pressure chemical vapor deposition LPCVD, atomic layer deposition ALD and the like. The first passivation layer 201 is used for passivating and isolating two-dimensional electron gas, avoiding electric leakage of the device and eliminating current collapse effect.
(4) As shown in fig. 3, etching part of the first passivation layer 201 until the AlGaN barrier layer 104 is exposed, and depositing a source electrode 202B and a drain electrode 202A on the AlGaN barrier layer 104 to obtain a fourth epitaxial wafer;
in one embodiment, the passivation layer is etched by plasma etching ICP, and the etching gas can be Ar or O 2 、N 2 、CF 4 、SF 6 One or more of the following. The source electrode 202B and the drain electrode 202A are deposited by magnetron sputtering, electron beam evaporation Ebeam, or the like. In one embodiment, the source electrode 202B or the drain electrode 202A is made of one or more materials selected from Ti, ni, al, au, pt, ag, W, cu, tiW and TiN; the thickness of the source electrode 202B or the drain electrode 202A is 0.2 μm to 1 μm; exemplary thicknesses of the source electrode 202B or the drain electrode 202A are 0.05 μm, 0.1 μm, 0.2 μm, 0.3 μm, 0.4 μm, 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm, but are not limited thereto. After metal deposition, metal patterning is performed using plasma etching ICP or a photoresist wet stripping process to form a source electrode 202B and a drain electrode 202A and then subjected to high temperature N 2 After annealing, good ohmic contact is formed, and the annealing temperature is 500-1000 ℃.
(5) As shown in fig. 4, a second passivation layer 203 is deposited on the surface of the fourth epitaxial wafer, so as to obtain a fifth epitaxial wafer;
in one embodiment, the dense passivation layer is deposited by plasma enhanced chemical vapor deposition PECVD, low pressure chemical vapor deposition LPCVD, atomic layer deposition ALD, or the like; in one embodiment, the material of the second passivation layer 203 is SiN, siO 2 And SiO x N y One or more of themThe method comprises the steps of carrying out a first treatment on the surface of the The thickness of the second passivation layer 203 is 5 nm-500 nm; exemplary thicknesses of the second passivation layer 203 are 10nm, 30nm, 50nm, 70nm, 90nm, 100nm, 110nm, 130nm, 150nm, 170nm, 190nm, 200nm, 220nm, 230nm, 250nm, 270nm, 290nm, 300nm, 330nm, 350nm, 370nm, 390nm, 400nm, 440nm, 430nm, 450nm, 470nm, 490nm, but are not limited thereto. The second passivation layer 203 is used to isolate moisture migration and ion migration inside the device, and improve the breakdown voltage performance of the device.
(6) As shown in fig. 4, etching a portion of the second passivation layer 203 until the first passivation layer 201 on the gate mesa structure is exposed, and depositing a gate electrode 204 on the first passivation layer 201 to obtain a sixth epitaxial wafer;
in one embodiment, the passivation layer of the P-GaN mesa region is removed by dry etching or wet etching until the first passivation layer 201 on the gate mesa structure is exposed. A metal layer is deposited using electron beam evaporation to form the gate electrode 204. In one embodiment, the material of the gate electrode 204 is selected from one or more of Ti, ni, cr, au, pt, sn, al, cu and Ag; the thickness of the gate electrode 204 is 0.1 μm to 1 μm; exemplary thicknesses of the gate electrode 204 are, but not limited to, 0.2 μm, 0.3 μm, 0.4 μm, 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm.
(7) As shown in fig. 5, depositing a third passivation layer 205 and a third passivation layer 205 on the surface of the sixth epitaxial wafer to obtain a seventh epitaxial wafer;
in one embodiment, the dense passivation layer is deposited by plasma enhanced chemical vapor deposition PECVD, low pressure chemical vapor deposition LPCVD, atomic layer deposition ALD, or the like; the material of the third passivation layer 205 is SiN and SiO 2 And SiO x N y One or more of the following; the thickness of the third passivation layer 205 is 0.2 μm to 1.5 μm; exemplary thicknesses of the third passivation layer 205 are, but not limited to, 0.3 μm, 0.4 μm, 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm, 1 μm, 1.1 μm, 1.2 μm, 1.3 μm, 1.4 μm. The third passivation layer 205 is used to isolate gate goldThe metal layer is used for facilitating the formation of a field plate structure by the source metal and the drain metal, and adjusting the voltage resistance and the capacitance effect of the device.
(8) As shown in fig. 5, the second passivation layer 203 and the third passivation layer 205 above the source electrode 202B and the drain electrode 202A are etched to expose the source electrode 202B and the drain electrode 202A, and a field plate metal layer 206 is deposited on the source electrode 202B and the drain electrode 202A to form a metal field plate structure, so as to obtain an eighth epitaxial wafer;
in one embodiment, the passivation layer on the surfaces of the source electrode 202B and the drain electrode 202A is removed by dry etching or wet etching, and the field plate metal layer 206 is deposited by electron beam evaporation to form a metal field plate structure. In one embodiment, the material of the field plate metal layer 206 is selected from one or more of Ti, ni, cr, au, pt, sn, al, cu and Ag; the thickness of the field plate metal layer 206 is 0.2 μm to 2 μm; exemplary thicknesses of the field plate metal layer 206 are, but not limited to, 0.3 μm, 0.4 μm, 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm, 1 μm, 1.1 μm, 1.2 μm, 1.3 μm, 1.4 μm.
(9) As shown in fig. 6, a fourth passivation layer 207 is deposited on the surface of the eighth epitaxial wafer, so as to obtain a ninth epitaxial wafer;
in one embodiment, the material of the fourth passivation layer 207 is SiN, siO 2 And SiO x N y One or more of the following; the thickness of the fourth passivation layer 207 is 0.3 μm to 1.5 μm; exemplary thicknesses of the fourth passivation layer 207 are, but not limited to, 0.4 μm, 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm, 1 μm, 1.1 μm, 1.2 μm, 1.3 μm, 1.4 μm.
(10) As shown in fig. 6, the third passivation layer 205, the field plate metal layer 206 and the fourth passivation layer 207 above the gate electrode 204 are etched to expose the gate electrode 204, the fourth passivation layer 207 above the metal field plate structure is etched to expose the metal field plate structure, and a welding electrode metal layer 208 is deposited on the gate electrode 204 and the metal field plate structure to obtain a tenth epitaxial wafer;
in one embodiment, the material of the welding electrode metal layer 208 is selected from one or more of Ti, ni, cr, au, pt, sn, fe, co, ni, al, cu, ag and AuSn; the thickness of the welding electrode metal layer 208 is 0.2-2 μm; exemplary thicknesses of the welding electrode metal layer 208 are, but not limited to, 0.3 μm, 0.4 μm, 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm, 1 μm, 1.1 μm, 1.2 μm, 1.3 μm, 1.4 μm, 1.5 μm, 1.6 μm, 1.7 μm, 1.8 μm, 1.9 μm.
The invention forms a through hole structure through the fourth passivation layer 207, so that the grid metal layer and the source electrode and drain electrode field plate metal layer 206 are subjected to redistribution of electrode areas on the surface of the chip in a metal interconnection mode, and the electrode areas are spread on the surface of the chip in a large area. The area of the electrode is increased, so that the heat radiation performance of the device can be improved, the heat radiation and the reliability of the device under high voltage and high current are ensured, and the strength of the magnetic substrate and the wafer, which are adhered by magnetic force, can be improved.
(11) As shown in fig. 7, an organic material buffer layer 209 is coated on the tenth epitaxial wafer, and a magnetic substrate 210 is stacked on the organic material buffer layer 209, to obtain an eleventh epitaxial wafer;
in one embodiment, the material of the organic material buffer layer 209 is selected from one of paraffin, thermosetting resin, thermoplastic resin, and photoresist; the thickness of the organic material buffer layer 209 is 1 μm to 10 μm; exemplary thicknesses of the organic material buffer layer 209 are 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, but are not limited thereto. Specifically, spin-coating an organic buffer material layer on the wafer surface, which has the main function of forming a protective structure layer on the wafer surface to prevent the wafer surface from being scratched due to tiny displacement of the magnetic substrate and the wafer, and then baking to remove redundant solvents in the film.
In one embodiment, the material of the magnetic substrate 210 is selected from one of neodymium iron boron, samarium cobalt, neodymium nickel cobalt, sintered ferrite, bonded ferrite, and injection molded ferrite; the thickness of the magnetic substrate 210 is 0.3mm to 1mm. Exemplary thicknesses of the magnetic substrate 210 are, but are not limited to, 0.4 μm, 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm. In one embodiment, the magnetic substrate 210 is stacked on the surface of the organic material buffer layer 209, such that the magnetic substrate 210 is adsorbed to the wafer through the organic buffer material, and a pressure of 100KG to 300KG is applied to escape bubbles in the organic buffer material.
(12) As shown in fig. 7, the sapphire substrate 101 of the eleventh epitaxial wafer is laser-stripped, and the exposed stripping layer 106 is cleaned and removed to expose the GaN high-resistance buffer layer 102, thereby obtaining a twelfth epitaxial wafer;
in one embodiment, the sapphire substrate 101 is laser stripped using an excimer laser or a solid state laser as a laser generator such that the sapphire substrate 101 is separated from the wafer body, the laser wavelength range being 193nm to 355nm. After separation, the residual material of peel ply 106 is removed using a cleaning solution, which may be HCl, H 2 SO 4 One or more of KOH and NaOH. The stripping layer 106 structure can enable the GaN material to be decomposed more efficiently and rapidly under the action of laser, so that impact on the GaN material in the laser stripping process is reduced, and the reliability of the GaN device is ensured.
(13) As shown in fig. 8, a solder material layer 211 is deposited on one side of the GaN high-resistance buffer layer 102 of the twelfth epitaxial wafer, and a high-thermal-conductivity substrate 212 is stacked on the solder material layer 211 to obtain a thirteenth epitaxial wafer;
in one embodiment, the material of the solder material layer 211 is selected from one of Ti, al, au, ni, sn, cu, ag and AuSn; the thickness of the solder material layer 211 is 1 μm to 10 μm; exemplary thicknesses of the solder material layer 211 are 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, but are not limited thereto.
In one embodiment, the material of the high thermal conductivity substrate 212 is selected from Si, siC, al 2 O 3 One of AlN and diamond; the thickness of the high heat-conducting substrate 212 is 0.3 mm-1 mm; exemplary thicknesses of the high thermal conductivity substrate 212 are, but not limited to, 0.4 μm, 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm.
In one embodiment, the high thermal conductivity substrate 212 is closely stacked on the soldering material layer 211 by using a thermocompression eutectic manner; the welding temperature of the hot-pressing eutectic is 200-400 ℃ and the pressure is 800-10000 KG.
It should be noted that, since GaN-based devices are often applied in a high-voltage and high-power scenario of 650V or 1200V, junction temperature of the chip is raised due to accumulation of internal thermal power consumption in the chip at high power density, and the output characteristic of the device is attenuated at high source-drain bias voltage, which is defined as "self-heating effect", and the larger the power density is, the more obvious the "self-heating effect" is. According to the invention, through the introduction of the heterogeneous substrate with high heat conductivity, the heat transmission capacity inside the chip is increased, the heat accumulation of the GaN near junction area is solved, and the high-power characteristic and the reliability of the device are improved.
(14) As shown in fig. 9, the magnetic substrate 210 and the organic material buffer layer 209 on the thirteenth epitaxial wafer are removed, so as to obtain a finished product.
In one embodiment, the magnetic substrate 210 and the buffer layer 209 of organic material are removed by thermal slip. A lateral shear force is applied by thermal slip, so that the magnetic substrate 210 and the wafer are laterally slipped and finally separated. And chemically cleaning the wafer under the action of ultrasonic waves by using alkaline chemical cleaning liquid to remove the organic buffer layer material remained on the surface.
Correspondingly, the invention also provides a GaN power device, which is prepared by adopting the preparation method of the GaN power device.
The above disclosure is only a preferred embodiment of the present invention, and it is needless to say that the scope of the invention is not limited thereto, and therefore, the equivalent changes according to the claims of the present invention still fall within the scope of the present invention.
Claims (10)
1. The preparation method of the GaN power device is characterized by comprising the following steps of:
s1, sequentially growing a stripping layer, a GaN high-resistance buffer layer, a GaN channel layer, an AlGaN barrier layer and a P-type GaN layer on a sapphire substrate;
s2, etching a mesa isolation structure and a grid mesa structure, and exposing part of the AlGaN barrier layer and the GaN high-resistance buffer layer;
s3, preparing a source electrode and a drain electrode on the surface of the AlGaN barrier layer, depositing a field plate metal layer on the source electrode and the drain electrode to form a metal field plate structure, depositing a gate electrode above the P-type GaN layer, and depositing a welding electrode metal layer on the gate electrode and the metal field plate structure;
s4, coating an organic material buffer layer, and stacking a magnetic substrate on the organic material buffer layer;
s5, stripping the sapphire substrate by laser, and cleaning and removing the exposed stripping layer to expose the GaN high-resistance buffer layer;
s6, depositing a welding material layer on one side of the GaN high-resistance buffer layer, and stacking a high-heat-conductivity substrate on the welding material layer;
s7, removing the magnetic substrate and the organic material buffer layer to obtain a finished product.
2. The method for manufacturing a GaN power device of claim 1, comprising the steps of:
sequentially growing a stripping layer, a GaN high-resistance buffer layer, a GaN channel layer, an AlGaN barrier layer and a P-type GaN layer on a sapphire substrate to obtain a first epitaxial wafer;
etching a mesa isolation structure and a grid mesa structure on the first epitaxial wafer to expose part of the AlGaN barrier layer and the GaN high-resistance buffer layer to obtain a second epitaxial wafer;
depositing a first passivation layer on the surface of the second epitaxial wafer to obtain a third epitaxial wafer;
etching part of the first passivation layer until the AlGaN barrier layer is exposed, and depositing a source electrode and a drain electrode on the AlGaN barrier layer to obtain a fourth epitaxial wafer;
depositing a second passivation layer on the surface of the fourth epitaxial wafer to obtain a fifth epitaxial wafer;
etching part of the second passivation layer until the first passivation layer on the gate mesa structure is exposed, and depositing a gate electrode on the first passivation layer to obtain a sixth epitaxial wafer;
depositing a third passivation layer on the surface of the sixth epitaxial wafer to obtain a seventh epitaxial wafer;
etching the second passivation layer and the third passivation layer above the source electrode and the drain electrode to expose the source electrode and the drain electrode, depositing a field plate metal layer on the source electrode and the drain electrode to form a metal field plate structure, and obtaining an eighth epitaxial wafer;
depositing a fourth passivation layer on the surface of the eighth epitaxial wafer to obtain a ninth epitaxial wafer;
etching the third passivation layer, the field plate metal layer and the fourth passivation layer above the gate electrode to expose the gate electrode, etching the fourth passivation layer above the metal field plate structure to expose the metal field plate structure, and depositing a welding electrode metal layer on the gate electrode and the metal field plate structure to obtain a tenth epitaxial wafer;
coating an organic material buffer layer on the tenth epitaxial wafer, and stacking a magnetic substrate on the organic material buffer layer to obtain an eleventh epitaxial wafer;
the sapphire substrate of the eleventh epitaxial wafer is stripped by laser, the exposed stripping layer is cleaned and removed, and the GaN high-resistance buffer layer is exposed, so that a twelfth epitaxial wafer is obtained;
depositing a welding material layer on one side of the GaN high-resistance buffer layer of the twelfth epitaxial wafer, and stacking a high-heat-conductivity substrate on the welding material layer to obtain a thirteenth epitaxial wafer;
and removing the magnetic substrate and the organic material buffer layer on the thirteenth epitaxial wafer to obtain a finished product.
3. The method for manufacturing a GaN power device according to claim 1 or 2, wherein the material of the organic material buffer layer is one selected from paraffin, thermosetting resin, thermoplastic resin, and photoresist;
the thickness of the organic material buffer layer is 1-10 mu m;
the material of the magnetic substrate is selected from one of neodymium iron boron, samarium cobalt, neodymium nickel cobalt, sintered ferrite, bonded ferrite and injection molding ferrite;
the thickness of the magnetic substrate is 0.3 mm-1 mm.
4. The method for manufacturing a GaN power device according to claim 1 or 2, wherein the material of the solder material layer is selected from one of Ti, al, au, ni, sn, cu, ag and AuSn;
the thickness of the welding material layer is 1-10 mu m;
the material of the high heat conduction substrate is selected from Si, siC, al 2 O 3 One of AlN and diamond;
the thickness of the high heat conduction substrate is 0.3 mm-1 mm.
5. The method for manufacturing the GaN power device according to claim 1 or 2, wherein the high-heat-conductivity substrate is tightly stacked on the welding material layer in a hot-pressing eutectic manner;
the welding temperature of the hot-pressing eutectic is 200-400 ℃ and the pressure is 800-10000 KG;
and removing the magnetic substrate and the organic material buffer layer in a thermal sliding manner.
6. The method for manufacturing a GaN power device according to claim 1 or 2, wherein the peeling layer is an a-doped GaN layer, a being one or more of In, si, mg and C;
the thickness of the stripping layer is 1 nm-200 nm.
7. The method for manufacturing a GaN power device according to claim 1 or 2, wherein the material of the source electrode or the drain electrode is one or more selected from Ti, ni, al, au, pt, ag, W, cu, tiW and TiN;
the thickness of the source electrode or the drain electrode is 0.2-1 mu m;
the material of the gate electrode is one or more selected from Ti, ni, cr, au, pt, sn, al, cu and Ag;
the thickness of the gate electrode is 0.1 μm to 1 μm.
8. The method for manufacturing a GaN power device according to claim 1 or 2, wherein the material of the field plate metal layer is one or more selected from Ti, ni, cr, au, pt, sn, al, cu and Ag;
the thickness of the field plate metal layer is 0.2-2 mu m;
the welding electrode metal layer is made of one or more materials selected from Ti, ni, cr, au, pt, sn, fe, co, ni, al, cu, ag and AuSn;
the thickness of the welding electrode metal layer is 0.2-2 mu m.
9. The method for manufacturing a GaN power device according to claim 2, wherein the materials of the first passivation layer, the second passivation layer, the third passivation layer and the fourth passivation layer are SiN and SiO 2 And SiO x N y One or more of the following;
the thickness of the first passivation layer is 5 nm-200 nm;
the thickness of the second passivation layer is 5 nm-500 nm;
the thickness of the third passivation layer is 0.2-1.5 mu m;
the thickness of the fourth passivation layer is 0.3-1.5 μm.
10. A GaN power device manufactured by the manufacturing method of the GaN power device according to any one of claims 1 to 9.
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