JP2021082773A - Semiconductor device, manufacturing method for semiconductor device, and field effect transistor - Google Patents

Abstract

To provide a technique that can suppress buffer leakage.SOLUTION: A semiconductor device includes a nitride semiconductor epitaxial layer, and a semiconductor substrate bonded to the nitride semiconductor epitaxial layer and being different in material from the nitride semiconductor epitaxial layer. The nitride semiconductor epitaxial layer includes an impurity region that is an ion implantation region on the semiconductor substrate side. The impurity region has higher impurity concentration and higher electric resistance than a part of the nitride semiconductor epitaxial layer that is adjacent to the impurity region.SELECTED DRAWING: Figure 1

Description

The present invention relates to a semiconductor device, a method for manufacturing a semiconductor device, and a field effect transistor.

In a transistor made of a nitride semiconductor, a method of epitaxially growing a nitride semiconductor on a semiconductor substrate is generally used. When epitaxial growth is performed, silicon atoms in the air adhere to the semiconductor substrate, and some silicon (Si) atoms are mixed at the interface between the semiconductor substrate and the epitaxial growth layer. When a large amount of Si atoms are mixed in the nitride semiconductor epitaxial layer, there is a problem that a drain leak current (also referred to as “buffer leak current”) is generated through the bulk crystal.

On the other hand, since the temperature rise of the transistor during operation causes a failure, it is necessary to reduce the thermal resistance from the transistor to the heat sink for cooling. Therefore, Patent Document 1 proposes a transistor in which the thermal resistance from the growth film to the heat sink is reduced by adhering diamond to the epitaxial growth layer separated from the semiconductor substrate. Patent Document 2 proposes a technique for removing a part of the epitaxial growth layer mixed with silicon atoms by scraping a part of the epitaxial growth layer from the semiconductor substrate in the film thickness direction.

Japanese Unexamined Patent Publication No. 2000-58562 Japanese Unexamined Patent Publication No. 2010-676662

Mixing of Si atoms in the nitride semiconductor epitaxial layer can be reduced by scraping a part of the epitaxial growth layer in the film thickness direction as in the technique of Patent Document 2. However, since there is a possibility that Si may be mixed in when diamond is bonded to the epitaxial growth layer, there is a problem that buffer leakage due to the mixed Si or the like is not sufficiently suppressed.

Therefore, the present invention has been made in view of the above problems, and an object of the present invention is to provide a technique capable of suppressing a buffer leak.

The semiconductor device according to the present invention includes a nitride semiconductor epitaxial layer and a semiconductor substrate bonded to the nitride semiconductor epitaxial layer and having a material different from that of the nitride semiconductor epitaxial layer. The semiconductor substrate side has an impurity region which is an ion injection region, and the impurity region has a higher impurity concentration and electrical resistance than a portion of the nitride semiconductor epitaxial layer adjacent to the impurity region.

According to the present invention, the nitride semiconductor epitaxial layer has an impurity region which is an ion implantation region on the semiconductor substrate side, and the impurity region has a higher impurity concentration and a higher impurity concentration than the portion of the nitride semiconductor epitaxial layer adjacent to the impurity region. High electrical resistance. According to such a configuration, the buffer leak can be suppressed.

It is sectional drawing which shows an example of the structure of the heterojunction field effect transistor which concerns on Embodiment 1. FIG. It is sectional drawing which shows an example of the manufacturing method of the heterojunction field effect transistor which concerns on Embodiment 1. FIG. It is sectional drawing which shows an example of the manufacturing method of the heterojunction field effect transistor which concerns on Embodiment 1. FIG. It is sectional drawing which shows an example of the manufacturing method of the heterojunction field effect transistor which concerns on Embodiment 1. FIG. It is sectional drawing which shows an example of the manufacturing method of the heterojunction field effect transistor which concerns on Embodiment 1. FIG. It is sectional drawing which shows an example of the manufacturing method of the heterojunction field effect transistor which concerns on Embodiment 1. FIG. It is sectional drawing which shows the modification of the manufacturing method of the heterojunction field effect transistor which concerns on Embodiment 1. FIG. It is sectional drawing which shows the modification of the manufacturing method of the heterojunction field effect transistor which concerns on Embodiment 1. FIG. It is sectional drawing which shows the modification of the manufacturing method of the heterojunction field effect transistor which concerns on Embodiment 1. FIG. It is sectional drawing which shows an example of the manufacturing method of the heterojunction field effect transistor which concerns on Embodiment 1. FIG. It is sectional drawing which shows an example of the manufacturing method of the heterojunction field effect transistor which concerns on Embodiment 1. FIG. It is sectional drawing which shows an example of the manufacturing method of the heterojunction field effect transistor which concerns on Embodiment 1. FIG. It is sectional drawing which shows an example of the manufacturing method of the heterojunction field effect transistor which concerns on Embodiment 1. FIG. It is sectional drawing which shows an example of the manufacturing method of the heterojunction field effect transistor which concerns on Embodiment 1. FIG. It is sectional drawing which shows an example of the manufacturing method of the heterojunction field effect transistor which concerns on Embodiment 1. FIG. It is sectional drawing which shows an example of the manufacturing method of the heterojunction field effect transistor which concerns on Embodiment 1. FIG. It is sectional drawing which shows an example of the manufacturing method of the heterojunction field effect transistor which concerns on Embodiment 1. FIG. It is a figure for demonstrating the effect of the heterojunction field effect transistor which concerns on Embodiment 1. FIG. It is a figure for demonstrating the effect of the heterojunction field effect transistor which concerns on Embodiment 1. FIG.

<Embodiment 1>
FIG. 1 is a cross-sectional view showing an example of the configuration of a heterojunction field effect transistor which is a semiconductor device according to the first embodiment of the present invention. This heterojunction field effect transistor includes a semiconductor substrate 16 bonded to an epitaxial growth layer 17 which is a nitride semiconductor epitaxial layer. The material of the semiconductor substrate 16 may be different from that of the epitaxial growth layer 17, but it is desirable that the semiconductor substrate 16 has a higher thermal conductivity than the epitaxial growth layer 17. For example, when the epitaxial growth layer 17 contains a nitride semiconductor such as GaN (gallium nitride), SiC (silicon carbide) or diamond having a higher thermal conductivity than the nitride semiconductor is used as the material of the semiconductor substrate 16. The "semiconductor substrate" referred to here may be an insulator such as diamond or silicon.

The epitaxial growth layer 17 of FIG. 1 includes a buffer layer 2, a channel layer 3, and an electron supply layer 4. That is, the epitaxial growth layer 17 includes an electron supply layer 4 on the uppermost layer, a channel layer 3 under the electron supply layer 4, a buffer layer 2 arranged in this order between the channel layer 3 and the semiconductor substrate 16, and a high resistance. It is a laminated structure including a chemical impurity injection layer 15. In such a configuration, the interface and bonding between the semiconductor substrate 16 and the epitaxial growth layer 17 are substantially the same as the interface and bonding between the semiconductor substrate 16 and the buffer layer 2.

A buffer layer 2 made of, for example, GaN is arranged on the semiconductor substrate 16. The epitaxial growth layer 17 has a high resistance impurity implantation layer 15 as an impurity region which is an ion implantation region on the semiconductor substrate 16 side. The high resistance impurity injection layer 15 has a higher impurity concentration and electrical resistance than the portion of the epitaxial growth layer 17 adjacent to the high resistance impurity injection layer 15. The high resistance impurity injection layer 15 according to the first embodiment is at least a part of the semiconductor substrate 16 side of the buffer layer 2, and is more impurities than the portion of the buffer layer 2 adjacent to the high resistance impurity injection layer 15. It is an impurity region with high concentration and electrical resistance. The high resistance impurity injection layer 15 may be a part of the epitaxial growth layer 17 and may not be a part of the buffer layer 2.

High resistance The high resistance of the impurity implantation layer 15 is realized by the ion implantation method. For example, for ions such as He, N, O, Mg, Ar, Ca, Fe, Zn, Sr, and Ba, the acceleration energy is 10 to 1000 keV and the dose amount is 1 × 10 ¹¹ to 1 × 10 ²⁰ cm- ^2. High resistance is achieved by using the ion implantation method of irradiation. In the first embodiment, Ar ions are injected with an acceleration energy of 100 keV and a dose amount of 5 × 10 ¹⁴ cm- ^2.

On the buffer layer 2, for example, a channel layer 3 made of GaN and having at least one of a composition and an impurity concentration different from that of the buffer layer 2 is arranged. On the channel layer 3, for example, _{an electron supply layer 4 made of Al 0.17} Ga _0.83 N is arranged with a thickness of 32 nm. Near the interface between the electron supply layer 4 and the channel layer 3, specifically, in the portion of the channel layer 3 at a certain depth from the interface with the electron supply layer 4, from the polarization charge generated by spontaneous polarization and piezo polarization. Two-dimensional electron gas 11 is induced.

Here, the mixed crystal ratio of Al in the electron supply layer 4 is 0.17, and the thickness of the electron supply layer 4 is 32 nm, but the composition and thickness of the electron supply layer 4 are not limited to this, and are final. It may be adjusted according to the specifications required for the transistor. ^{For example, in the above configuration, a two-dimensional electron gas 11 of about 6.2 × 10 12} cm- ² is induced near the interface between the electron supply layer 4 and the channel layer 3, so the sheet carrier concentration thereof is adjusted to be smaller. If this is the case, at least one of lowering the Al mixed crystal ratio of the electron supply layer 4 and reducing the thickness may be performed. On the contrary, if the sheet carrier concentration of the two-dimensional electron gas 11 is adjusted to be higher, at least one of increasing the Al mixed crystal ratio of the electron supply layer 4 and increasing the thickness is performed. It should be carried out.

In the above description, the interface and bonding between the semiconductor substrate 16 and the epitaxial growth layer 17 are substantially the same as the interface and bonding between the semiconductor substrate 16 and the buffer layer 2, and the high resistance impurity injection layer 15 is a buffer. It was at least a part of the layer 2 on the semiconductor substrate 16 side. However, as will be described later, there is also a configuration in which the buffer layer 2 is not included in the epitaxial growth layer 17. In the case of this configuration, the interface and bonding between the semiconductor substrate 16 and the epitaxial growth layer 17 are substantially the same as the interface and bonding between the semiconductor substrate 16 and the channel layer 3, and the high resistance impurity injection layer 15 is a channel. It is at least a part of the layer 3 on the semiconductor substrate 16 side. The density of dislocations inherent in the epitaxial growth layer 17 is, for example, 1 × 10 ¹⁰ cm- ² or less, and the Si concentration is, for example, 1 × 10 ¹⁶ cm ^-3 or less.

By implanting ions into at least a part of the epitaxial growth layer 17 on the semiconductor substrate 16 side, the high resistance impurity implantation layer 15 is formed in the ion-implanted region within 300 nm on the epitaxial growth layer 17 side from the interface of the semiconductor substrate 16. .. The defect density of the high resistance impurity implantation layer 15 is 10 times or more higher than that of the non-ion implantation region, and the resistance of the high resistance impurity implantation layer 15 is higher than that of a part of the surface opposite to the epitaxial growth layer 17. The high resistance impurity injection layer 15 has the effect of suppressing the drain leak current (buffer leak current).

On the upper surface of the electron supply layer 4, which is the uppermost layer of the epitaxial growth layer 17, a drain electrode 7 and a source electrode 8 made of a laminated film of Ti and Al (hereinafter referred to as “Ti / Al film”), Ni and Au are provided. A gate electrode 9 made of a laminated film (hereinafter referred to as “Ni / Au film”) is provided. The drain electrode 7 and the source electrode 8 are provided apart from each other, and the gate electrode 9 is provided apart from the drain electrode 7 and the source electrode 8 in the region between them.

The drain electrode 7 and the source electrode 8 may be made of a material other than the Ti / Al film as long as the ohmic contact with the epitaxial growth layer 17 is obtained. For example, Ti, Al, Nb, Hf, Zr, Sr, It may be a metal such as Ni, Ta, Au, Pt, Mo, W, or a multilayer film composed of two or more of them. Further, the material of the gate electrode 9 may be other than the Ni / Au film, for example, metals such as Ti, Al, Cu, Cr, Mo, W, Pt, Au, Ni, Pd, IrSi, PtSi, NiSi ₂ Palladium such as, or nitride metal such as TiN and WN, or a multilayer film in which they are combined may be used.

At least a part of the electron supply layer 4, which is the epitaxial growth layer 17 under the drain electrode 7 and the source electrode 8, is provided with n-type impurity injection regions 5 and 6 to which n-type impurities are added, respectively. The upper part of the n-type impurity injection regions 5 and 6 reaches the upper surface of the electron supply layer 4, the depth thereof is larger than the thickness of the electron supply layer 4, and the bottom portion reaches the channel layer 3. Here, Si is used as the n-type impurity added to the n-type impurity injection regions 5 and 6. However, the n-type impurities added to the n-type impurity injection regions 5 and 6 are not limited to Si, and other materials (for example, O, Ge, N, etc.) that form n-type impurity levels in the nitride semiconductor are used. There may be. Further, as will be described later, the n-type impurity injection regions 5 and 6 may not be arranged.

The upper surface of the electron supply layer 4 is covered with the surface protective film 10 except for the portion where the drain electrode 7, the source electrode 8 and the gate electrode 9 are arranged. Here, the surface protective film 10 is made of ECR (Electron Cyclotron Resonance) -SiN, and its thickness is, for example, 80 nm.

<Manufacturing method>
2 to 17 are diagrams for explaining an example of the method for manufacturing the heterojunction field effect transistor shown in FIG. 1, or a diagram for explaining a modified example thereof. In these figures, the same or corresponding components as those shown in FIG. 1 are designated by the same reference numerals.

First, the laminate shown in FIG. 2 is formed. For example, a manufacturing semiconductor substrate 1 including a nitride semiconductor made of GaN is installed in an epitaxial growth apparatus. Then, for example, a buffer layer 2 made of GaN is formed on the semiconductor substrate 1 for manufacturing by using an epitaxial growth method such as a MOCVD (Metal Organic Chemical Vapor Deposition) method or an MBE (Molecular Beam Epitaxy) method.

Subsequently, a channel layer 3 made of GaN is formed on the buffer layer 2 by an epitaxial growth method. Further, an electron supply layer 4 made of _{Al 0.17} Ga _0.83 N is formed on the channel layer 3 by an epitaxial growth method. As a result, as shown in FIG. 2, an epitaxial growth layer 17a, which is a nitride semiconductor epitaxial layer including the buffer layer 2, the channel layer 3, and the electron supply layer 4, is formed on the manufacturing semiconductor substrate 1.

The epitaxial growth layer 17a becomes the epitaxial growth layer 17 of FIG. 1 by adding the high resistance impurity injection layer 15 through the steps described below. As shown in FIG. 2, interfacial impurities 12 such as Si atoms in the air that generate a buffer leak current are mixed in the portion of the epitaxial growth layer 17a on the manufacturing semiconductor substrate 1 side.

The manufacturing semiconductor substrate 1 on which the buffer layer 2, the channel layer 3, and the electron supply layer 4 are formed is taken out from the epitaxial growth apparatus. Then, using the photolithography technique, a resist mask 14 having openings in the formation regions of the drain electrode 7 and the source electrode 8 is formed on the electron supply layer 4. Then, under the condition that the implantation dose amount is 1 × 10 ¹³ to 1 × 10 ¹⁷ cm- ² and the implantation energy is 10 to 1000 keV, the resist mask 14 is used as a mask, and n-type impurities such as Si are removed into the epitaxial growth layer 17a. Ion implantation is performed. As a result, n-type impurity injection regions 5 and 6 are formed as shown in FIG.

Although not shown, after removing the resist mask 14, metals such as Ti, Al, Nb, Hf, Zr, Sr, Ni, Ta, Au, Pt, Mo, and W are used, for example, by a vapor deposition method or a sputtering method. Alternatively, a multilayer film composed of two or more of them is deposited on the electron supply layer 4. Then, the drain electrode 7 and the source electrode 8 are formed as shown in FIG. 4 by patterning the deposited film using a lift-off method, a photolithography method, or the like.

Next, although not shown, metals such as Ti, Al, Cu, Cr, Mo, W, Pt, Au, Ni, and Pd, and silicides such as _{IrSi, PtSi, and NiSi 2 are used, for example, by a vapor deposition method or a sputtering method.} Alternatively, a nitride metal such as TiN or WN, or a multilayer film combining them is deposited on the electron supply layer 4. Then, the gate electrode 9 is formed as shown in FIG. 5 by patterning the sedimentary film by using a lift-off method, a photolithography method, or the like.

After that, a surface protective film 10 made of an oxide film or a nitride film of Si or Al is formed on the surface of the electron supply layer 4 by using a film forming method having high coating properties such as an ALD (Atomic Layer Deposition) method. Then, the surface protective film 10 is patterned by dry etching or the like so that the drain electrode 7, the source electrode 8 and the gate electrode 9 are exposed from the surface protective film 10. As a result, as shown in FIG. 6, a surface protective film 10 that covers the surface of the electron supply layer 4 is formed. The method for forming the surface protective film 10 is not limited to the ALD method, and other methods such as the PECVD (Plasma Enhanced Chemical Vapor Deposition) method and the sputtering method may be used, or a combination thereof may be used.

Here, a modified example at this point will be described. When the band gap size of the channel layer 3 is E3 and the band gap size of the electron supply layer 4 is E4, the operation of the heterojunction field effect transistor can be ensured if the relationship E3 <E4 is satisfied. .. Therefore, the manufacturing semiconductor substrate 1, the buffer layer 2, and the channel layer 3 do not necessarily have to be composed of GaN, and the electron supply layer 4 does not necessarily have to be composed _{of Al 0.17} Ga _{0.83 N.} For example, the compositions of the elements constituting the channel layer 3 and the electron supply layer 4 may be different from each other, and these elements may contain at least one of Al and Ga and N. For example, the manufacturing semiconductor substrate 1, the buffer layer 2, and the channel layer 3 _{may be made of a material containing Al x} Ga _1-x N (0 ≦ x ≦ 1) as a main component.

In order to satisfy the relationship of E3 <E4 in that configuration, the nitride semiconductor constituting the channel layer 3 is Al _x1 Ga _1-x1 N, and the nitride semiconductor constituting the electron supply layer 4 is Al _x2 Ga _1-x2. When N is set, the relations of 0 ≦ x1 <1, 0 <x2 <1, and x1 <x2 may be satisfied. Further, the channel layer 3 and the electron supply layer 4 may be made of a nitride semiconductor in which In is added to at least one of Al and Ga and N.

In the growth step of the channel layer 3 and the electron supply layer 4 made of various nitride semiconductors as described above, the raw materials of trimethylammonium, trimethylgallium, trimethylindium, ammonia, or n-type dopant which are the raw material gases of the nitride semiconductors. The pressure, flow rate, temperature, and introduction time of silane, which is a gas, are adjusted. By such adjustment, the channel layer 3 and the electron supply layer 4 having a desired composition, film thickness, and doping concentration can be formed.

When the channel layer 3 and the electron supply layer 4 are composed of a compound composed of an element containing at least one of Al and Ga and N, a large polarization effect is generated in the electron supply layer 4, so that the concentration of 2 is high. The dimensional electron gas 11 can be generated. When the concentration of the two-dimensional electron gas 11 is high, it is advantageous for increasing the current of the transistor and further increasing the output. However, the binary crystal of AlN cannot be adopted only for the channel layer 3. This is because there is no material having a band gap exceeding AlN in the nitride semiconductor at present, so that there is no material that can be used for the electron supply layer 4.

The higher the dielectric breakdown electric field of the channel layer 3, the higher the withstand voltage of the heterojunction field effect transistor. Al _x Ga _1-x N, the higher Al composition is higher, the greater the band gap, since the breakdown electric field increases, _Al x1 _{Ga1 -x1} N constituting the channel layer 3 is Al composition higher (x1 Is close to 1) is preferable. Further, the larger the band gap of the electron supply layer 4, the more the gate leak current flowing from the gate electrode 9 to the hetero interface through the electron supply layer 4 can be suppressed. _Therefore, Al x2 Ga _1-x2 N constituting the electron supply layer 4 can be suppressed. Also, it is preferable that the Al composition is higher (x2 is close to 1).

The cross-sectional shape of the gate electrode 9 does not have to be rectangular as shown in FIG. 1, and may be, for example, T-shaped, Y-shaped, or Γ-shaped. Further, as shown in FIG. 7, a field plate electrode 13 that is electrically connected to the gate electrode 9 and extends on the surface protective film 10 may be provided. FIG. 7 shows a configuration in which the field plate electrode 13 extends from the gate electrode 9 to the drain electrode 7 side, but the field plate electrode 13 may extend to the source electrode 8 side or the drain electrode. It may extend to both the 7 side and the 8 side of the source electrode.

By providing the field plate electrode 13, the electric field concentration at the end of the gate electrode 9 can be suppressed, which is effective in reducing the current collapse. The material of the field plate electrode 13 may be any material as long as it can be electrically connected to the gate electrode 9 and can be formed so as not to come into contact with the epitaxial growth layer 17a. After forming the surface protective film 10, a conductive film to be used as a material for the field plate electrode 13 is formed on the surface protective film 10 by a vapor deposition method or the like, and the conductive film is processed into a desired pattern by a lift-off method or the like. The field plate electrode 13 can be formed.

The semiconductor substrate 1 for manufacturing is not limited to GaN, and may be composed of AlN, InN, a mixed crystal thereof, or the like, or may be composed of Si. However, it is difficult to continuously grow crystals having a lattice constant different from that of the semiconductor substrate 1 for manufacturing from the semiconductor substrate 1 for manufacturing with good quality. Therefore, it is preferable that the lattice constants of the semiconductor substrate 1 for manufacturing and the lattice constants of the buffer layer 2 and the channel layer 3 are the same. When it is difficult to make the lattice constants uniform, the influence on the buffer leak current may be considered by inserting a lattice strain relaxation layer into the epitaxial growth layer 17a. Further, from the viewpoint of lattice strain relaxation, the channel layer 3 and the electron supply layer 4 may be formed without forming the buffer layer 2 on the semiconductor substrate 1 for manufacturing. That is, it is not always necessary to form the buffer layer 2 on the semiconductor substrate 1 for manufacturing.

Further, each of the channel layer 3 and the electron supply layer 4 does not necessarily have to have a single layer structure having a single composition. If the condition of the size of the band gap (E3 <E4) is satisfied, the entire channel layer 3 and the electron supply layer 4 may be one layer in which the In composition, the Al composition, and the Ga composition continuously change. However, it may have a multi-layer structure in which a plurality of layers having different compositions are combined so that the composition changes stepwise. In addition, in FIG. 7 and FIGS. 8 and 9 described later, the channel layer 3 and the electron supply layer 4 are one layer whose composition continuously changes as described above, and the buffer layer 2 is not formed. For convenience, it is illustrated by one channel layer 3. The channel layer 3 and the electron supply layer 4 may contain impurities exhibiting n-type or p-type in the nitride semiconductor.

If the drain electrode 7 and the source electrode 8 form an ohmic contact with the two-dimensional electron gas 11 generated near the interface between the electron supply layer 4 and the channel layer 3, the drain electrode 7 and the source are as shown in FIG. It is not necessary to provide the n-type impurity injection regions 5 and 6 under the electrode 8.

Further, the drain electrode 7 and the source electrode 8 may be provided so as to be in contact with the upper surface of the epitaxial growth layer 17a as shown in FIG. 8, or to be in contact with the recess portion on the upper side of the epitaxial growth layer 17a as shown in FIG. It may be provided in. However, the configuration in which the n-type impurity injection regions 5 and 6 are arranged under the drain electrode 7 and the source electrode 8 reduces the resistance between the drain electrode 7 and the source electrode 8 and the two-dimensional electron gas 11. Therefore, it is advantageous for increasing the current and output of the transistor.

The configuration of FIG. 8 can be formed by omitting the ion implantation of the n-type impurity shown in FIG. Further, the configuration of FIG. 9 can be formed by, for example, performing a step of selectively removing the upper portion of the epitaxial growth layer 17a using a _{Cl 2-based etching gas instead of the step shown in FIG.} In addition, each of the above-mentioned modified examples can be carried out in combination with each other.

The method for manufacturing the heterojunction field effect transistor will be described from the continuation of the process of FIG. After the step of FIG. 6, the semiconductor substrate 1 for manufacturing is removed by thinning in order to improve the resistance and heat dissipation efficiency by ion implantation into the epitaxial growth layer 17a. However, when the thickness of the epitaxial growth layer 17a is about 10 μm, the strength thereof becomes low, so that the epitaxial growth layer 17a may become defective due to breakage during the dividing, joining, and peeling steps. In particular, when Si is used for the semiconductor substrate 1 for manufacturing and GaN is used for the epitaxial growth layer 17a, stress is inherent in the epitaxial growth layer 17a due to the difference in the lattice constant and the coefficient of thermal expansion of the two materials. If the semiconductor substrate 1 for manufacturing is removed under this state, the epitaxial growth layer 17a may be damaged due to the stress inherent in the GaN. In the following, an example of removing the semiconductor substrate 1 for manufacturing by thinning is shown, but a method other than thinning may be used as long as the damage of the epitaxial growth layer 17a is suppressed.

As shown in FIG. 10, the adhesive protective layer 18 is coated and formed on the semiconductor element formed on the semiconductor substrate 1 for manufacturing. Here, the semiconductor element includes a drain electrode 7, a source electrode 8, a gate electrode 9, a surface protective film 10, and the like formed on the epitaxial growth layer 17a. The adhesive protective layer 18 is a layer that reinforces the strength of the film thinned in the subsequent process. When the semiconductor element is a high-frequency circuit element including an electrode having a hollow structure (not shown) such as an air bridge structure, the electrode is protected by an adhesive protective layer 18 so as not to be damaged in a later peeling step or the like. The adhesive protective layer 18 contains, for example, an adhesive made of a heat-curable resin or a photocurable resin and an organic solvent, which can be removed by a chemical treatment. The material includes, for example, acrylic resin, olefin resin, phenol resin, polypropylene resin, polyethylene resin, polyethylene resin and the like. In the method of applying the adhesive protective layer 18, for example, after placing the adhesive to be the adhesive protective layer 18 on the main surface on which the semiconductor element of the semiconductor substrate 1 for manufacturing is formed, the in-plane of the semiconductor substrate 1 for manufacturing is applied. A spin coating method is used in which the device rotates at high speed with reference to the center of the device. The coating thickness of the adhesive protective layer 18 is, for example, 5 to 8 μm. The method of applying the adhesive protective layer 18 may be a printing method, a spray method, or the like. By heating the applied adhesive protective layer 18 to 90 to 120 ° C. on a hot plate or the like, the solvent component of the adhesive protective layer 18 is evaporated and the adhesive protective layer 18 is cured. When the adhesive protective layer 18 contains a photocurable resin, the dried adhesive protective layer 18 may be irradiated with light to be cured.

Then, as shown in FIG. 11, a release layer 20 is formed on the support substrate 21 separately from the semiconductor elements processed so far to form the first structure. The release layer 20 contains, for example, an adhesive composed of a resin made of a carbon material and an organic solvent that absorbs heat and thermally decomposes when irradiated with light. The release layer 20 is formed by, for example, applying by a spin coating method, a printing method, a spray method, or the like, and then heating and drying. For the support substrate 21, a hard and light-transmitting wafer such as non-alkali glass or sapphire glass is used.

Further, as shown in FIG. 11, the adhesive layer 19 is formed on the adhesive protective layer 18 to form the second structure. In the first embodiment, the adhesive layer 19 contains an adhesive composed of an ultraviolet curable resin such as urethane acrylate, acrylic resin acrylate, and epoxy acrylate and an organic solvent. The adhesive layer 19 is formed by, for example, applying by a spin coating method, a printing method, a spray method, or the like, and then heating and drying.

Then, as shown in FIG. 12, the first structure and the second structure are overlapped with each other, and the release layer 20 and the adhesive layer 19 are brought into contact with each other. In this state, the first structure and the second structure are adhered and bonded by irradiating ultraviolet rays from the light-transmitting support substrate 21 side to cure the adhesive layer 19 with a resin. The adhesive layer 19 does not have to contain an ultraviolet curable resin. However, when the adhesive layer 19 contains an ultraviolet curable resin as in the first embodiment, the adhesive layer 19 can be cured in a relatively short time, so that the process time can be shortened and the alignment can be misaligned. Suppression can be expected. If air or the like enters the adhesive layer 19 and the release layer 20 during the above-mentioned adhesion (bonding), that portion becomes an unadhered portion, which causes a decrease in the adhesive strength. Therefore, if the adhesive layer 19 and the peeling layer 20 are defoamed in a vacuum after stacking and before bonding, and then bonding is performed, the unbonded portion can be reduced, so that a decrease in adhesive strength is suppressed. can do.

As described above, a laminate in which the adhesive protective layer 18, the adhesive layer 19, the release layer 20, and the support substrate 21 are arranged in this order is formed on the semiconductor element. The order of forming the laminate is not limited to the above. For example, the laminate may be formed by forming the adhesive protective layer 18, the adhesive layer 19, the release layer 20, and the support substrate 21 on the semiconductor element in this order.

Next, as shown in FIG. 13, the manufacturing semiconductor substrate 1 and the manufacturing semiconductor substrate 1 of the epitaxial growth layer 17a are thinned by polishing from the opposite side (back surface) of the manufacturing semiconductor substrate 1 to the epitaxial growth layer 17a. And scrape the adjacent part. As a result, the semiconductor substrate 1 for manufacturing can be removed, and the portion of the epitaxial growth layer 17a on which the interfacial impurities 12 are deposited can be removed to some extent. Although only the semiconductor substrate 1 for manufacturing may be removed, it is preferable to remove some interfacial impurities 12 that cause a buffer leak current.

The thickness of the manufacturing semiconductor substrate 1 before polishing is, for example, 500 μm, and the thickness of the epitaxial growth layer 17a after polishing is, for example, several hundred nm. As the polishing method of the semiconductor substrate 1 for manufacturing, for example, mechanical polishing, chemical polishing, mechanical chemical polishing and the like are used. Then, for example, dry etching such as RIE (reactive ion etching) is used to further reduce the wall thickness.

Next, as shown in FIG. 14, the high resistance impurity implantation layer 15 is formed by implanting ions into at least a part of the epitaxial growth layer 17a on the side from which the manufacturing semiconductor substrate 1 has been removed. As a result, the epitaxial growth layer 17a becomes the epitaxial growth layer 17 of FIG. The ion implantation method is used to increase the resistance for forming the high resistance impurity implantation layer 15. For example, for ions such as He, N, O, Mg, Ar, Ca, Fe, Zn, Sr, and Ba, the acceleration energy is 10 to 1000 keV and the dose amount is 1 × 10 ¹¹ to 1 × 10 ²⁰ cm- ^2. High resistance is achieved by using the ion implantation method of irradiation. In the first embodiment, Ar ions are injected with an acceleration energy of 100 keV and a dose amount of 5 × 10 ¹⁴ cm- ^2.

In FIG. 14, the high resistance impurity implantation layer 15 is formed by implanting ions into the lower surface of the epitaxial growth layer 17a from which the manufacturing semiconductor substrate 1 has been removed, but the present invention is not limited to this. .. As described above, when materials having different lattice constants are used for the manufacturing semiconductor substrate 1 and the buffer layer 2, a lattice strain relaxation layer may be inserted into the epitaxial growth layer 17a. In that case, the process is interrupted during epitaxial growth, and depending on the conditions, agglutination of impurities may occur at the interface (growth interruption interface) caused by the interruption. In such a case, the buffer layer 2 may be removed to some extent in the step of FIG. 13 to form the high resistance impurity injection layer 15 at the interface between the buffer layer 2 and the channel layer 3. Alternatively, the buffer layer 2 may be removed to form the high resistance impurity injection layer 15 on the side (back surface) of the channel layer 3 from which the buffer layer 2 has been removed.

The high resistance impurity injection layer 15 is in a state where peaks other than the epitaxial growth layer 17 and the semiconductor substrate 16 due to defect generation are detected in the X-ray diffraction analysis. Alternatively, the high resistance impurity implantation layer 15 is a region within 300 nm from the surface of the implantation region in cross-section transmission electron microscope observation, and the region has point defects, line defects, stacking defects, etc. with respect to the non-ion implantation region. The density of volume defects has increased 10 times or more. The electrical resistivity of the high resistivity impurity implantation layer 15 is higher than that of a part of the non-ion implantation region. The amount of increase in point defects may be evaluated by the channeling method of Rutherford backscattering.

In the first embodiment, the ions were implanted directly into the buffer layer 2, but the concentration of the ion-implanted ion atoms has a peak in a region of a certain depth from the ion-implanted surface of the semiconductor layer. Therefore, an insulating film (not shown) may be formed on at least a part of the epitaxial growth layer 17a on the side from which the manufacturing semiconductor substrate 1 has been removed, and the high resistance impurity injection layer 15 may be formed after the insulating film is formed. .. According to such a configuration, an ion concentration peak such as Ar ion can be formed in the vicinity of the back surface of the buffer layer 2. The insulating film may be, for example, a SiN film having a thickness of several nm to several tens of nm formed by PECVD or the like. The peak ion concentration can also be controlled by the accelerated energy of ion implantation. After ion implantation, the SiN film may be removed by hydrofluoric acid treatment or the like. Further, regardless of whether or not an insulating film is formed, the ion concentration (impurity concentration) of the high resistance impurity implantation layer 15 from the side (back surface) where the high resistance impurity implantation layer 15 of the epitaxial growth layer 17 is formed by ion implantation. ) May be removed up to the highest part. According to such a configuration, a region having a relatively low resistance on the back surface side of the epitaxial growth layer 17a and the interfacial impurities 12 can be removed. In the configuration in which the region having a relatively low resistance is removed in this way, the parasitic capacitance of the transistor can be reduced and the characteristics can be improved as compared with the configuration in which the region is not removed. Further, after the high resistance impurity injection layer 15 is formed, a plurality of semiconductor elements may be separated by dicing.

Next, as shown in FIG. 15, a semiconductor substrate 16 made of a different material from the epitaxial growth layer 17 is bonded to the side (back surface) of the epitaxial growth layer 17 on which the high resistance impurity injection layer 15 is formed. In the first embodiment, as the semiconductor substrate 16, for example, a diamond layer having a thickness of 100 μm is formed on a silicon substrate, and the surface roughness (for example, root mean square roughness Rq) of the diamond layer is reduced to 1 nm or less by precision polishing. A substrate is used. When all the semiconductor substrates 1 for manufacturing are removed and the semiconductor substrate 16 having high thermal conductivity is bonded to the entire back surface of the epitaxial growth layer 17, the thermal resistance can be lowered and the cooling effect can be enhanced. ..

For the bonding between the epitaxial growth layer 17 and the semiconductor substrate 16, for example, room temperature bonding is used. Specifically, in the vacuum chamber, the polished surface of the epitaxial growth layer 17 and the diamond bonding surface on the semiconductor substrate 16 side are irradiated with an argon ion beam to remove (clean) the oxides on the surfaces. After that, the surfaces from which the oxides have been removed are aligned with each other, and the surfaces are brought into contact with each other and pressed in a vacuum to perform room temperature bonding.

After that, the support substrate 21, the peeling layer 20, the adhesive layer 19, and the adhesive protective layer 18 are peeled (removed) from the structure formed by the steps so far by the steps described below.

First, as shown in FIG. 16, the release layer 20 and the support substrate 21 are separated by irradiating the release layer 20 with light and heat-decomposing the release layer 20. In the first embodiment, the resin of the release layer 20 is thermally decomposed by irradiating the structure formed by the previous steps with light from the support substrate 21 side, and the support substrate 21 together with the release layer 20 is decomposed. To peel off. For light irradiation, for example, a laser that scans the entire surface of the release layer 20 is used. By irradiating the release layer 20 with a laser, carbon or the like in the release layer 20 absorbs light, is heated, and is thermally decomposed. As a result, the adhesive force (adhesiveness, adhesive force, adhesiveness) between the support substrate 21 and the adhesive layer 19 is reduced, so that the release layer 20 and the support substrate 21 can be easily peeled off.

Next, as shown in FIG. 17, the adhesive layer 19 is peeled off by heat treatment. Since the adhesive layer 19 is firmly adhered to the adhesive protective layer 18, the adhesive layer 19 cannot be peeled off using the adhesive tape. Therefore, a heat treatment is performed in order to reduce the adhesive force between the adhesive layer 19 and the adhesive protective layer 18 and peel them off. By this heat treatment, the organic component is released as a gas from the adhesive layer 19 and the adhesive protective layer 18, and the adhesive force between the adhesive layer 19 and the adhesive protective layer 18 is reduced, so that the adhesive layer 19 can be peeled off.

The temperature of the heat treatment may be higher than the curing temperature at which the adhesive protective layer 18 is formed. For example, when the adhesive protective layer 18 cured at 90 ° C. using a hot plate is heated on the hot plate set at 200 ° C. for 10 minutes, the adhesive layer 19 can be easily peeled off. Here, when the heating temperature for peeling the adhesive layer 19 is lower than 150 ° C., the release of gas is small, so that the adhesive force does not decrease significantly, and a large force is required for peeling the adhesive layer 19. Become. On the contrary, if the heating temperature for peeling the adhesive layer 19 greatly exceeds 220 ° C., deformation such as warpage of the semiconductor element occurs, which causes breakage and cracks in the subsequent peeling step. Therefore, the heating temperature for peeling the adhesive layer 19 is preferably 170 to 220 ° C., for example. After the heat treatment, the adhesive layer 19 can be easily peeled off without residue by attaching an adhesive tape to the adhesive layer 19 and peeling it.

Finally, the adhesive protective layer 18 is peeled off by a chemical treatment. The peeling is performed, for example, by immersing the adhesive protective layer 18 in a peeling liquid such as an alkaline, acidic, or organic solvent and decomposing it. After removing the adhesive protective layer 18, the semiconductor element is washed and dried to form the structure of the heterojunction field effect transistor shown in FIG. After that, a heterojunction field effect transistor as a semiconductor device is completed through a process of forming wiring, via holes, and the like.

<Summary of Embodiment 1>
FIG. 18 shows the results of actual measurement of the distribution of impurity concentrations in the heterojunction field effect transistor (hereinafter referred to as “related transistor”) related to the first embodiment by secondary ion mass spectrometry (SIMS). It is a figure which shows. The related transistor includes a substrate corresponding to the semiconductor substrate 1 for manufacturing and an epitaxial growth layer corresponding to the epitaxial growth layer 17a without the high resistance impurity injection layer 15. FIG. 18 shows the concentration distribution of Si, which is a donor-type impurity, and C, which is an acceptor-type impurity. The horizontal axis represents the depth from the upper surface of the epitaxial growth layer, and the vertical axis represents the concentration.

In FIG. 18, it is shown that Si and C are segregated and aggregated at the position of the interface between the substrate and the epitaxial growth layer (the position where the depth is about 1.4 μm). At the interface, the peak concentration of the donor-type impurity (Si) is about two orders of magnitude higher than the peak concentration of the acceptor-type impurity (C).

FIG. 19 is a diagram showing the relationship between the difference in peak concentrations of C and Si and the magnitude of the buffer leak current. FIG. 19 shows that the buffer leak current increases when the peak concentration of Si becomes larger than the peak concentration of C. Therefore, as described above, when the peak concentration of the donor type impurity (Si) is about two orders of magnitude higher than the peak concentration of the acceptor type impurity (C), the buffer leak current at the interface becomes relatively large. .. It is considered that the agglutination of impurities occurs as a result of incorporating impurities derived from atmospheric transport until the substrate is introduced into the epitaxial growth furnace and impurities derived from the atmosphere when the epitaxial growth layer is grown.

In view of the above, in the first embodiment, ion implantation of an acceptor-type impurity such as Ar is performed on at least a part of the epitaxial growth layer 17a on the side from which the manufacturing semiconductor substrate 1 is removed. The high resistance impurity implantation layer 15 formed by this ion implantation reduces the difference between the peak concentration of donor-type impurities and the peak concentration of acceptor-type impurities, and increases the electrical resistance. According to such a configuration, the buffer leak can be suppressed and the transistor characteristics can be improved.

In FIG. 1, the high resistance impurity injection layer 15 is arranged only at the interface between the semiconductor substrate 16 and the buffer layer 2, but is not limited to this. For example, as described above, when the lattice strain relaxation layer is inserted, the high resistance impurity injection layer 15 may be arranged at the interface between the buffer layer 2 and the channel layer 3.

In the present invention, the embodiments can be appropriately modified or omitted within the scope of the invention.

1 Semiconductor substrate for manufacturing, 15 High resistance impurity injection layer, 16 Semiconductor substrate, 17, 17a epitaxial growth layer.

Claims (6)

Nitride semiconductor epitaxial layer and
A semiconductor substrate bonded to the nitride semiconductor epitaxial layer and having a material different from that of the nitride semiconductor epitaxial layer is provided.
The nitride semiconductor epitaxial layer has an impurity region which is an ion implantation region on the semiconductor substrate side.
The impurity region is a semiconductor device having a higher impurity concentration and electrical resistance than a portion of the nitride semiconductor epitaxial layer adjacent to the impurity region. A nitride semiconductor epitaxial layer is formed on a semiconductor substrate for manufacturing,
The manufacturing semiconductor substrate is removed, or the manufacturing semiconductor substrate and the portion of the nitride semiconductor epitaxial layer adjacent to the manufacturing semiconductor substrate are removed.
An impurity region is formed by implanting ions into at least a part of the nitride semiconductor epitaxial layer on the side from which the manufacturing semiconductor substrate has been removed.
A method for manufacturing a semiconductor device, wherein the impurity region has a higher impurity concentration and electrical resistance than a portion of the nitride semiconductor epitaxial layer adjacent to the impurity region. The method for manufacturing a semiconductor device according to claim 2.
A method for manufacturing a semiconductor device, which removes from the side of the nitride semiconductor epitaxial layer on which the impurity region is formed to the portion of the impurity region having the highest impurity concentration. The method for manufacturing a semiconductor device according to claim 2.
An insulating film is formed on at least a part of the nitride semiconductor epitaxial layer on the side from which the manufacturing semiconductor substrate has been removed.
A method for manufacturing a semiconductor device, which forms the impurity region after forming the insulating film. The method for manufacturing a semiconductor device according to claim 2.
A method for manufacturing a semiconductor device, in which a semiconductor substrate made of a material different from that of the nitride semiconductor epitaxial layer is bonded to the side of the nitride semiconductor epitaxial layer on which the impurity region is formed. The field effect transistor which is the semiconductor device according to claim 1.

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