TW201737352A - Device and method for producing a lateral HEMT - Google Patents
Device and method for producing a lateral HEMT Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title description 6
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- 229910052751 metal Inorganic materials 0.000 claims description 15
- 239000002184 metal Substances 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 13
- 238000005530 etching Methods 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 97
- 239000000463 material Substances 0.000 description 6
- 230000015556 catabolic process Effects 0.000 description 5
- 230000005684 electric field Effects 0.000 description 5
- 230000017525 heat dissipation Effects 0.000 description 5
- 238000009413 insulation Methods 0.000 description 5
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- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 4
- 239000011241 protective layer Substances 0.000 description 4
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
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- 230000008021 deposition Effects 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
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- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
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- 230000000593 degrading effect Effects 0.000 description 1
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- 229910052737 gold Inorganic materials 0.000 description 1
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- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
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- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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Abstract
Description
本發明係關於裝置及製造橫向HEMT的方法。 The present invention relates to devices and methods of fabricating lateral HEMTs.
橫向高電子遷移率電晶體HEMT藉由(例如)AlGaN/GaN或InGaN/GaN或AlN/GaN異質結構之沉積而沉積於諸如藍寶石、SiC或Si的基板上。在此情況下,在Si上沉積GaN引起生長的GaN層中的高負載,此係由於Si與GaN之間的大的晶格不匹配。此外,矽在用於生長GaN的典型溫度下(通常在1000℃至1200℃範圍內)變得機械不穩定。為了減小此等負載,供製造此等HEMT電晶體,使用具有立方面心晶格結構(具有{111}平面)的摻雜Si進行GaN之沉積。此處不利的是出現高基板漏電流。此外,不利的是此等HEMT電晶體之崩潰電壓限制組件的熱耦合,結果熱耗散受到限制。為改良來自電晶體的熱耗散,文件DE 10 2013 211 374 A1描述絕緣層及背面金屬化物的使用。然而,熱耗散仍受到絕緣層之厚度的限制。 The lateral high electron mobility transistor HEMT is deposited on a substrate such as sapphire, SiC or Si by deposition of, for example, AlGaN/GaN or InGaN/GaN or AlN/GaN heterostructures. In this case, depositing GaN on Si causes a high load in the grown GaN layer due to a large lattice mismatch between Si and GaN. In addition, germanium becomes mechanically unstable at typical temperatures for growing GaN, typically in the range of 1000 ° C to 1200 ° C. In order to reduce these loads, for the fabrication of such HEMT transistors, the deposition of GaN is performed using doped Si having a vertical aspect lattice structure (having a {111} plane). The disadvantage here is that high substrate leakage current occurs. Furthermore, it is disadvantageous that the thermal coupling of the breakdown voltage limiting components of such HEMT transistors results in limited thermal dissipation. In order to improve the heat dissipation from the crystal, the use of the insulating layer and the back metallization is described in the document DE 10 2013 211 374 A1. However, heat dissipation is still limited by the thickness of the insulating layer.
已知藉由局部地移除主動電晶體區之下方的基板來提高崩潰電壓,且消除基板漏電流。此處不利的是半導體之背面至電路板或板的熱耦合較不良,(例如)此係因為部分移除的基板配置於導熱耦合件與半導體之間,結果更加無法充分地耗散來自組件的熱。 It is known to increase the breakdown voltage by locally removing the substrate under the active transistor region and to eliminate substrate leakage current. The disadvantage here is that the thermal coupling of the back side of the semiconductor to the circuit board or board is poor, for example, because the partially removed substrate is disposed between the thermally conductive coupling and the semiconductor, and as a result, the component is not sufficiently dissipated. heat.
本發明之目標在於改良電晶體的崩潰特性及熱耗散。 The object of the present invention is to improve the collapse characteristics and heat dissipation of the transistor.
裝置包含橫向HEMT,該橫向HEMT包含至少一個緩衝層,在該緩衝層上配置另一半導體層。第一電極、閘極電極及第二電極配置於半導體層上。根據本發明,第一場板配置在該緩衝層之下方,其中該第一場板至少部分地直接鄰接該緩衝層。 The device comprises a lateral HEMT comprising at least one buffer layer on which another semiconductor layer is disposed. The first electrode, the gate electrode, and the second electrode are disposed on the semiconductor layer. According to the invention, the first field plate is disposed below the buffer layer, wherein the first field plate at least partially directly adjoins the buffer layer.
此處優點為電晶體的鎖定及切換特性經改良,結果提高了電晶體的崩潰電壓。 The advantage here is that the locking and switching characteristics of the transistor are improved, resulting in an increase in the breakdown voltage of the transistor.
在一個發展中,第一場板具有至少一個階梯,其中該階梯實質上垂直於該緩衝層而配置。 In one development, the first field plate has at least one step, wherein the step is configured substantially perpendicular to the buffer layer.
此處有利的是第一場板可與第二電極(所謂的汲極電極)絕緣,以使得實現高反向電壓。 It is advantageous here that the first field plate can be insulated from the second electrode (so-called drain electrode) such that a high reverse voltage is achieved.
在另一組態中,該階梯配置於閘極電極之下方。 In another configuration, the step is disposed below the gate electrode.
在一個發展中,該階梯配置於閘極電極之基點之下方,其中該基點配置於閘極電極面向第二電極的一側處。 In one development, the step is disposed below a base point of the gate electrode, wherein the base point is disposed at a side of the gate electrode facing the second electrode.
此處優點為第一場板相對於緩衝層的接觸長度與絕緣層之長度之間的比率係可調整的,以使得在高熱耗散與高阻斷能力之間實現最佳。 The advantage here is that the ratio between the contact length of the first field plate relative to the buffer layer and the length of the insulating layer is adjustable to achieve an optimum between high heat dissipation and high blocking capability.
在一個發展中,第一電極表示源極電極且第二電極表示汲極電極。 In one development, the first electrode represents the source electrode and the second electrode represents the drain electrode.
在另一組態中,第一絕緣層配置在緩衝層之下方,其中該第一絕緣層至少部分地直接鄰接緩衝層。 In another configuration, the first insulating layer is disposed below the buffer layer, wherein the first insulating layer at least partially directly adjoins the buffer layer.
此處有利的是來自HEMT的熱耗散得到改良。 It is advantageous here that the heat dissipation from the HEMT is improved.
在一個發展中,第一絕緣層具有至少自閘極電極(尤其,自該閘極電極之基點)延伸直至第二電極的橫向長度。 In one development, the first insulating layer has a lateral length extending at least from the gate electrode (especially from the base point of the gate electrode) up to the second electrode.
此處優點為動態導通電阻低,此係因為第一場板位於空間鄰近於第二電極的位置,從而影響了其間的電場。此處術語導通電阻理解為意謂源極與漏極之間的電阻,該電阻在HEMT的動態接通及關斷的情況下產生。 The advantage here is that the dynamic on-resistance is low because the first field plate is located in a space adjacent to the second electrode, thereby affecting the electric field therebetween. The term on-resistance is understood here to mean the resistance between the source and the drain, which is produced with the dynamic turn-on and turn-off of the HEMT.
在另一組態中,第一絕緣層經設計以構造第一場板。在此情況下,第一場板部分地配置於第一絕緣層之下方且部分地直接鄰接第一絕緣層。 In another configuration, the first insulating layer is designed to construct a first field plate. In this case, the first field plate is partially disposed below the first insulating layer and partially directly adjacent to the first insulating layer.
此處優點為在組件內形成的場尖峰被移入絕緣層,以使得可減小絕緣層內的場尖峰且並不因此降低組件的效能或可靠性。結果,在極端情況下防止組件的損壞。 The advantage here is that the field spikes formed within the assembly are moved into the insulating layer such that field spikes within the insulating layer can be reduced without thereby degrading the performance or reliability of the assembly. As a result, damage to the components is prevented in extreme cases.
在另一組態中,經構造的摻雜半導體基板至少部分地配置在緩衝層之下方。在此情況下,經構造的摻雜半導體基板直接鄰接緩衝層。 In another configuration, the structured doped semiconductor substrate is at least partially disposed below the buffer layer. In this case, the structured doped semiconductor substrate directly adjoins the buffer layer.
此處有利的是HEMT內的漏電流減小。 It is advantageous here that the leakage current in the HEMT is reduced.
在一個發展中,第一通孔配置於第一電極與第一場板之間。術語通孔理解為意謂垂直電連接。在此情況下,該第一通孔電連接第一電極及第一場板。 In one development, the first via is disposed between the first electrode and the first field plate. The term through hole is understood to mean a vertical electrical connection. In this case, the first via is electrically connected to the first electrode and the first field plate.
此處優點為第一電極及第一場板具有相同的電位。結果,在切換程序期間可更快速地清除在高反向電壓下由電負載產生的充電缺陷。由於切換程序快速進行,因此HEMT的高效切換係可能的。此外,電場分佈(尤其,在場板上)以靶向方式變化,以使得組件的動態效能得到改良。 The advantage here is that the first electrode and the first field plate have the same potential. As a result, charging defects generated by the electrical load at high reverse voltages can be cleared more quickly during the switching process. Since the switching procedure is fast, efficient switching of the HEMT is possible. In addition, the electric field distribution (especially on the field plate) is varied in a targeted manner to improve the dynamic performance of the assembly.
在另一組態中,閘極電極包含第二場板,其中該第二場板配置於閘極電極的正上方且至少沿第一電極之方向橫向延伸。 In another configuration, the gate electrode includes a second field plate, wherein the second field plate is disposed directly above the gate electrode and extends laterally at least in a direction of the first electrode.
此處有利的是可調節主動電晶體區中的場分佈。第一絕緣層之構造能夠以可變之方式設定自場板至漏極側的距離及自場板至緩衝層的距離,以使得可以靶向方式控制組件中的電場分佈。在此情況下,最大電場強度移位至絕緣層內的場板邊緣。 It is advantageous here to adjust the field distribution in the active transistor region. The configuration of the first insulating layer can variably set the distance from the field plate to the drain side and the distance from the field plate to the buffer layer so that the electric field distribution in the component can be controlled in a targeted manner. In this case, the maximum electric field strength is shifted to the edge of the field plate within the insulating layer.
在一種發展中,背面電極配置在緩衝層之下方,在絕緣層內距緩衝層一垂直距離處。在此情況下,第二通孔將背面電極電連接至第二場板,以使得形成背面空腔。 In one development, the back electrode is disposed below the buffer layer at a vertical distance from the buffer layer within the insulating layer. In this case, the second through hole electrically connects the back electrode to the second field plate such that a back cavity is formed.
此處優點為可設定閘極電壓或閘極-源極電壓(所謂的臨限電壓),在該閘極電壓或閘極-源極電壓下電晶體自關斷狀態改變為接通狀態,或反之亦然。結果,(例如)可操作通常接通的組件及通常關斷的組件兩者。 The advantage here is that the gate voltage or the gate-source voltage (so-called threshold voltage) can be set, and the transistor changes from the off state to the on state at the gate voltage or the gate-source voltage, or vice versa. As a result, for example, both a normally-on component and a normally-off component can be operated.
根據用於製造包含至少一個緩衝層之橫向HEMT的本發明的方法,在該緩衝層上配置另一半導體層,其中第一電極、閘極電極及第二電極配置於另一半導體層上且緩衝層配置於摻雜半導體基板之正面,其中該摻雜半導體基板具有與該正面相對定位的背面,該方法包含藉由處理或蝕刻該摻雜半導體基板之該背面至少部分地移除該摻雜半導體基板。此外,該方法包含以構造方式於緩衝層之下方施加第一絕緣層,以使得該第一絕緣層具有在閘極電極之基點與第二電極之間延伸的橫向長度。此外該方法包含在緩衝層及第一絕緣層之下方製造第一金屬層,以使得形成第一場板。 According to the method of the invention for fabricating a lateral HEMT comprising at least one buffer layer, another semiconductor layer is disposed on the buffer layer, wherein the first electrode, the gate electrode and the second electrode are disposed on the other semiconductor layer and buffered a layer disposed on a front surface of the doped semiconductor substrate, wherein the doped semiconductor substrate has a back surface positioned opposite the front surface, the method comprising at least partially removing the doped semiconductor by processing or etching the back surface of the doped semiconductor substrate Substrate. Additionally, the method includes applying a first insulating layer under the buffer layer in a structured manner such that the first insulating layer has a lateral length extending between a base point of the gate electrode and the second electrode. Additionally, the method includes fabricating a first metal layer below the buffer layer and the first insulating layer such that a first field plate is formed.
此處優點為電晶體具有高崩潰電壓。 The advantage here is that the transistor has a high breakdown voltage.
另一優點自以下例示性具體實例之描述及/或自附屬專利申請專利範圍中顯而易見。 Another advantage is apparent from the following description of exemplary embodiments and/or from the scope of the appended patent application.
100‧‧‧第一裝置 100‧‧‧ first device
101‧‧‧緩衝層 101‧‧‧buffer layer
102‧‧‧另一半導體層 102‧‧‧ another semiconductor layer
103‧‧‧第一電極 103‧‧‧First electrode
104‧‧‧閘極電極 104‧‧‧gate electrode
105‧‧‧第二電極 105‧‧‧second electrode
107‧‧‧閘極介電質 107‧‧‧gate dielectric
108‧‧‧第一絕緣層 108‧‧‧First insulation
109‧‧‧第一場板 109‧‧‧ first board
116‧‧‧基點 116‧‧‧ base point
118‧‧‧階梯 118‧‧‧ ladder
200‧‧‧第二裝置 200‧‧‧second device
201‧‧‧緩衝層 201‧‧‧buffer layer
202‧‧‧另一半導體層 202‧‧‧ another semiconductor layer
203‧‧‧第一電極 203‧‧‧First electrode
204‧‧‧閘極電極 204‧‧‧gate electrode
205‧‧‧第二電極 205‧‧‧second electrode
208‧‧‧第一絕緣層 208‧‧‧first insulation
209‧‧‧第一場板 209‧‧‧ first board
210‧‧‧摻雜矽基板/經構造的矽基板/經構造的摻雜半導體基板 210‧‧‧Doped germanium substrate/structured germanium substrate/structured doped semiconductor substrate
216‧‧‧基點 216‧‧‧ base point
218‧‧‧階梯 218‧‧‧ ladder
300‧‧‧第三裝置 300‧‧‧ third device
301‧‧‧緩衝層 301‧‧‧buffer layer
302‧‧‧另一半導體層 302‧‧‧ another semiconductor layer
303‧‧‧第一電極 303‧‧‧First electrode
304‧‧‧閘極電極 304‧‧‧gate electrode
305‧‧‧第二電極 305‧‧‧second electrode
308‧‧‧第一絕緣層 308‧‧‧First insulation
309‧‧‧第一場板 309‧‧‧ first board
311‧‧‧通孔 311‧‧‧through hole
316‧‧‧基點 316‧‧‧ base point
318‧‧‧階梯 318‧‧‧ ladder
400‧‧‧第四裝置/橫向HEMT 400‧‧‧Fourth Device/Horizontal HEMT
401‧‧‧緩衝層 401‧‧‧buffer layer
402‧‧‧另一半導體層/第二層 402‧‧‧Another semiconductor layer/second layer
403‧‧‧第一電極 403‧‧‧First electrode
404‧‧‧閘極電極 404‧‧‧gate electrode
405‧‧‧汲極電極 405‧‧‧汲electrode
407‧‧‧閘極介電質 407‧‧‧gate dielectric
408‧‧‧第一絕緣層 408‧‧‧First insulation
412‧‧‧第二場板 412‧‧‧ second board
416‧‧‧基點 416‧‧‧ base point
420‧‧‧通孔 420‧‧‧through hole
421‧‧‧區 421‧‧‧ District
422‧‧‧區 422‧‧‧ District
423‧‧‧背面電極 423‧‧‧Back electrode
424‧‧‧第二通孔 424‧‧‧Second through hole
1020、1030、1040、1050、1060、1070、1080、1090、1100、1110、1120、1130、1140、1150‧‧‧步驟 1020, 1030, 1040, 1050, 1060, 1070, 1080, 1090, 1100, 1110, 1120, 1130, 1140, 1150‧‧ steps
本發明基於較佳具體實例及隨附圖式在下文中加以解釋,其中:圖1展示根據本發明之第一裝置,圖2展示根據本發明之第二裝置,圖3展示根據本發明之第三裝置,圖4展示根據本發明之第四裝置,且圖5展示根據本發明之用於製造裝置的方法。 The invention is explained below based on preferred embodiments and with the accompanying drawings in which: Figure 1 shows a first device according to the invention, Figure 2 shows a second device according to the invention, Figure 3 shows a third device according to the invention Apparatus, Figure 4 shows a fourth apparatus in accordance with the present invention, and Figure 5 shows a method for manufacturing a apparatus in accordance with the present invention.
圖1展示根據本發明之包含橫向HEMT的第一裝置100。在此情況下,橫向HEMT包含緩衝層101,該緩衝層包含第一半導體材料。包含第二半導體材料的另一半導體層102配置於緩衝層101上,其中該第二半導體材料具有不同於第一半導體材料之電子遷移率的電子遷移率。換言之,由於第一半導體材料及第二半導體材料不同,因此形成異質結構。第一電極103、閘極電極104及第二電極105配置於另一半導體層102上。閘極介電質107視情況配置於另一半導體層102上。絕緣保護層配置於第一電極103、閘極電極104及第二電極105上,且保護電極103、104及105免受機械影響。第一場板109配置於緩衝層101之下方。該場板藉由第一絕緣層108成形。 1 shows a first device 100 including a lateral HEMT in accordance with the present invention. In this case, the lateral HEMT comprises a buffer layer 101 comprising a first semiconductor material. Another semiconductor layer 102 comprising a second semiconductor material is disposed on the buffer layer 101, wherein the second semiconductor material has an electron mobility that is different from the electron mobility of the first semiconductor material. In other words, since the first semiconductor material and the second semiconductor material are different, a heterostructure is formed. The first electrode 103, the gate electrode 104, and the second electrode 105 are disposed on the other semiconductor layer 102. The gate dielectric 107 is disposed on the other semiconductor layer 102 as appropriate. The insulating protective layer is disposed on the first electrode 103, the gate electrode 104, and the second electrode 105, and the protective electrodes 103, 104, and 105 are protected from mechanical influence. The first field plate 109 is disposed below the buffer layer 101. The field plate is formed by a first insulating layer 108.
圖2展示根據本發明之包含橫向HEMT的第二裝置200。在此情況下,與圖1之參考符號之尾數相同的參考符號之尾數表示相同的特徵。場板209、摻雜矽基板210之經構造的區及第一絕緣層208配置於緩衝層201之下方。在此情況下,第一場板209的形狀藉由經構造的矽基板210及第一絕緣層208成形。 2 shows a second device 200 including a lateral HEMT in accordance with the present invention. In this case, the mantissa of the same reference numeral as the reference number of the reference symbol of FIG. 1 indicates the same feature. The field plate 209, the structured region of the doped germanium substrate 210, and the first insulating layer 208 are disposed below the buffer layer 201. In this case, the shape of the first field plate 209 is formed by the structured ruthenium substrate 210 and the first insulating layer 208.
圖3展示根據本發明之包含橫向HEMT的第三裝置300。在此情況下,與圖1及圖2之參考符號之尾數相同的參考符號之尾數表示相同的特徵。第一場板309配置於緩衝層301之下方。通孔311電連接第一電極303及第一場板309。 3 shows a third device 300 including a lateral HEMT in accordance with the present invention. In this case, the mantissa of the same reference numerals as the reference numerals of FIGS. 1 and 2 denote the same features. The first field plate 309 is disposed below the buffer layer 301. The through hole 311 electrically connects the first electrode 303 and the first field plate 309.
在一個例示性具體實例中,橫向HEMT之第一場板109、209及309具有垂直於緩衝層101、201及301配置的階梯。該階梯118、218及318為實質上垂直的;此意謂考慮到製造公差。 In an illustrative embodiment, the first field plates 109, 209, and 309 of the lateral HEMT have steps that are perpendicular to the configuration of the buffer layers 101, 201, and 301. The steps 118, 218 and 318 are substantially vertical; this means that manufacturing tolerances are taken into account.
視情況,階梯118、218及318配置於閘極電極104、204及304之下方。在此情況下,閘極電極104、204及304之基點116、216及316配置於閘極電極104、204及304面向第二電極105、205及305的一側處。在另一可選例示性具體實例中,階梯118、218及318配置於閘極電極104、204及304面向第一電極103、203及303的基點處。 Steps 118, 218, and 318 are disposed below gate electrodes 104, 204, and 304, as appropriate. In this case, the base points 116, 216, and 316 of the gate electrodes 104, 204, and 304 are disposed at the side of the gate electrodes 104, 204, and 304 facing the second electrodes 105, 205, and 305. In another alternative exemplary embodiment, the steps 118, 218, and 318 are disposed at base points of the gate electrodes 104, 204, and 304 facing the first electrodes 103, 203, and 303.
在一個例示性具體實例中,第一電極103、203及303為源極電極且第二電極105、205及305為汲極電極。 In an illustrative embodiment, first electrodes 103, 203, and 303 are source electrodes and second electrodes 105, 205, and 305 are drain electrodes.
在另一例示性具體實例中,第一絕緣層具有至少自閘極電極104、204及304之基點116、216及316延伸直至第二電極105、205及305的橫向長度。彼情形意謂第一絕緣層108、208及308亦可覆蓋第二電極105、 205及305。 In another exemplary embodiment, the first insulating layer has a lateral length extending at least from the base points 116, 216, and 316 of the gate electrodes 104, 204, and 304 up to the second electrodes 105, 205, and 305. In other instances, the first insulating layers 108, 208, and 308 may also cover the second electrode 105, 205 and 305.
由於摻雜半導體基板210至少部分地配置於緩衝層101、201及301之下方,因此該摻雜半導體基板210首先使第一絕緣層108、208及308成形,其中第一場板109、209及309接著一方面藉由經構造的摻雜半導體基板210且藉由第一絕緣層108、208及308成形。 Since the doped semiconductor substrate 210 is at least partially disposed under the buffer layers 101, 201, and 301, the doped semiconductor substrate 210 first shapes the first insulating layers 108, 208, and 308, wherein the first field plates 109, 209 and 309 is then formed on the one hand by the structured doped semiconductor substrate 210 and by the first insulating layers 108, 208 and 308.
圖4展示根據本發明之包含橫向HEMT的第四裝置400。橫向HEMT具有緩衝層401,在該緩衝層上配置另一半導體層402。第一電極403、閘極電極404及汲極電極405配置於另一半導體層402上。視情況,閘極介電質407配置於第二層402上。閘極電極404具有第二場板412,該第二場板自閘極電極404沿源極電極403之方向橫向延伸。在此情況下,橫向HEMT 400具有分離源極場板,該分離源極場板藉由通孔420連接至源極電極403。分離源極場板包含區421及區422。此外,橫向HEMT 400具有背面電極423,該背面電極藉助於第二通孔424電連接至第二場板412。分離源極場板及背面電極423兩者均藉由第一絕緣層408成形。 4 shows a fourth device 400 including a lateral HEMT in accordance with the present invention. The lateral HEMT has a buffer layer 401 on which another semiconductor layer 402 is disposed. The first electrode 403, the gate electrode 404, and the drain electrode 405 are disposed on the other semiconductor layer 402. The gate dielectric 407 is disposed on the second layer 402 as appropriate. The gate electrode 404 has a second field plate 412 that extends laterally from the gate electrode 404 in the direction of the source electrode 403. In this case, the lateral HEMT 400 has a split source field plate that is connected to the source electrode 403 by a via 420. The split source field plate includes a region 421 and a region 422. Furthermore, the lateral HEMT 400 has a back electrode 423 that is electrically connected to the second field plate 412 by means of a second via 424. Both the split source field plate and the back electrode 423 are formed by the first insulating layer 408.
在一個例示性具體實例中,緩衝層101、201、301及401包含GaN。另一半導體層102、202、302及402包含AlGaN或InGaN或AIN。 In an exemplary embodiment, buffer layers 101, 201, 301, and 401 comprise GaN. The other semiconductor layers 102, 202, 302, and 402 include AlGaN or InGaN or AIN.
舉例而言,第一絕緣層108、208、308及408包含氧化矽或SiN。 For example, the first insulating layers 108, 208, 308, and 408 comprise hafnium oxide or SiN.
第一場板109、209及309為金屬,其中該金屬具有高熱導率,以視情況使將第一場板用作額外電極成為可能。舉例而言,金屬為銅、鋁、鈦、鎳、銀或金。第一場板109、209及309亦可由多個金屬之堆疊而構造。舉例而言,半導體基板210為摻雜Si或SiC。 The first field plates 109, 209, and 309 are metals, wherein the metal has a high thermal conductivity, making it possible to use the first field plate as an additional electrode, as appropriate. For example, the metal is copper, aluminum, titanium, nickel, silver or gold. The first field plates 109, 209, and 309 can also be constructed from a stack of multiple metals. For example, the semiconductor substrate 210 is doped with Si or SiC.
圖5展示用於製造包含橫向HEMT之裝置的方法。在此情況下,在HEMT之背面上(亦即,在背對電極的一側上)執行方法。因此涉及背面處理程序。方法開始於步驟1030,藉由處理或蝕刻摻雜半導體基板之背面至少部分地移除橫向HEMT的摻雜半導體基板。在後續步驟1060中,於摻雜半導體基板之背面上施加及構造第一絕緣層,以使得第一絕緣層具有至少在閘極電極之基點與第二電極之間延伸的橫向長度。 Figure 5 shows a method for fabricating a device comprising a lateral HEMT. In this case, the method is performed on the back side of the HEMT (i.e., on the side facing away from the electrode). So it involves the backside processing. The method begins in step 1030 by at least partially removing a doped semiconductor substrate of a lateral HEMT by processing or etching the backside of the doped semiconductor substrate. In a subsequent step 1060, a first insulating layer is applied and configured on the back side of the doped semiconductor substrate such that the first insulating layer has a lateral length that extends at least between the base point of the gate electrode and the second electrode.
在另一例示性具體實例中,絕緣層並不完全延伸至閘極電極。 In another illustrative embodiment, the insulating layer does not extend completely to the gate electrode.
在後續步驟1070中,於緩衝層及第一絕緣層上施加及構造第一金屬層,以使得形成第一場板。 In a subsequent step 1070, a first metal layer is applied and configured over the buffer layer and the first insulating layer such that a first field plate is formed.
在外基板上施加受保護層保護的HEMT(亦即,具有電極的一側)。此舉有助於對橫向HEMT的處理。視情況,在步驟1150中之製造方法結束時可移除外基板。 A HEMT protected by a protective layer (i.e., a side having electrodes) is applied to the outer substrate. This will help with the processing of the lateral HEMT. Optionally, the outer substrate can be removed at the end of the manufacturing process in step 1150.
在另一例示性具體實例中,在步驟1030及步驟1060之間執行另一步驟。在此情況下,步驟1040緊接在步驟1030之後,其中步驟1040涉及藉助於乾式蝕刻移除第一電極之區中包含緩衝層及另一半導體層的異質結構。結果亦藉由在步驟1070中施加第二金屬層填充鍍覆穿孔。 In another illustrative embodiment, another step is performed between step 1030 and step 1060. In this case, step 1040 is immediately after step 1030, wherein step 1040 involves removing the heterostructure comprising the buffer layer and the other semiconductor layer in the region of the first electrode by means of dry etching. The result is also filled by plating the perforations by applying a second metal layer in step 1070.
在另一例示性具體實例中,在可選步驟1040之後,將藉由移除第一電極之區直至正面之保護層來執行另一步驟1050。在執行步驟1060及步驟1070之後,隨之進行另一步驟1080,其中構造第一金屬層,以使得閘極電極與汲極電極之間的路徑之下方的區曝露。後續步驟1090涉及移除第一電極之下方的區中的第一金屬層,因此產生用於第二通孔的區。 後續步驟1100涉及將第二絕緣層施加於閘極電極與汲極電極之間的路徑之下方的區中。後續步驟1110涉及移除源極極觸點之下方的區中的第二絕緣層。後續步驟1120涉及施加第二金屬層,且後續步驟1130涉及施加第三絕緣層。後續步驟1140涉及施加第三金屬層。由於現由第一金屬層、第二金屬層及第三金屬層組成之分離源極場板的構造,組件中之電場分佈可以靶向方式控制。以此方式,可將最大場強度移位至場板邊緣且因此在第一絕緣層內。此舉減少直至頂面保護層的GaN緩衝層中的峰值場強度。結果,提高電晶體之崩潰電壓且減少電荷反轉缺陷或製造缺陷。因此提高動態效能。同時,提高組件的可靠性。以此方式製造的電晶體可用於(例如)汽車行業中之混合或電動車輛中及(例如)用於實現反相器系統之光伏打之領域中的許多電力電子轉換器中。 In another exemplary embodiment, after optional step 1040, another step 1050 will be performed by removing the region of the first electrode up to the protective layer on the front side. After performing step 1060 and step 1070, a further step 1080 is performed in which the first metal layer is constructed such that the region below the path between the gate electrode and the drain electrode is exposed. Subsequent step 1090 involves removing the first metal layer in the region below the first electrode, thus creating a region for the second via. Subsequent step 1100 involves applying a second insulating layer in a region below the path between the gate electrode and the drain electrode. Subsequent step 1110 involves removing the second insulating layer in the region below the source pole contact. Subsequent step 1120 involves applying a second metal layer, and subsequent step 1130 involves applying a third insulating layer. Subsequent step 1140 involves applying a third metal layer. Due to the configuration of the separated source field plates now composed of the first metal layer, the second metal layer and the third metal layer, the electric field distribution in the assembly can be controlled in a targeted manner. In this way, the maximum field strength can be shifted to the edge of the field plate and thus within the first insulating layer. This reduces the peak field strength in the GaN buffer layer up to the top protective layer. As a result, the breakdown voltage of the transistor is increased and the charge reversal defect or manufacturing defect is reduced. Therefore, the dynamic performance is improved. At the same time, improve the reliability of the components. The transistors fabricated in this manner can be used, for example, in hybrid or electric vehicles in the automotive industry and, for example, in many power electronic converters used in the field of photovoltaics for implementing inverter systems.
100‧‧‧第一裝置 100‧‧‧ first device
101‧‧‧緩衝層 101‧‧‧buffer layer
102‧‧‧另一半導體層 102‧‧‧ another semiconductor layer
103‧‧‧第一電極 103‧‧‧First electrode
104‧‧‧閘極電極 104‧‧‧gate electrode
105‧‧‧第二電極 105‧‧‧second electrode
107‧‧‧閘極介電質 107‧‧‧gate dielectric
108‧‧‧第一絕緣層 108‧‧‧First insulation
109‧‧‧第一場板 109‧‧‧ first board
116‧‧‧基點 116‧‧‧ base point
118‧‧‧階梯 118‧‧‧ ladder
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