CN111565045B

CN111565045B - Comparator and analog-to-digital converter

Info

Publication number: CN111565045B
Application number: CN202010452057.0A
Authority: CN
Inventors: 刘森; 戴彬; 张均安; 李建平; 刘兴龙; 史林森
Original assignee: Micro Niche Guangzhou Semiconductor Co Ltd
Current assignee: Micro Niche Guangzhou Semiconductor Co Ltd
Priority date: 2020-05-26
Filing date: 2020-05-26
Publication date: 2020-11-03
Anticipated expiration: 2040-05-26
Also published as: CN111565045A

Abstract

The invention provides a comparator and an analog-to-digital converter, wherein the comparator comprises: the preamplifier is used for amplifying a group of differential input signals to generate two groups of differential output signals; and the reestablishing latch comprises two reestablishing latch units which are connected with the corresponding output ends of the preamplifier, so that two groups of differential output signals are input into the corresponding reestablishing latch units in a staggered mode to carry out voltage regeneration on staggered input signals. The invention solves the problem that the prior comparator is easy to generate a metastable state.

Description

Comparator and analog-to-digital converter

Technical Field

The present invention relates to the field of integrated circuits, and more particularly, to a comparator and an analog-to-digital converter.

Background

A high-precision Successive Approximation (SAR) ADC is a very common ADC, especially for some high-speed, high-precision and low-power applications. Compared with the Σ -ADC, under the same precision requirement, the SAR ADC bandwidth can be made very high, the power consumption can be made low, and the SAR ADC bandwidth is particularly suitable for the requirements of 12-16 bit precision and throughput rate below 10 MSPS. Compared with a pipeline ADC, the SAR ADC speed is very dominant in power consumption although difficult to match; in addition, as the process size is reduced, the SAR ADC is easier to design, because the key of the pipeline ADC is the gain and bandwidth index of the operational amplifier, when the pipeline ADC enters an advanced process, the intrinsic gain of a transistor is gradually reduced, and the high gain is gradually difficult to ensure under the high bandwidth; the core module of the SAR ADC is a capacitance DAC and a high-speed comparator, and the capacitance value of the capacitor can be reduced by using an advanced process design under the condition of ensuring equal capacitance matching, so that the area is saved, and for the comparator, the advantage that the bandwidth is easier to be increased and the integration is facilitated is achieved. Therefore, SAR ADCs are widely used in MCUs and DSPs.

With the development of applications, people have increasingly strict requirements on the precision and speed of the SAR ADC, and the design of the SAR ADC also faces many challenges, one of which is how to design a high-speed high-precision comparator. The high precision means that the signal to be identified by the comparator is very small, and the high speed means that the comparison time of the comparator is very short, so that a metastable state is very easy to occur in the design, that is, the comparator fails to give a comparison result within a specified time, so that the conversion of the ADC is directly interrupted, and the precision is damaged. Therefore, how to remove the comparator meta-stability is a very critical issue in the SAR ADC design.

Disclosure of Invention

In view of the above-mentioned shortcomings of the prior art, it is an object of the present invention to provide a comparator and an analog-to-digital converter, which are used to solve the problem that the conventional comparator is very prone to metastability.

To achieve the above and other related objects, the present invention provides a comparator, comprising:

the preamplifier is used for amplifying a group of differential input signals to generate two groups of differential output signals;

the reestablishment latch comprises two reestablishment latch units which are connected with the corresponding output ends of the preamplifier, so that two groups of differential output signals are input into the corresponding reestablishment latch units in a staggered mode to carry out voltage regeneration on staggered input signals;

wherein the preamplifier includes: the NMOS transistor comprises a first resistor, a second resistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor and a fourth PMOS transistor; wherein, the gate terminal of the first NMOS transistor and the gate terminal of the second NMOS transistor are connected to the differential input signal, the source terminal of the first NMOS transistor is connected to the source terminal of the second NMOS transistor and the drain terminal of the third NMOS transistor, the drain terminal of the first NMOS transistor is connected to one end of the first resistor and is used as the first output terminal of the preamplifier, the drain terminal of the second NMOS transistor is connected to one end of the second resistor and is used as the second output terminal of the preamplifier, the gate terminal of the third NMOS transistor is connected to the first bias voltage, the source terminal of the third NMOS transistor is grounded, the other end of the first resistor is connected to the drain terminal of the first PMOS transistor and the drain terminal of the second PMOS transistor and is used as the third output terminal of the preamplifier, the other end of the second resistor is connected to the drain terminal of the third PMOS transistor and the drain terminal of the fourth PMOS transistor, meanwhile, the source end of the first PMOS tube is connected with a power supply voltage, the grid end of the first PMOS tube is connected with a second bias voltage, the source end of the second PMOS tube is connected with the power supply voltage, the grid end of the second PMOS tube is connected with the drain end of the fourth PMOS tube, the source end of the third PMOS tube is connected with the power supply voltage, the grid end of the third PMOS tube is connected with the second bias voltage, the grid end of the fourth PMOS tube is connected with the power supply voltage, and the grid end of the fourth PMOS tube is connected with the drain end of the second PMOS tube.

Optionally, the third NMOS transistor is replaced with a current source, where one end of the current source is connected to the source terminal of the first NMOS transistor and the source terminal of the second NMOS transistor, and the other end of the current source is grounded.

Optionally, a clock signal is used to replace the first bias voltage and the second bias voltage, and at this time, the gate terminal of the third NMOS transistor, the gate terminal of the first PMOS transistor, and the gate terminal of the third PMOS transistor are all connected to the clock signal.

Optionally, the circuit structures of the two reestablishing latch units are the same, and both include: the first transmission gate, the second transmission gate, the fourth NMOS transistor, the fifth NMOS transistor, the sixth NMOS transistor, the fifth PMOS transistor, the sixth PMOS transistor and the seventh PMOS transistor; wherein, the input ends of the first transmission gate and the second transmission gate are connected to a group of the staggered input signals output by the preamplifier, two control ends of the first transmission gate and the second transmission gate are connected to a group of clock signals which are in opposite phases, the output end of the first transmission gate is connected to the drain end of the fourth NMOS tube and the drain end of the fifth PMOS tube and is used as the first output end of the reestablishing latch unit, the output end of the second transmission gate is connected to the drain end of the fifth NMOS tube and the drain end of the sixth PMOS tube and is used as the second output end of the reestablishing latch unit, the gate end of the fourth NMOS tube is connected to the drain end of the fifth NMOS tube, the gate end of the fifth NMOS tube is connected to the drain end of the fourth NMOS tube, and the source end of the fourth NMOS tube is connected to the source end of the fifth NMOS tube and the drain end of the sixth NMOS tube, the source terminal of the sixth NMOS tube is grounded, the gate terminal of the fifth PMOS tube is connected to the drain terminal of the sixth PMOS tube, the gate terminal of the sixth PMOS tube is connected to the drain terminal of the fifth PMOS tube, the source terminal of the fifth PMOS tube is connected to the source terminal of the sixth PMOS tube and the drain terminal of the seventh PMOS tube, the source terminal of the seventh PMOS tube is connected to power supply voltage, and the gate terminal of the seventh PMOS tube and the gate terminal of the sixth NMOS tube are connected to a group of clock signals which are opposite in phase to each other.

Optionally, the first transmission gate and the second transmission gate have the same circuit structure, and both include: a seventh NMOS transistor and an eighth PMOS transistor; the source terminal of the seventh NMOS tube is connected to the source terminal of the eighth PMOS tube, the drain terminal of the seventh NMOS tube is connected to the drain terminal of the eighth PMOS tube, the gate terminal of the seventh NMOS tube is connected to a clock signal, the gate terminal of the eighth PMOS tube is connected to an inverted clock signal, the gate terminal of the sixth NMOS tube is connected to the inverted clock signal, and the gate terminal of the seventh PMOS tube is connected to the clock signal; or the grid end of the seventh NMOS tube is connected with an inverted clock signal, the grid end of the eighth PMOS tube is connected with the clock signal, the grid end of the sixth NMOS tube is connected with the clock signal at the moment, and the grid end of the seventh PMOS tube is connected with the inverted clock signal.

The present invention also provides an analog-to-digital converter comprising: a comparator as described above.

Optionally, the analog-to-digital converter comprises a successive approximation type analog-to-digital converter.

As described above, according to the comparator and the analog-to-digital converter of the present invention, through the design of the preamplifier and the rebuilt latch, a set of differential input signals is amplified to generate two sets of differential output signals, and the two sets of differential output signals are alternately input into the corresponding rebuilt latch unit to increase the signal difference input to the rebuilt latch unit, where the signal difference is used as the initial state of the rebuilt latch unit, and the speed of building the rebuilt latch unit is directly determined (the larger the initial value is, the faster the building is), so that the rebuilt latch unit can more easily realize the rebuilt, and the comparator is prevented from generating a metastable state; meanwhile, the two reestablishing latch units are different in disorder inevitably due to layout design and/or manufacturing deviation, so that the probability that the two reestablishing latch units are metastable under the same input voltage at the same time is reduced, and the metastable state of the comparator is further avoided. Therefore, the comparator eliminates the metastable state to the greatest extent, thereby improving the speed and the precision of the comparator and being particularly suitable for high-speed and high-precision application scenes.

Drawings

Fig. 1 shows a block circuit diagram of the comparator according to the present invention.

Fig. 2 shows a specific circuit diagram of the preamplifier according to the present invention.

FIG. 3 is a specific circuit diagram of the rebuilt latch according to the present invention.

Fig. 4 is a specific circuit diagram of the transmission gate according to the present invention.

Description of the element reference numerals

100 preamplifier, 200 rebuild latch, 201 first rebuild latch unit, 202 second rebuild latch unit.

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

Please refer to fig. 1 to 4. It should be noted that the drawings provided in the present embodiment are only schematic and illustrate the basic idea of the present invention, and although the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in actual implementation, the form, quantity and proportion of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.

As shown in fig. 1, the present embodiment provides a comparator, including:

the preamplifier 100 is used for amplifying a group of differential input signals VIN and VIP to generate two groups of differential output signals Von1 and Vop1, Von2 and Vop 2;

the rebuilt latch 200 includes two rebuilt latch units connected to corresponding output terminals of the preamplifier 100, so that two sets of the differential output signals Von1, Vop1, Von2 and Vop2 are alternately input into the corresponding rebuilt latch units to perform voltage regeneration on the interleaved input signals Von1, Vop2, Von2 and Vop 1.

As an example, as shown in fig. 2, the preamplifier 100 includes: a first resistor R1, a second resistor R2, a first NMOS transistor NM1, a second NMOS transistor NM2, a third NMOS transistor NM3, a first PMOS transistor PM1, a second PMOS transistor PM2, a third PMOS transistor PM3 and a fourth PMOS transistor PM 4; wherein a gate terminal of the first NMOS transistor NM1 and a gate terminal of the second NMOS transistor NM2 are connected to the differential input signals VIN and VIP, a source terminal of the first NMOS transistor NM1 is connected to a source terminal of the second NMOS transistor NM2 and a drain terminal of the third NMOS transistor NM3, a drain terminal of the first NMOS transistor NM1 is connected to one end of the first resistor R1 and serves as a first output terminal of the preamplifier 100 to output a differential output signal Von2, a drain terminal of the second NMOS transistor NM2 is connected to one end of the second resistor R2 and serves as a second output terminal of the preamplifier 100 to output a differential output signal Vop2, a gate terminal of the third NMOS transistor NM3 is connected to a first bias voltage Vb1, a source terminal of the third NMOS transistor NM3 is grounded, and the other end of the first resistor R1 is connected to the PM1 of the first PMOS transistor PM1 and the drain terminal of the second PMOS transistor NM2, and at the same time, as a third output terminal of the preamplifier 100, to output a differential output signal Von1, the other end of the second resistor R2 is connected to the drain terminal of the third PMOS transistor PM3 and the drain terminal of the fourth PMOS transistor PM4, and at the same time, as a fourth output terminal of the preamplifier 100, to output a differential output signal Vop1, the source terminal of the first PMOS transistor PM1 is connected to the power voltage VDD, the gate terminal of the first PMOS transistor PM1 is connected to the second bias voltage Vb2, the source terminal of the second PMOS transistor PM2 is connected to the power supply voltage VDD, the gate terminal of the second PMOS transistor PM2 is connected to the drain terminal of the fourth PMOS transistor PM4, the source terminal of the third PMOS transistor PM3 is connected to the power voltage VDD, the gate terminal of the third PMOS transistor PM3 is connected to the second bias voltage Vb2, the source terminal of the fourth PMOS transistor PM4 is connected to the power supply voltage VDD, and the gate terminal of the fourth PMOS transistor PM4 is connected to the drain terminal of the second PMOS transistor PM 2.

In this example, as shown in fig. 2, the first NMOS transistor NM1 and the second NMOS transistor NM2 are used as a pair of differential input transistors, and the differential input signals VIN and VIP are input; the third NMOS transistor NM3 is used as a tail current source to provide a fixed tail current bias for the differential input pair transistor; gate terminals of the second PMOS transistor PM2 and the fourth PMOS transistor PM4 are cross-coupled to form positive feedback, so as to increase the gain and bandwidth of the preamplifier 100, thereby increasing the precision and speed of the comparator of this example, and at the same time, the first PMOS transistor PM1, the second PMOS transistor PM2, the third PMOS transistor PM3 and the fourth PMOS transistor PM4 amplify differential input signals based on negative resistance effect, and generate two sets of differential output signals Von1, Vop1, Von2 and Vop2 through the first resistor R1 and the second resistor R2.

Specifically, as shown in fig. 2, the present example uses the third NMOS transistor NM3 as a tail current source; of course, in other examples, a current source may be used instead of the third NMOS transistor NM3, where one end of the current source is connected to the source terminal of the first NMOS transistor NM1 and the source terminal of the second NMOS transistor NM2, and the other end of the current source is grounded.

Specifically, as shown in fig. 2, in this example, the gate terminal of the third NMOS transistor NM3 is connected to the first bias voltage Vb1, and the gate terminals of the first PMOS transistor PM1 and the third PMOS transistor PM3 are both connected to the second bias voltage Vb 2; of course, in other examples, a clock signal CLK may be used instead of the first bias voltage Vb1 and the second bias voltage Vb2, where the gate terminal of the third NMOS transistor NM3, the gate terminal of the first PMOS transistor PM1, and the gate terminal of the third PMOS transistor PM3 are all connected to the clock signal CLK.

As an example, as shown in fig. 3, the circuit structures of the two reestablishing latch units are the same, and each of the two reestablishing latch units includes: the first transmission gate TG1, the second transmission gate TG2, the fourth NMOS transistor NM4, the fifth NMOS transistor NM5, the sixth NMOS transistor NM6, the fifth PMOS transistor PM5, the sixth PMOS transistor PM6 and the seventh PMOS transistor PM 7; the input terminals of the first transmission gate TG1 and the second transmission gate TG2 are connected to a set of the interleaved input signals Von1 and Vop2 or Von2 and Vop1 output by the preamplifier 100, and the two control terminals of the first transmission gate TG1 and the second transmission gate TG2 are connected to a set of clock signals CLK and Vop1 which are opposite in phase,

An output terminal of the first transmission gate TG1 is connected to a drain terminal of the fourth NMOS transistor NM4 and a drain terminal of the fifth PMOS transistor PM5, and simultaneously serves as a first output terminal of the re-establishment latch unit to output a level signal DB1 or a level signal DB2, an output terminal of the second transmission gate TG2 is connected to a drain terminal of the fifth NMOS transistor NM5 and a drain terminal of the sixth PMOS transistor PM6, and simultaneously serves as a second output terminal of the re-establishment latch unit to output a level signal D1 or a level signal D2, a gate terminal of the fourth NMOS transistor NM4 is connected to a drain terminal of the fifth NMOS transistor NM5, a gate terminal of the fifth NMOS transistor NM5 is connected to a drain terminal of the fourth NMOS transistor NM4, a source terminal of the fourth NMOS transistor NM4 is connected to a source terminal of the fifth NMOS transistor NM5 and a drain terminal of the sixth NMOS transistor 6, the sixth NMOS transistor NM6 is grounded, and the fifth PMOS transistor PM5 is connected to a gate terminal of the sixth PMOS transistor PM6, a gate terminal of the sixth PMOS transistor PM6 is connected to a drain terminal of the fifth PMOS transistor PM5, a source terminal of the fifth PMOS transistor PM5 is connected to a source terminal of the sixth PMOS transistor PM6 and a drain terminal of the seventh PMOS transistor PM7, a source terminal of the seventh PMOS transistor PM7 is connected to a power supply voltage VDD, and a gate terminal of the seventh PMOS transistor PM7 and the sixth PMOS transistor PM7 are connected to the power supply voltage VDDThe grid end of the NMOS tube NM6 is connected with a group of clock signals CLK,

. In this example, as shown in fig. 3, the rebuilt latch 200 includes a first rebuilt latch unit 201 and a second rebuilt latch unit 202; wherein, the input terminal of the first transmission gate TG1 in the first re-establishing latch unit 201 is connected to the interleaved input signal Von1, the input terminal of the second transmission gate TG2 in the first re-establishing latch unit 201 is connected to the interleaved input signal Vop2, meanwhile, the first output terminal of the first re-establishing latch unit 201 outputs the level signal DB1, and the second output terminal of the first re-establishing latch unit 201 outputs the level signal D1; the input terminal of the first transmission gate TG1 in the second reestablishing latch unit 202 is connected to the interleaved input signal Von2, the input terminal of the second transmission gate TG2 in the second reestablishing latch unit 202 is connected to the interleaved input signal Vop1, the first output terminal of the second reestablishing latch unit 202 outputs the level signal DB2, and the second output terminal of the second reestablishing latch unit 202 outputs the level signal D2.

Specifically, as shown in fig. 4, the first transmission gate TG1 and the second transmission gate TG2 have the same circuit structure, and both include: a seventh NMOS transistor NM7 and an eighth PMOS transistor PM 8; a source terminal of the seventh NMOS transistor NM7 is connected to a source terminal of the eighth PMOS transistor PM8, a drain terminal of the seventh NMOS transistor NM7 is connected to a drain terminal of the eighth PMOS transistor PM8, a gate terminal of the seventh NMOS transistor NM7 is connected to the clock signal CLK, and a gate terminal of the eighth PMOS transistor PM8 is connected to the inverted clock signal CLK

At this time, the gate terminal of the sixth NMOS transistor NM6 receives the inverted clock signal

The gate terminal of the seventh PMOS transistor PM7 receives a clock signal CLK; or the grid end of the seventh NMOS tube NM7 is connected with an inverted clock signal

The gate terminal of the eighth PMOS transistor PM8 receives the clock signal CLK, the gate terminal of the sixth NMOS transistor NM6 receives the clock signal CLK, and the gate terminal of the seventh PMOS transistor PM7 receives the inverted clock signal

(ii) a So that the first transmission gate TG1 and the second transmission gate TG2 are both turned on and off, the sixth NMOS transistor NM6 and the seventh PMOS transistor PM7 are both turned on and off, and their on and off states are opposite (i.e., when the first transmission gate TG1 and the second transmission gate TG2 are turned on, the sixth NMOS transistor NM6 and the seventh PMOS transistor PM7 are turned off, otherwise, when the first transmission gate TG1 and the second transmission gate TG2 are turned off, the sixth NMOS transistor NM6 and the seventh PMOS transistor PM7 are turned on). Optionally, in this example, a gate terminal of the seventh NMOS transistor NM7 is connected to the clock signal CLK, and a gate terminal of the eighth PMOS transistor PM8 is connected to the inverted clock signal

The gate terminal of the seventh PMOS transistor PM7 receives the clock signal CLK.

In this example, as shown in FIG. 3, when the clock signal CLK is high,

When the level is low, the first transmission gate TG1 and the second transmission gate TG2 are turned on, the sixth NMOS transistor NM6 and the seventh PMOS transistor PM7 are turned off, and then the cross input signals Von1 and Vop2 are input into the first re-establishment latch unit 201 through the first transmission gate TG1 and the second transmission gate TG2, and the cross input signals Von2 and Vop1 are input into the second re-establishment latch unit 202 through the first transmission gate TG1 and the second transmission gate TG 2; when the clock signal CLK is low,

When the voltage is high, the first transmission gate TG1 and the second transmission gate TG2 are turned off, the sixth NMOS tube NM6 and the seventh PMOS tube PM7 are turned on, and at this time, the fourth NMOS tube NM4 and the fifth NMOS tube NM5, the fifth PMOS tube PM5 and the sixth PMOS tube PM6 are cross-coupled by gate terminals to form positive feedback, and based on the positive feedback, the voltages of the cross input signals Von1 and Vop2 input into the first re-establishing latch unit 201 and the voltages of the cross input signals Von2 and Vop1 input into the second re-establishing latch unit 202 can be quickly pulled apart, so that the first re-establishing latch unit 201 can generate the output of the level signals DB1 and D1 based on the initial states of Von1 and Vop2 and the initial states of Von2 and Vop1 to complete the establishment of high and low levels, and the first re-establishing latch unit 201 can generate the output of the level signals DB1 and D1, and the second re-establishing latch unit 202 can generate the output 2 and DB2 and D2.

It should be noted that, when the comparator described in this example operates, within a specified time, as long as any one of the two reestablishing latch units outputs the comparison result first, and the other one of the two reestablishing latch units does not affect the normal conversion of the analog-to-digital converter whether outputting the comparison result later or entering the metastable state; in order to achieve the purpose, in practical application, a digital processing module, such as a digital processing module including a logical or, for performing correlation processing on the output level signals of the two reestablishing latch units is further added after the comparator in this example; of course, other digital processing modules capable of achieving the purpose are also applicable to the present example, and the present example does not limit the present example.

The present embodiment also provides an analog-to-digital converter, including: a comparator as described above.

As an example, the analog-to-digital converter comprises a successive approximation type analog-to-digital converter; of course, the analog-to-digital converter may also be another type of analog-to-digital converter, and the type of the analog-to-digital converter is not limited in this example.

In summary, according to the comparator and the analog-to-digital converter of the present invention, through the design of the preamplifier and the rebuilt latch, a set of differential input signals is amplified to generate two sets of differential output signals, and the two sets of differential output signals are input to the corresponding rebuilt latch unit in a staggered manner to increase the signal difference input to the rebuilt latch unit, where the signal difference is used as the initial state of the rebuilt latch unit, and the speed of building the rebuilt latch unit is directly determined (the larger the initial value is, the faster the building is), so that the rebuilt latch unit can more easily realize the rebuilt, and the comparator is prevented from generating a metastable state; meanwhile, the two reestablishing latch units are different in disorder inevitably due to layout design and/or manufacturing deviation, so that the probability that the two reestablishing latch units are metastable under the same input voltage at the same time is reduced, and the metastable state of the comparator is further avoided. Therefore, the comparator eliminates the metastable state to the greatest extent, thereby improving the speed and the precision of the comparator and being particularly suitable for high-speed and high-precision application scenes. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims

1. A comparator, characterized in that the comparator comprises:

wherein the preamplifier includes: the NMOS transistor comprises a first resistor, a second resistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor and a fourth PMOS transistor; wherein, the gate terminal of the first NMOS transistor and the gate terminal of the second NMOS transistor are connected to the differential input signal, the source terminal of the first NMOS transistor is connected to the source terminal of the second NMOS transistor and the drain terminal of the third NMOS transistor, the drain terminal of the first NMOS transistor is connected to one end of the first resistor and is used as the first output terminal of the preamplifier, the drain terminal of the second NMOS transistor is connected to one end of the second resistor and is used as the second output terminal of the preamplifier, the gate terminal of the third NMOS transistor is connected to the first bias voltage, the source terminal of the third NMOS transistor is grounded, the other end of the first resistor is connected to the drain terminal of the first PMOS transistor and the drain terminal of the second PMOS transistor and is used as the third output terminal of the preamplifier, the other end of the second resistor is connected to the drain terminal of the third PMOS transistor and the drain terminal of the fourth PMOS transistor, meanwhile, the output end of the preamplifier is used as a fourth output end of the preamplifier, the source end of the first PMOS tube is connected with a power supply voltage, the grid end of the first PMOS tube is connected with a second bias voltage, the source end of the second PMOS tube is connected with the power supply voltage, the grid end of the second PMOS tube is connected with the drain end of the fourth PMOS tube, the source end of the third PMOS tube is connected with the power supply voltage, the grid end of the third PMOS tube is connected with the second bias voltage, the grid end of the fourth PMOS tube is connected with the power supply voltage, and the grid end of the fourth PMOS tube is connected with the drain end of the second PMOS tube;

the circuit structures of the two reestablishment latch units are the same, and both the reestablishment latch units comprise: the first transmission gate, the second transmission gate, the fourth NMOS transistor, the fifth NMOS transistor, the sixth NMOS transistor, the fifth PMOS transistor, the sixth PMOS transistor and the seventh PMOS transistor; wherein, the input ends of the first transmission gate and the second transmission gate are connected to a group of the staggered input signals output by the preamplifier, two control ends of the first transmission gate and the second transmission gate are connected to a group of clock signals which are in opposite phases, the output end of the first transmission gate is connected to the drain end of the fourth NMOS tube and the drain end of the fifth PMOS tube and is used as the first output end of the reestablishing latch unit, the output end of the second transmission gate is connected to the drain end of the fifth NMOS tube and the drain end of the sixth PMOS tube and is used as the second output end of the reestablishing latch unit, the gate end of the fourth NMOS tube is connected to the drain end of the fifth NMOS tube, the gate end of the fifth NMOS tube is connected to the drain end of the fourth NMOS tube, and the source end of the fourth NMOS tube is connected to the source end of the fifth NMOS tube and the drain end of the sixth NMOS tube, the source terminal of the sixth NMOS tube is grounded, the gate terminal of the fifth PMOS tube is connected to the drain terminal of the sixth PMOS tube, the gate terminal of the sixth PMOS tube is connected to the drain terminal of the fifth PMOS tube, the source terminal of the fifth PMOS tube is connected to the source terminal of the sixth PMOS tube and the drain terminal of the seventh PMOS tube, the source terminal of the seventh PMOS tube is connected to power supply voltage, and the gate terminal of the seventh PMOS tube and the gate terminal of the sixth NMOS tube are connected to a group of clock signals which are opposite in phase to each other.

2. The comparator as claimed in claim 1, wherein the third NMOS transistor is replaced by a current source, and one end of the current source is connected to the source terminal of the first NMOS transistor and the source terminal of the second NMOS transistor, and the other end of the current source is grounded.

3. The comparator as claimed in claim 1, wherein a clock signal is used to replace the first bias voltage and the second bias voltage, and the gate terminal of the third NMOS transistor, the gate terminal of the first PMOS transistor and the gate terminal of the third PMOS transistor are all connected to the clock signal.

4. The comparator according to claim 1, wherein the first transmission gate and the second transmission gate have the same circuit structure, and each of the first transmission gate and the second transmission gate comprises: a seventh NMOS transistor and an eighth PMOS transistor; the source terminal of the seventh NMOS tube is connected to the source terminal of the eighth PMOS tube, the drain terminal of the seventh NMOS tube is connected to the drain terminal of the eighth PMOS tube, the gate terminal of the seventh NMOS tube is connected to a clock signal, the gate terminal of the eighth PMOS tube is connected to an inverted clock signal, the gate terminal of the sixth NMOS tube is connected to the inverted clock signal, and the gate terminal of the seventh PMOS tube is connected to the clock signal; or the grid end of the seventh NMOS tube is connected with an inverted clock signal, the grid end of the eighth PMOS tube is connected with the clock signal, the grid end of the sixth NMOS tube is connected with the clock signal at the moment, and the grid end of the seventh PMOS tube is connected with the inverted clock signal.

5. An analog-to-digital converter, comprising: a comparator as claimed in any one of claims 1 to 4.

6. The analog-to-digital converter according to claim 5, characterized in that the analog-to-digital converter comprises a successive approximation type analog-to-digital converter.