CN111564499A - 一种低压多功能电荷俘获型突触晶体管及其制备方法 - Google Patents
一种低压多功能电荷俘获型突触晶体管及其制备方法 Download PDFInfo
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Abstract
本发明公开了一种低压多功能电荷俘获型突触晶体管及其制备方法,属于面向神经网络硬件化应用的突触器件领域。本发明采用氮化硅和氧化铪双俘获层结构来在单一器件上同时实现短长时程突触可塑性,从而丰富了突触器件的功能;三栅纳米线结构有利于增强界面电场,从而降低了界面处FN隧穿宽度,增强了界面处隧穿几率,降低了操作电压和器件功耗。另外,器件具有完全的CMOS材料以及工艺兼容性,这些优良的器件特性使得其有潜力应用到未来大规模神经网络计算系统中。
Description
技术领域
本发明涉及神经形态计算系统领域,为搭建神经形态计算系统提供基础突触器件单元,特别涉及一种具有低功耗、高可靠性和良好CMOS工艺兼容性优势的电荷俘获型突触晶体管。
背景技术
神经形态计算是通过模拟高并行度、高容错性、高能效的生物神经形态系统的计算模式而实现的一种存算一体的新型计算架构,其中底层的突触和神经元器件是搭建复杂神经形态计算系统的基础,对于突触器件而言,目前新兴了大量的突触器件,如阻变存储器(Resistive Random Access Memory,RRAM),相变存储器(Phase Change Random AccessMemory,PCRAM),离子栅控突触晶体管(Ionic Gated Field-effect Transistor,IGFET)和电荷俘获型突触晶体管(Charge Trapped Field-effect Transistor,CTFET),其中电荷俘获型突触晶体管具有CMOS工艺兼容性好、集成密度高和读写分离的优势,但是目前的电荷俘获突触晶体管存在功能单一、操作电压高等挑战。
具体来说,由于CTFET是基于非易失性的电荷俘获机制来工作的,因而其只能模拟长时程的突触可塑性,缺乏对同样重要的短时程可塑性的模拟,而短时程可塑性在突触计算中扮演着重要的角色。
另一方面,电荷在编程和擦除时需要隧穿过比较宽的势垒,因而操作电压高。
综上,低压操作并且能够同时实现短长时程可塑性的突触晶体管有待开发。
发明内容
传统的电荷俘获型突触晶体管基于非易失性电荷俘获机制来工作,因而其只能实现长时程可塑性,无法实现短时程可塑性;此外由于电荷在编程和擦除时需要隧穿过宽的势垒,因而其操作电压较高。针对以上问题,本发明的目的是提供一种低压多功能电荷俘获型突触晶体管及其制备方法。
本发明提出的低压多功能电荷俘获型突触晶体管,包括SOI衬底、纳米线沟道区、源区、漏区、层间介质、栅电极、隔离层和金属引出层,其中:源区、漏区以及连接二者的纳米线沟道区形成于SOI衬底上,从纳米线沟道区往外依次为氧化硅、氮化硅、氧化铪和氧化铝叠层结构的层间介质,栅电极位于层间介质之上;隔离层覆盖晶体管器件的表面;金属引出层中源漏的金属引出线通过贯穿隔离层和层间介质的通孔分别连接至源区、漏区,栅电极的金属引出线通过穿过隔离层的通孔连接栅电极。
在本发明的低压多功能电荷俘获型突触晶体管中,所述层间介质从纳米线沟道区起由内向外依次是隧穿氧化硅层、氮化硅俘获层、氧化铪俘获层、氧化铝阻挡层。该突触晶体管采用氮化硅和氧化铪双俘获层结构,通过具有深能级缺陷的远离沟道的氧化铪俘获层和缺陷能级较浅的靠近沟道的氮化硅俘获层的叠层结构来同时实现短长时程可塑性。优选的,所述隧穿氧化层的厚度为1~2nm,氮化硅俘获层的厚度为3~5nm,氧化铪俘获层的厚度为3~5nm,氧化铝阻挡层的厚度为8~10nm。
采用三栅(Tri-gate)硅纳米线结构来增强界面电场,从而增强界面处FN(Fowler-Nordheim)隧穿的几率,提高电荷俘获或者释放的效率,降低操作电压。
在本发明的低压多功能电荷俘获型突触晶体管中,所述栅电极为金属栅电极,其材料优选为氮化钛、铝、钽、钨和氮化钽等,厚度为50~200nm。
本发明还提供了上述低压多功能电荷俘获型突触晶体管的制备方法,包括以下步骤:
1)在SOI衬底上利用光刻技术图形化,刻蚀形成硅纳米线沟道区以及分别连接其两端的源区和漏区,得到哑铃型硅结构,并对源区和漏区进行掺杂、退火;
2)通过热氧化在哑铃型硅结构上形成隧穿氧化硅层,并依次淀积氮化硅俘获层、氧化铪俘获层、氧化铝阻挡层,形成层间介质;
3)在氧化铝阻挡层上淀积金属电极层,利用光刻技术定义栅线条并刻蚀至氧化铝阻挡层,形成栅电极;
4)淀积隔离层并对表面进行平坦化,然后制作源漏栅的金属引出。
上述步骤1)具体包括:
1a)在SOI衬底上旋涂无机负性光刻胶,如含氢硅酸盐类的HSQ(HydrogenSilsesquioxane)电子束胶,然后通过电子束光刻技术图形化无机负性光刻胶作为纳米线硬掩模;
1b)旋涂有机正性光刻胶,通过光刻技术图形化有机正性光刻胶作为源漏掩膜;
1c)以纳米线硬掩模(无机胶)和源漏掩膜(有机胶)为混合掩膜,各向异性刻蚀硅形成哑铃型结构;
1d)去掉源漏掩膜,保留纳米线硬掩膜,通过离子注入技术对源漏进行重掺杂,然后湿法腐蚀去除纳米线硬掩膜,退火激活源漏杂质。
其中,退火方式可以采用快速热退火(Rapid Thermal Annealing,RTA)、激光退火(LaserAnnealing)、闪耀退火(Flash Annealing)和尖峰退火(Spike Annealing)中的一种。上述步骤2)中淀积氮化硅俘获层、氧化铪俘获层、氧化铝阻挡层的方法和步骤4)中淀积隔离层的方法包括低压化学气相沉积(Low Pressure Chemical Vapor Deposition,LPCVD)、等离子体增强化学气相沉积(Plasma Enhanced Chemical Vapor Deposition,PECVD)和原子层沉积(Atomic Layer Deposition,ALD)等方法。在本发明的实施例中,在步骤2)中采用LPCVD技术淀积氮化硅俘获层,再利用ALD依次淀积氧化铪俘获层和氧化铝阻挡层;在步骤4)采用LPCVD技术淀积氧化硅隔离层。
上述步骤4)中,淀积隔离层并对表面进行平坦化后,利用光刻技术定义源漏栅上方的通孔,以光刻胶为掩膜,先采用干法刻蚀技术刻蚀隔离层,后采用湿法腐蚀栅通孔中剩余的隔离层以及源漏通孔中剩余的氧化铝、氧化铪、氮化硅和氧化硅层;淀积金属填充通孔并形成金属膜,进行表面平坦化后利用光刻技术定义金属引出线,以光刻胶为掩膜,干法刻蚀金属层至隔离层,形成金属引出。
上述步骤3)和步骤4)中采用磁控溅射(Magnetron Sputtering)、金属蒸发沉积(Metal Evaporation)等物理气相沉积(Physical Vapor Deposition,PVD)的方式淀积金属。
上述制备方法中,所采用的光刻技术为诸如193nm光刻技术等能够纳米尺度的光刻技术。
上述制备方法中,所采用的刻蚀技术为反应离子刻蚀(Reactive Ion Etching,RIE)和电感耦合等离子体刻蚀(Inductively Coupled Plasma Etching,ICPE)等方法。
上述步骤5)中,通孔填充为具有高填充率和低电阻率的金属材料,如Ti、W、Al、Cu和TiN及其金属复合叠层等。
本发明的优点和积极效果如下:
1)能够在同一器件上实现短长时程突触可塑性,采用具有深能级缺陷的远离沟道的氧化铪俘获层来模拟长时程可塑性,采用具有较浅能级缺陷的靠近沟道的氮化硅俘获层来模拟短时程可塑性;
2)采用三栅结构的纳米线结构,可以增强氮化硅和氧化硅的界面电场,从而有利于界面处的FN隧穿,提高了俘获和释放电荷的效率。
3)在操作方式上,采用先将电子编程到氮化硅和氧化硅界面,而后改变电荷的纵向俘获位置的方式来改变沟道阈值电压,这种方式可以降低FN隧穿的宽度,降低操作电压;
4)当操作电压降低后,栅介质中FN隧穿的几率会降低,即栅泄漏电流会降低,从而功耗也会实现相应的降低。
附图说明
图1-图8为本发明低压多功能电荷俘获型突触晶体管的各关键工艺步骤的示意图。各图中,(a)为器件的俯视图,(b)为(a)沿A-A’方向的器件剖面图,(c)为(a)沿B-B’方向的器件剖面图。其中:
图1为在SOI衬底上旋涂HSQ电子束胶的步骤;
图2为利用电子束曝光技术定义纳米线掩膜的步骤;
图3为利用光刻技术定义源漏掩膜,与纳米线掩膜作为混合掩膜刻蚀形成哑铃型的纳米线结构的步骤;
图4为热氧化生成隧穿氧化层,依次淀积氮化硅俘获层、氧化铪俘获层、氧化铝阻挡层和氮化钛栅电极层的步骤;
图5为利用光刻技术定义栅电极,刻蚀形成栅电极至氧化铝层的步骤;
图6为淀积氧化硅隔离层的步骤;
图7为通孔刻蚀至源漏硅界面和栅电极表面的步骤;
图8为淀积金属层,图形化形成金属引出线,并平坦化的步骤。
图9为图1~图8中所有材料的图例。
具体实施方式
下面结合附图,通过具体实例来对本发明进行详细说明。
如图1至图8所示,根据下述步骤制备低压多功能电荷俘获型突触晶体管:
1)对SOI基片的硅膜进行减薄,具体的操作方式为干氧氧化或者氢氧合成氧化表面硅膜成氧化硅膜,而后用氢氟酸溶液将表面氧化硅膜漂洗掉,进而旋涂HSQ电子束胶,如图1所示。也可以采用体硅衬底,而后依次淀积氧化硅膜和多晶硅膜,从而形成SOI基片。
2)利用电子束光刻技术定义纳米线掩膜,纳米线掩膜的宽度即为后续形成硅纳米线的线宽,如图2所示。
3)利用光刻技术定义源漏掩膜,与纳米线硬掩模共同形成哑铃型结构的混合曝光掩膜,然后干法刻蚀形成哑铃型的硅纳米线结构,如图3所示;去掉源漏上方的有机掩膜,保留硅纳米线上方的无机硬掩膜,通过离子注入技术对源漏进行重掺杂,然后湿法腐蚀去除无机硬掩膜,快速热退火激活源漏杂质。
4)在硅纳米线表面干氧氧化生成2nm厚的氧化硅膜,然后利用低压化学气相沉积(LowPressure Chemical Vapor Deposition,LPCVD)技术淀积5nm厚的氮化硅俘获膜,再利用原子层淀积(Atomic Layer Deposition,ALD)依次淀积5nm厚的氧化铪俘获膜和8nm厚的氧化铝阻挡膜,最后利用磁控溅射(Magnetron Sputtering)技术淀积100nm厚的氮化钛金属层,如图4所示。
5)利用光刻技术定义栅电极,以光刻胶为掩膜,采用电感耦合等离子体刻蚀(InductivelyCoupled Plasma Etching,ICPE)去除氮化钛膜至氧化铝层,为了防止金属短路,对氧化铝层进行适当的过刻蚀,如图5所示。
6)采用低压化学气相沉积淀积200nm厚的氧化硅隔离层,并用化学机械抛光(ChemicalMechanical Polishing,CMP)进行表面平坦化,如图6所示。
7)利用光刻技术定义源漏栅上方的通孔,以光刻胶为掩膜,先采用干法刻蚀技术刻蚀氧化硅层150nm,而后采用BOE(Buffered Oxide Etch)溶液湿法腐蚀栅通孔中剩余的氧化硅层以及源漏通孔中剩余的氧化铝、氧化铪、氮化硅和氧化硅层,如图7所示。
8)采用磁控溅射依次淀积金属钛(粘附层)和金属铝填充通孔并形成金属膜(即Metal0),采用化学机械抛光(Chemical Mechanical Polishing,CMP)进行表面平坦化,利用光刻技术定义金属引出线,利用光刻胶为掩膜,干法刻蚀金属层至氧化硅隔离层,为了防止金属互联线短路,需要进行适量的过刻蚀如图8所示。
本发明实施例并非用以限定本发明。任何熟悉本领域的技术人员,在不脱离本发明技术方案范围情况下,都可利用上述揭示的方法和技术内容对本发明技术方案作出许多可能的变动和修饰,或修改为等同变化的等效实施例。因此,凡是未脱离本发明技术方案的内容,依据本发明的技术实质对以上实施例所做的任何简单修改、等同变化及修饰,均仍属于本发明技术方案保护的范围内。
Claims (9)
1.一种电荷俘获型突触晶体管,包括SOI衬底、纳米线沟道区、源区、漏区、层间介质、栅电极、隔离层和金属引出层,其中:源区、漏区以及连接二者的纳米线沟道区形成于SOI衬底上,从纳米线沟道区往外依次为氧化硅、氮化硅、氧化铪和氧化铝叠层结构的层间介质,栅电极位于层间介质之上;隔离层覆盖晶体管器件的表面;金属引出层中源漏的金属引出线通过贯穿隔离层和层间介质的通孔分别连接至源区、漏区,栅电极的金属引出线通过穿过隔离层的通孔连接栅电极。
2.如权利要求1所述的电荷俘获型突触晶体管,其特征在于,所述层间介质从纳米线沟道区起由内向外依次是隧穿氧化硅层、氮化硅俘获层、氧化铪俘获层、氧化铝阻挡层,其中所述隧穿氧化层的厚度为1~2nm,氮化硅俘获层的厚度为3~5nm,氧化铪俘获层的厚度为3~5nm,氧化铝阻挡层的厚度为8~10nm。
3.如权利要求1所述的电荷俘获型突触晶体管,其特征在于,所述栅电极为金属栅电极。
4.权利要求1~3任一所述的电荷俘获型突触晶体管的制备方法,包括以下步骤:
1)在SOI衬底上利用光刻技术图形化,刻蚀形成硅纳米线沟道区以及分别连接其两端的源区和漏区,得到哑铃型硅结构,并对源区和漏区进行掺杂、退火;
2)通过热氧化在哑铃型硅结构上形成隧穿氧化硅层,并依次淀积氮化硅俘获层、氧化铪俘获层、氧化铝阻挡层,形成层间介质;
3)在氧化铝阻挡层上淀积金属电极层,利用光刻技术定义栅线条并刻蚀至氧化铝阻挡层,形成栅电极;
4)淀积隔离层并对表面进行平坦化,然后制作源漏栅的金属引出。
5.如权利要求4所述的制备方法,其特征在于,所述步骤1)包括:
1a)在SOI衬底上旋涂无机负性光刻胶,然后通过电子束光刻技术图形化无机负性光刻胶作为纳米线硬掩模;
1b)旋涂有机正性光刻胶,通过光刻技术图形化有机正性光刻胶作为源漏掩膜;
1c)以纳米线硬掩模和源漏掩膜为混合掩膜,各向异性刻蚀硅形成哑铃型结构;
1d)去掉源漏掩膜,保留纳米线硬掩膜,通过离子注入技术对源漏进行重掺杂,然后湿法腐蚀去除纳米线硬掩膜,退火激活源漏杂质。
6.如权利要求5所述的制备方法,其特征在于,所述无机负性光刻胶为HSQ电子束胶。
7.如权利要求4所述的制备方法,其特征在于,步骤2)中采用低压化学气相沉积、等离子体增强化学气相沉积和原子层沉积中的一种或多种方法淀积氮化硅俘获层、氧化铪俘获层、氧化铝阻挡层;步骤4)中采用低压化学气相沉积、等离子体增强化学气相沉积和原子层沉积中的一种方法淀积隔离层。
8.如权利要求4所述的制备方法,其特征在于,在步骤4)中,淀积隔离层并对表面进行平坦化后,利用光刻技术定义源漏栅上方的通孔,以光刻胶为掩膜,先采用干法刻蚀技术刻蚀隔离层,后采用湿法腐蚀栅通孔中剩余的隔离层以及源漏通孔中剩余的氧化铝、氧化铪、氮化硅和氧化硅层;淀积金属填充通孔并形成金属膜,进行表面平坦化后利用光刻技术定义金属引出线,以光刻胶为掩膜,干法刻蚀金属层至隔离层,形成金属引出。
9.如权利要求8所述的制备方法,其特征在于,步骤4)中采用磁控溅射或金属蒸发沉积的方式淀积金属。
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