CN111564415A - 具有填充的导电腔体的半导体封装 - Google Patents

具有填充的导电腔体的半导体封装 Download PDF

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Publication number
CN111564415A
CN111564415A CN202010079564.4A CN202010079564A CN111564415A CN 111564415 A CN111564415 A CN 111564415A CN 202010079564 A CN202010079564 A CN 202010079564A CN 111564415 A CN111564415 A CN 111564415A
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China
Prior art keywords
cavity
major surface
insulating body
thermally
electrically conductive
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CN202010079564.4A
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English (en)
Inventor
黄志洋
蔡福城
S·马海因尔
J·梅尔茨
N·奥斯曼
J·V·苏赛普拉卡萨姆
H·H·郑
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Infineon Technologies AG
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Infineon Technologies AG
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Publication of CN111564415A publication Critical patent/CN111564415A/zh
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Abstract

本发明公开了一种半导体封装，包括框架，该框架具有：具有第一主表面和与第一主表面相对的第二主表面的绝缘主体；第一主表面处的第一多个金属迹线；以及绝缘主体中的第一腔体。导热和/或导电材料填充绝缘主体中的第一腔体，并且具有与第一多个金属迹线不同的成分。导热和/或导电材料在绝缘主体的第一主表面和第二主表面之间提供导热和/或导电路径。在绝缘主体的第一主表面附接到框架的半导体管芯电连接到第一多个金属迹线并且电连接到填充绝缘主体中的第一腔体的导热和/或导电材料。还描述了一种对应的制造方法。

Description

具有填充的导电腔体的半导体封装
背景技术
常规引线框架封装由于使用厚的铜底座而提供了良好的散热性。然而，常规引线框架封装中的电信号的再分布受到引线键合约束的限制。与常规引线框架封装相比，常规RDL(再分布层)封装(例如基于层合的封装)为电信号再分布提供了更好的灵活性。然而，常规RDL封装通常具有通过蚀刻薄的Cu片或通过Cu镀覆来制造的较薄的铜迹线。在常规RDL封装中，使用薄的铜迹线会限制这种封装的散热和功率(大电流)容量。这种限制对于片上系统(SoC)产品/芯片而言更为严重，在SoC产品/芯片中，较高的引脚数和电信号再分布是重要考虑因素，同时必须提供足够水平的功率和热量管理。
因此，需要具有良好的电信号再分布以及良好的功率和热量管理的改进的功率半导体封装。
发明内容
根据半导体封装的实施例，所述半导体封装包括：框架，所述框架包括具有第一主表面和与所述第一主表面相对的第二主表面的绝缘主体、第一主表面处的第一多个金属迹线以及绝缘主体中的第一腔体；填充绝缘主体中的第一腔体并且具有与第一多个金属迹线不同的成分的导热和/或导电材料，所述导热和/或导电材料在绝缘主体的第一和第二主表面之间提供导热和/或导电路径；以及半导体管芯，所述半导体管芯在绝缘主体的第一主表面附接到框架，并且电连接到第一多个金属迹线并电连接到填充绝缘主体中的第一腔体的导热和/或导电材料。
半导体管芯可以是功率半导体管芯，并且功率半导体管芯的面向绝缘主体的第一主表面的高功率端子可以电连接到填充绝缘主体中的第一腔体的导热和/或导电材料。
单独地或组合地，框架还可以包括绝缘主体的第二主表面处的第二多个金属迹线、以及多个过孔，所述多个过孔将绝缘主体的第一主表面处的第一多个金属迹线电连接到绝缘主体的第二主表面处的第二多个金属迹线，并且功率半导体管芯的高功率端子可以通过填充绝缘主体中的第一腔体的导热和/或导电材料而电连接到绝缘主体的第二主表面处的金属迹线。
单独地或组合地，填充第一腔体的导热和/或导电材料的面积可以至少是单个过孔的平均面积的10倍。
单独地或组合地，框架还可以包括在绝缘主体中的第二腔体，第二腔体可以小于第一腔体并且与第一腔体在横向上间隔开，第二腔体可以填充有具有与所述第一多个金属迹线不同的成分的导热和/或导电材料，并且在绝缘主体的第一和第二主表面之间提供导热和/或导电路径，并且面向绝缘主体的第一主表面的功率半导体管芯的第二高功率端子可以电连接到填充绝缘主体中的第二腔体的导热和/或导电材料。
单独地或组合地，功率半导体管芯可以包括多个低功率端子，所述多个低功率端子通过多个过孔和第一多个金属迹线而电连接到绝缘主体的第二主表面处的第二多个金属迹线。
单独地或组合地，半导体封装还可以包括逻辑管芯，所述逻辑管芯附接到功率半导体管芯的背离框架的一侧或在绝缘主体的第一主表面附接到框架，并且逻辑管芯可以被配置为控制功率半导体管芯。
单独地或组合地，半导体封装还可以包括在绝缘主体的第一主表面包封半导体管芯的包封体。
单独地或组合地，框架可以是印刷电路板，并且包封体可以是模制化合物。
单独地或组合地，填充第一腔体的导热和/或导电材料可以包括硬化的银浆、硬化的铜浆、纳米碳材料或硬化的焊锡浆，并且第一多个金属迹线可以包括电镀铜。
单独地或组合地，填充第一腔体的导热和/或导电材料可以未被绝缘主体的第一主表面处的金属迹线覆盖，并且半导体管芯可以在绝缘主体的第一主表面附接到导热和/或导电材料。
单独地或组合地，第一腔体可以终止于绝缘主体的第二主表面处的金属迹线，并且半导体管芯可以通过填充第一腔体的导热和/或导电材料而电连接到使第一腔体终止于绝缘主体的第二主表面的金属迹线。
单独地或组合地，第一腔体可以终止于绝缘主体的第一主表面处的金属迹线，半导体管芯可以附接到使第一腔体终止于绝缘主体的第一主表面的金属迹线，并且半导体管芯可以通过使第一腔体终止于绝缘主体的第一主表面的金属迹线而电连接到填充第一腔体的导热和/或导电材料。
单独地或组合地，填充第一腔体的导热和/或导电材料可以未被绝缘主体的第二主表面处的金属迹线覆盖。
单独地或组合地，半导体管芯可以在绝缘主体的第一主表面处被包封在模制化合物中，并且使第一腔体终止于绝缘主体的第一主表面处的金属迹线可以将模制化合物与填充第一腔体的导热和/或导电材料分隔开。
单独地或组合地，框架还可以包括在绝缘主体中的第二腔体，第二腔体可以小于第一腔体并且与第一腔体在横向上间隔开，第二腔体可以填充有具有与第一多个金属迹线不同的成分的导热和/或导电材料，并且在绝缘主体的第一和第二主表面之间提供导热和/或导电路径，并且半导体管芯可以电连接到填充绝缘主体中的第二腔体的导热和/或导电材料。
单独地或组合地，填充第二腔体的导热和/或导电材料可以具有与填充第一腔体的导热和/或导电材料相同的成分。
单独地或组合地，填充第一腔体的导热和/或导电材料可以包括硬化的银浆、硬化的铜浆、纳米碳材料或硬化的焊锡浆，第一多个金属迹线可以包括电镀铜，并且填充第二腔体的导热和/或导电材料可以包括硬化的银浆、硬化的铜浆、纳米碳材料或硬化的焊锡浆。
根据制造半导体封装的方法的实施例，该方法包括：在框架的绝缘主体中形成腔体，该绝缘主体具有第一主表面和与第一主表面相对的第二主表面，并且在绝缘主体的第一主表面处形成第一多个金属迹线；用具有与第一多个金属迹线不同的成分的导热和/或导电材料填充绝缘主体中的第一腔体，所述导热和/或导电材料在绝缘主体的第一和第二主表面之间提供导热和/或导电路径；以及在绝缘主体的第一主表面处将半导体管芯附接到框架，使得半导体管芯电连接到第一多个金属迹线并且电连接到填充绝缘主体中的第一腔体的导热和/或导电材料。
用导热和/或导电材料填充绝缘主体中的第一腔体可以包括：在第一腔体中和形成在绝缘主体的第一主表面处的多个金属迹线中的互连焊盘上丝网印刷导电浆。
单独地或组合地，导电浆可以是烧结的银浆、烧结的铜浆或烧结的焊锡浆，并且可以在导电浆的丝网印刷之前，通过电化学沉积形成第一多个金属迹线。
单独地或组合地，在绝缘主体的第一主表面处将半导体管芯附接到框架可以包括：将半导体管芯的高功率端子倒装芯片键合到填充绝缘主体中的第一腔体的导热和/或导电材料，并将半导体管芯的多个低功率端子倒装芯片键合到绝缘主体的第一主表面处的互连焊盘。
单独地或组合地，该方法还可以包括：在将半导体管芯附接到框架之后，将半导体管芯和绝缘主体的第一主表面包封在模制化合物中。
根据半导体封装的另一个实施例，所述半导体封装包括：框架，其包括绝缘主体、所述绝缘主体的第一主表面处的第一金属迹线、在绝缘主体的与第一主表面相对的第二主表面处的第二金属迹线、将第一主表面处的第一金属迹线中的一些或全部电连接到第二主表面处的第二金属迹线中的一些或全部的过孔、以及形成在绝缘主体的无导电过孔的区域中的腔体；填充绝缘主体中的腔体的硬化的银浆、硬化的铜浆、纳米碳材料或硬化的焊锡浆；以及半导体管芯，其在绝缘主体的第一主表面处附接到框架，并且电连接到第一金属迹线的一些或全部，并且电连接到填充绝缘主体中的腔体的硬化的银浆、硬化的铜浆、纳米碳材料或硬化的焊锡浆。
本领域技术人员在阅读以下具体实施方式并在查看附图时将认识到附加的特征和优点。
附图说明
附图的元件不必相对于彼此成比例。类似的附图标记表示对应的相似的部分。除非它们彼此排斥，否则可以组合各种所示的实施例的特征。在附图中描绘了实施例，并且在随后的说明书中详细描述了实施例。
图1示出了半导体封装的实施例的局部截面图，该半导体封装包括具有无导电过孔的填充的腔体的框架。
图2示出了半导体封装的另一个实施例的局部截面图，该半导体封装包括具有无导电过孔的填充的腔体的框架。
图3示出了半导体封装的另一个实施例的局部截面图，该半导体封装包括具有无导电过孔的填充的腔体的框架。
图4示出了半导体封装的另一个实施例的局部截面图，该半导体封装包括具有无导电过孔的填充的腔体的框架。
图5示出了制造图1至图4所示的半导体封装的方法的实施例的流程图。
图6A至图6D示出了在图5所示的制造方法的不同阶段期间的相应的局部截面图。
图7A至图7C示出了图1至图4所示的半导体封装中所包括的框架的不同层。
具体实施方式
本文描述的实施例提供了一种半导体封装以及相应的制造半导体封装的方法，该半导体封装包括被附接有一个或多个半导体管芯的框架。框架具有腔体，该腔体无导电过孔并且填充有硬化的银浆、硬化的铜浆、纳米碳材料、硬化的焊锡浆或不同于框架的电镀金属部分的类似类型的导热和/或导电材料。填充框架中的腔体的导热和/或导电材料在框架的相对的主表面之间提供导热和/或导电路径。框架可以具有填充有导热和/或导电材料的单个腔体或多于一个腔体，以用于在框架的相对的主表面之间提供至少一个导热和/或导电路径。
图1示出了半导体封装100的实施例的局部截面图。半导体封装100包括框架102，框架102包括具有第一主表面106和与第一主表面106相对的第二主表面108的绝缘主体104、第一主表面106处的第一金属迹线110、以及形成在绝缘主体104中的第一腔体112。在一个实施例中，框架102是电路板，例如印刷电路板(PCB)。在PCB框架的情况下，PCB可以是单面的(例如一个铜层)、双面的(例如在绝缘主体两侧上的两个铜层)、或多层的(例如与绝缘材料层交替的铜内层和铜外层)。在另一个实施例中，框架102是塑料模制主体。可以使用在其中形成有腔体的其他框架。
框架102还可以包括在绝缘主体104的第二主表面108处的第二金属迹线114、以及过孔116，过孔116将绝缘主体104的第一主表面106处的第一金属迹线110中的一些或全部电连接到绝缘主体104的第二主表面108处的第二金属迹线114中的一些或全部。在绝缘主体104的每个主表面106、108处的金属迹线110、114通过绝缘材料118彼此分隔开，在PCB框架的情况下，绝缘材料118例如是在迹线110、114和过孔116的电镀期间所使用的光致抗蚀剂掩模。腔体112形成在绝缘主体104的无导电过孔的区域中。如本文所使用的，术语“过孔”是指绝缘材料中的小开口或孔，其允许不同的层之间的导电连接。即，过孔是允许框架102的专用层之间的电互连的机械结构。
框架102可以具有如图1所示的两层的金属迹线110、114或多于两层的金属迹线。在任一情况下，过孔116将绝缘主体104的第一主表面106处的第一金属迹线110中的一些或全部电连接到绝缘主体104的第二主表面108处的第二金属迹线114中的一些或全部。在框架102具有多于两层的金属迹线110、114的情况下，过孔116将被提供在框架102的多于一个绝缘层118中。
形成在框架102的绝缘主体104中的无过孔腔体112填充有导热和/或导电材料120。填充腔体112的导热和/或导电材料120具有与金属迹线110、114和导电过孔116不同的成分。换言之，填充腔体112的导热和/或导电材料120可以包括与金属迹线110、114和导电过孔116不同的材料(例如，硬化的银浆用于填充腔体112的材料120，并且Cu用于金属迹线110、114和过孔116)，或者填充腔体112的导热和/或导电材料120可以包括与金属迹线110、114和过孔116相同类型但具有一个或多个结构和/或化学上(例如纯度级别、组成部分的浓度级别等)的差异的材料(例如，具有小于99.99％的Cu纯度级别的硬化的Cu浆用于填充腔体112的材料120，并且至少99.99％的纯Cu用于金属迹线110、114和过孔116)。因为填充腔体112的导热和/或导电材料120与金属迹线110、114和过孔116在不同的时间形成和/或通过不同的工艺形成，所以填充腔体112的材料120不具有与金属迹线110、114和过孔116相同的成分——即使它们包含相同类型的材料(例如Cu)。在PCB的情况下，金属迹线110、114可以被图案化到层合到绝缘主体104的层上和/或层合在绝缘主体104的层之间的一个或多个铜片层中。导电过孔116可以通过形成在绝缘主体104中的孔进行镀覆。在一个实施例中，金属迹线110、114和导电过孔116包括通过电化学沉积(ECD)形成的电镀铜。
金属迹线110、114可以被图案化为用于在绝缘主体104的一个或两个主表面106、108处的信号再分布的导电轨，和/或被图案化为用于将一个或多个半导体管芯122附接到半导体封装100的框架102和/或将半导体封装100附接到另一个半导体封装和/或电路板的导电焊盘。例如，一个或多个半导体管芯122可以在绝缘主体104的第一主表面106处附接到框架102，并且电连接到第一金属迹线110并电连接到填充形成在绝缘主体104中的腔体112的导热和/或导电材料120。半导体封装100可以在绝缘主体104的第二主表面108处附接到另一个半导体封装或电路板(未示出)。
诸如导线钉凸块、金属柱、垂直键合线等的管芯互连124可以用于将每个半导体管芯122上的管芯焊盘126附接到被图案化到第一金属迹线110中的对应焊盘128。管芯附接材料128可以用来将管芯互连124连结到被图案化到第一金属迹线110中的焊盘。管芯附接材料128可以具有与填充形成在框架102的绝缘主体104中的腔体112的导热和/或导电材料120相同或不同的成分。例如，可以使用诸如丝网印刷的共同的沉积工艺来形成管芯附接材料128以及填充腔体112的导热和/或导电材料120。
在一个实施例中，填充形成在绝缘主体104中的腔体112的导热和/或导电材料120包括硬化的银浆。在另一个实施例中，填充形成在绝缘主体104中的腔体112的导热和/或导电材料120包括硬化的铜浆。在另一个实施例中，填充形成在绝缘主体104中的腔体112的导热和/或导电材料120包括纳米碳材料。在另一个实施例中，填充形成在绝缘主体104中的腔体112的导热和/或导电材料120包括诸如SAC305的硬化的焊锡浆，SAC305是包含96.5％的锡、3％的银和0.5％的铜的无铅合金。其他类型的导热和/或导电材料也可以填充形成在绝缘主体104中的腔体112。
在每种情况下，腔体112形成在绝缘主体104的无导电过孔的区域中，并且填充腔体112的导热和/或导电材料120具有与框架102的金属迹线110、114和导电过孔116(例如电镀铜)不同的成分(例如，硬化的银浆、硬化的铜浆、纳米碳材料或硬化的焊锡浆)。通过这种方式，由填充绝缘主体104中的腔体112的导热和/或导电材料120提供的导热和/或导电路径不受过孔设计规则或过孔加工限制和容差的约束。例如，典型的PCB热过孔可以具有约为0.5mm2的面积和约为40μm的最小过孔到过孔间距。这样的尺寸限制了可以放置在半导体管芯的热热点或管芯温度趋于更热的任何区域下方的过孔的数量，这影响了封装的热性能。例如，在功率半导体管芯的情况下，严重的电瞬变可以生成可以到达不受控的导通的点的热热点。如果温度继续升高，可能会造成永久损坏。
通过省略在半导体管芯的一个或多个热热点下方的热过孔以有利于本文所述的填充的腔体，与使用过孔相比，可以减小框架102的整体尺寸，和/或可以降低由填充框架102的绝缘主体104中的腔体112的导热和/或导电材料120提供的导热和/或导电路径的热阻，从而减小整体封装成本和/或改善封装100的热性能。在一个实施例中，填充绝缘主体104中的腔体112的导热和/或导电材料120具有的面积是在腔体112的区域外部的个体过孔116的平均面积的至少10倍，例如至少100倍，例如至少200倍，例如至少300倍，例如至少400倍，例如至少500倍。
填充框架102的绝缘主体104中的腔体112的导热和/或导电材料120也可以具有小于可以通过由Cu片轧制/冲压Cu块来实现的最小厚度的厚度。这样的Cu块具有约为125μm的典型的最小厚度，而填充绝缘主体104中的腔体112的导热和/或导电材料120可以具有小于100μm或甚至小于80μm的厚度，与使用Cu块相比，这进一步降低了由填充腔体112的导热和/或导电材料120提供的导热和/或导电路径的热阻。
在一个实施例中，半导体封装100中包括的至少一个半导体管芯122是功率半导体管芯，例如功率MOSFET(金属氧化物半导体场效应晶体管)管芯、IGBT(绝缘栅双极晶体管)管芯、HEMT(高电子迁移率晶体管)管芯、功率二极管管芯等。功率半导体管芯122的面向绝缘主体104的第一主表面106的高功率端子127(例如漏极、集电极或阴极端子)电连接到填充绝缘主体104中的腔体112的导热和/或导电材料120。根据该实施例，功率半导体管芯122的高功率端子127通过填充绝缘主体104中的腔体112的导热和/或导电材料120(而不是通过多个过孔或Cu块)来电连接到绝缘主体104的第二主表面108处的金属迹线114'。半导体封装100可以包括单个半导体管芯122或多于一个管芯122。仅为了便于说明，图1中示出了一个半导体管芯122。
附接到封装100的框架102的至少一个半导体管芯122可以具有多于一个热热点或多于一个其中管芯温度趋于更热的区域。在一个实施例中，框架102还包括形成在绝缘主体104中的至少一个第二腔体130。第二腔体130与第一腔体112在横向上间隔开，并且第二腔体130可以小于第一腔体112。第二腔体130还填充有具有与框架102的金属迹线110、114和过孔116不同的成分的导热和/或导电材料132，并且在绝缘主体104的第一和第二主表面106、108之间提供附加的导热和/或导电路径。在功率半导体管芯122的情况下，功率半导体管芯122的面向绝缘主体104的第一主表面106的第二高功率端子129可以电连接到填充形成在绝缘主体104中的第二腔体130的导热和/或导电材料132。根据该实施例，功率半导体管芯122的第二高功率端子129通过填充绝缘主体104中的第二腔体130的导热和/或导电材料132(而不是通过多个过孔或Cu块)来电连接到绝缘主体104的第二主表面108处的金属迹线114”。
填充形成在绝缘主体104中的第二腔体130的导热和/或导电材料132可以具有或可以不具有与填充形成在绝缘主体104中的第一腔体112的导热和/或导电材料120相同的成分。在一个实施例中，填充第一腔体112的导热和/或导电材料120包括硬化的银浆、硬化的铜浆、纳米碳材料或硬化的焊锡浆，填充第二腔体130的导热和/或导电材料132包括硬化的银浆、硬化的铜浆、纳米碳材料或硬化的焊锡浆，并且框架102的金属迹线110、114和导电过孔116包括电镀铜。例如，可以使用共同的沉积工艺(例如丝网印刷)形成填充形成在绝缘主体104中的第一腔体112的导热和/或导电材料120和填充形成在绝缘主体104中的第二腔体130的导热和/或导电材料132，而框架102的金属迹线110、114和导电过孔116可以通过电镀工艺(例如ECD)形成。
继续功率半导体管芯的示例，功率半导体管芯122还可以具有低功率端子(例如I/O(输入/输出)端子)、感测端子(例如电压、电流和/或温度感测端子)等，其通过过孔116并通过绝缘主体104的第一主表面106处的金属迹线110电连接到绝缘主体104的第二主表面108处的金属迹线114。
半导体封装100还可以包括包封体134，该包封体134在绝缘主体104的第一主表面106处包封每个半导体管芯122。在一个实施例中，框架102是PCB，并且包封体134是模制化合物。
根据图1所示的实施例，填充形成在框架102的绝缘主体104中的每个腔体112、130的导热和/或导电材料120、132未被绝缘主体104的第一主表面106处的金属迹线覆盖。这样，在没有中间金属迹线的情况下，图1所示的半导体管芯122在绝缘主体104的第一主表面106处通过管芯互连124附接到填充每个腔体112、130的导热和/或导电材料120、132。进一步根据该实施例，每个腔体112、130终止于绝缘主体104的第二主表面108处的金属迹线114'，114”。半导体管芯122通过填充相应的腔体112、130的导热和/或导电材料120、132电连接到金属迹线114，金属迹线114使该腔体112、130终止于绝缘主体104的第二主表面108处。使每个腔体112、130终止于绝缘主体104的第二主表面108处的金属迹线114可以被图案化为用于附接到另一半导体封装或诸如PCB的电路板(未示出)的焊盘，并且与填充每个腔体112、130的导热和/或导电材料120、132相比，金属迹线114相对较薄。在一个实施例中，使每个腔体112、130终止于绝缘主体104的第二主表面108处的金属迹线114具有约为15μm至20μm的厚度。
图2示出了半导体封装200的另一个实施例的局部截面图。图2中所示的半导体封装200与图1中所示的半导体封装100相似。然而，不同之处在于，在图2中，形成在封装框架102的绝缘主体104中的至少一个第一腔体112终止于在绝缘主体104的第一主表面106处的金属迹线110'。半导体管芯122附接到使第一腔体112终止于绝缘主体104的第一主表面106处的金属迹线110'，并且通过使第一腔体112终止于绝缘主体104的第一主表面106处的金属迹线110'电连接到填充第一腔体112的导热和/或导电材料120。填充形成在在绝缘主体104中的每个腔体112、130的导热和/或导电材料120、132未被绝缘主体104的第二主表面108处的金属迹线覆盖。
使第一腔体112终止于绝缘主体104的第一主表面106处的金属迹线110'将包封体134与填充第一腔体112的导热和/或导电材料120分隔开。在模制化合物类型的包封体134的情况下，通过用金属迹线110'使第一腔体112终止于绝缘主体104的第一主表面106，消除了模制化合物包封体134与填充第一腔体112的导热和/或导电材料120之间分层的可能性。在腔体填充材料是硬化的焊锡浆的情况下，使第一腔体112终止于绝缘主体104的第一主表面106处的金属迹线110'也缓解了重新熔化的焊料接触模制化合物类型的包封体134的情况。形成在封装框架102的绝缘主体104中的其他腔体130也可以终止于绝缘主体104的第一主表面106处的金属迹线。
图3示出了半导体封装300的另一个实施例的局部截面图。图3所示的半导体封装300与图1所示的半导体封装100相似。然而，不同之处在于，图3中的半导体封装300还包括逻辑管芯302，逻辑管芯302附接到第一半导体管芯122的背离框架102的一侧。在一个实施例中，第一半导体管芯122是功率晶体管管芯，诸如功率MOSFET管芯、IGBT管芯、HEMT管芯等，并且逻辑管芯302包括用于控制功率晶体管管芯122的控制器和/或驱动器电路。逻辑管芯302可以通过管芯附接材料304(例如，焊料、胶等)附接到功率晶体管管芯122。逻辑管芯302可以通过电导体306(例如键合线)电连接到绝缘主体104的第一主表面106处的一些金属迹线110。
图4示出了半导体封装400的另一个实施例的局部截面图。图4所示的半导体封装400与图3所示的半导体封装300相似。然而，不同之处在于，在图4中，逻辑管芯在绝缘主体104的第一表面106处附接到框架102，而不是附接到功率晶体管管芯122。逻辑管芯302具有焊盘402，焊盘402通过与功率晶体管管芯122相同或不同的互连404附接到框架102。
图5示出了制造本文所述的半导体封装100、200、300、400的方法的实施例。图6A至图6D示出了在制造工艺的不同阶段期间的相应的局部截面图。
该方法包括提供框架，例如电路板、塑料模制主体等(方框500)。然后在框架中形成一个或多个腔体(方框502)。一个或多个腔体可以作为例如典型的PCB或塑料模制工艺的部分而形成在框架中。然后形成金属迹线和导电过孔。在铜迹线和过孔的情况下，可以使用ECD表面镀覆工艺来电镀迹线和过孔。利用ECD，在框架的绝缘主体的主表面的未被电镀掩模(例如，光致抗蚀剂)覆盖的区域上形成Cu迹线，并且形成在绝缘主体中的穿通孔的侧壁被电镀有Cu。
图6A示出了在绝缘主体104中形成一个或多个腔体112、130之后以及在形成金属迹线110、114和导电过孔116之后的框架102。
然后，在形成在框架102的绝缘主体104中的每个腔体112、130中填充具有与框架102的金属迹线110、114和导电过孔116不同的成分的导热和/或导电材料120、132(方框506)。在一个实施例中，通过在每个腔体112、130中和形成在绝缘主体104的第一主表面106处的金属迹线110中的互连焊盘上丝网印刷导电浆600，来填充形成在框架102的绝缘主体104中的每个腔体112、130。例如，导电浆600可以是烧结的银浆、烧结的铜浆或烧结的焊锡浆，并且金属迹线110、114和过孔116可以是通过ECD形成的电镀铜。每个填充的腔体112、130在绝缘主体104的第一和第二主表面106、108之间提供导热和/或导电路径。
图6B示出了在用导电浆600填充形成在绝缘主体104中的每个腔体112、130之后的框架102。
然后，在绝缘主体104的第一主表面106处将一个或多个半导体管芯122附接到框架102(方框508)。至少一个半导体管芯122电连接到绝缘主体104的第一主表面106处的金属迹线110并且电连接到形成在绝缘主体104中的每个腔体112、130中的导电浆600。被丝网印刷在互连焊盘上的导电浆600用作将管芯互连124结合到框架102的焊盘的管芯附接材料，该互连焊盘被图案化到绝缘主体104的第一主表面106处的金属迹线110中。在一个实施例中，通过将半导体管芯122的高功率端子127倒装芯片键合到形成在绝缘主体104中的第一腔体112中的导电浆600，并将半导体管芯122的低功率端子倒装芯片键合到被图案化到绝缘主体104的第一主表面106处的金属迹线110中的互连焊盘，来在绝缘主体104的第一表面106处将至少一个半导体管芯122附接到框架102。
图6C示出了在绝缘主体104的第一主表面106处将每个管芯122附接到框架102之后的框架102。可以将附加管芯附接到绝缘主体104的第二主表面106和/或附接到管芯122中的一个或多个管芯，所述管芯122附接到绝缘主体104的第一主表面106，例如如图3所示。
然后，半导体封装经受回流工艺，在该工艺期间，被丝网印刷在每个腔体112、130中和形成在绝缘主体104的第一主表面106处的金属迹线110中的互连焊盘上的导电浆600在升高的温度(并且可选地，升高的压力)下被回流，并且然后导电浆600被冷却直到被硬化，以形成管芯附接材料128，管芯附接材料128将管芯互连124固定到框架102以及填充形成在框架102的绝缘主体104中的每个腔体112的导热和/或导电材料120、132。在绝缘主体104的第一主表面106处附接到框架102的每个半导体管芯122然后被包封在诸如模制化合物的包封体134中(方框510)。可以执行附加的工艺，例如去毛刺、标记、单一化等。
图6D示出了在回流和包封工艺之后的框架102。
图7A至图7C示出了本文所述的半导体封装框架102的不同的层。图7A示出了在绝缘主体104的第一主表面106处的金属迹线110，图7C示出了在绝缘主体104的第二主表面108处的金属迹线114，并且图7B示出了电连接绝缘主体104的相对的主表面106、108处的金属迹线110、114的金属过孔116。如本文先前所述，金属迹线110、114可以被图案化为用于绝缘主体104的一个或两个主表面106、108处的信号再分布的导电轨110a、114a，和/或金属迹线110、114可以被图案化为用于将一个或多个半导体管芯附接到框架102和/或将框架102附接到另一个半导体封装或电路板(未示出)的导电焊盘110b、114b。
绝缘主体104的至少一个区域没有导电过孔。在图7A至图7C中用虚线框示出了一个这样的区域。如图7B所示，其示出了绝缘衬底104的过孔层，在绝缘衬底104的至少一个区域中省略了导电过孔116。这些无过孔区域中的每个被保留用于形成绝缘主体104中的腔体112/130。如本文先前所述的，绝缘主体104中的每个腔体112/130随后填充有具有与框架102的金属迹线110、114和过孔116不同的成分的导热和/或导电材料120/132，以在绝缘主体104的第一和第二主表面106、108之间提供一个或多个单独的导热和/或导电路径。在图7C中，在绝缘主体104的第二主表面108处并且位于被保留用于腔体的无过孔区域内的单独的焊盘114b可以结合在一起以形成单个焊盘。
诸如“第一”、“第二”等的术语用于描述各种元件、区域、部分等，并且也不旨在是限制性的。在整个说明书中，相似的术语指代相似的元件。
如本文中所使用的，术语“具有”、“包含”、“包括”等是开放式术语，其指示所陈述的元件或特征的存在，但是不排除附加的元件或特征。除非上下文另外明确指出，否则冠词“一”和“所述”旨在包括复数以及单数。
应当理解，除非另外特别指出，否则本文所述的各种实施例的特征可以彼此组合。
尽管本文已经示出和描述了特定实施例，但是本领域普通技术人员将理解，在不脱离本发明的范围的情况下，各种替代和/或等效的实施方式可以代替所示出和描述的特定实施例。本申请旨在涵盖本文讨论的特定实施例的任何改变或变型。因此，本发明旨在仅受到权利要求及其等同物的限制。

Claims (21)

1.一种半导体封装，包括：
框架，包括具有第一主表面和与所述第一主表面相对的第二主表面的绝缘主体、所述第一主表面处的第一多个金属迹线、以及在所述绝缘主体中的第一腔体；
导热和/或导电材料，填充所述绝缘主体中的所述第一腔体并且具有与所述第一多个金属迹线不同的成分，所述导热和/或导电材料在所述绝缘主体的所述第一主表面和所述第二主表面之间提供导热和/或导电路径；以及
半导体管芯，所述半导体管芯在所述绝缘主体的所述第一主表面处附接到所述框架，并且电连接到所述第一多个金属迹线并电连接到填充所述绝缘主体中的所述第一腔体的所述导热和/或导电材料。
2.根据权利要求1所述的半导体封装，其中，所述半导体管芯是功率半导体管芯，并且其中，所述功率半导体管芯的面向所述绝缘主体的所述第一主表面的高功率端子电连接到填充所述绝缘主体中的所述第一腔体的所述导热和/或导电材料。
3.根据权利要求2所述的半导体封装，其中，所述框架还包括：所述绝缘主体的所述第二主表面处的一个或多个第二金属迹线；以及一个或多个过孔，所述一个或多个过孔将所述绝缘主体的所述第一主表面处的所述第一多个金属迹线中的一个或多个金属迹线电连接到所述绝缘主体的所述第二主表面处的所述一个或多个第二金属迹线，并且其中，所述功率半导体管芯的所述高功率端子通过填充所述绝缘主体中的所述第一腔体的所述导热和/或导电材料而电连接到所述绝缘主体的所述第二主表面处的金属迹线。
4.根据权利要求3所述的半导体封装，其中，填充所述第一腔体的所述导热和/或导电材料具有至少是个体过孔的平均面积的10倍的面积。
5.根据权利要求2所述的半导体封装，其中，所述框架还包括所述绝缘主体中的第二腔体，其中，所述第二腔体小于所述第一腔体并且在横向上与所述第一腔体间隔开，其中，所述第二腔体填充有导热和/或导电材料，所述导热和/或导电材料具有与所述第一多个金属迹线不同的成分并且在所述绝缘主体的所述第一主表面和所述第二主表面之间提供导热和/或导电路径，并且其中，所述功率半导体管芯的面向所述绝缘主体的所述第一主表面的第二高功率端子电连接到填充所述绝缘主体中的所述第二腔体的所述导热和/或导电材料。
6.根据权利要求2所述的半导体封装，其中，所述功率半导体管芯包括一个或多个低功率端子，所述一个或多个低功率端子通过一个或多个过孔以及所述第一多个金属迹线中的一个或多个金属迹线电连接到所述绝缘主体的所述第二主表面处的一个或多个第二金属迹线。
7.根据权利要求2所述的半导体封装，还包括逻辑管芯，所述逻辑管芯附接到所述功率半导体管芯的背离所述框架的一侧或在所述绝缘主体的所述第一主表面处附接到所述框架，其中，所述逻辑管芯被配置为控制所述功率半导体管芯。
8.根据权利要求1所述的半导体封装，其中，填充所述第一腔体的所述导热和/或导电材料包括硬化的银浆、硬化的铜浆、纳米碳材料或硬化的焊锡浆，并且其中，所述第一多个金属迹线包括电镀铜。
9.根据权利要求1所述的半导体封装，其中，填充所述第一腔体的所述导热和/或导电材料未被所述绝缘主体的所述第一主表面处的金属迹线覆盖，并且其中，所述半导体管芯附接到所述绝缘主体的所述第一主表面处的所述导热和/或导电材料。
10.根据权利要求9所述的半导体封装，其中，所述第一腔体终止于所述绝缘主体的所述第二主表面处的金属迹线，并且其中，所述半导体管芯通过填充所述第一腔体的所述导热和/或导电材料而电连接到使所述第一腔体终止于所述绝缘主体的所述第二主表面处的所述金属迹线。
11.根据权利要求1所述的半导体封装，其中，所述第一腔体终止于所述绝缘主体的所述第一主表面处的金属迹线，其中，所述半导体管芯附接到使所述第一腔体终止于所述绝缘主体的所述第一主表面处的所述金属迹线，并且其中，所述半导体管芯通过使所述第一腔体终止于所述绝缘主体的所述第一主表面处的所述金属迹线而电连接到填充所述第一腔体的所述导热和/或导电材料。
12.根据权利要求11所述的半导体封装，其中，填充所述第一腔体的所述导热和/或导电材料未被所述绝缘主体的第二主表面处的金属迹线覆盖。
13.根据权利要求11所述的半导体封装，其中，所述半导体管芯在所述绝缘主体的所述第一主表面处被包封在模制化合物中，并且其中，使所述第一腔体终止于所述绝缘主体的所述第一主表面处的所述金属迹线将所述模制化合物与填充所述第一腔体的所述导热和/或导电材料分隔开。
14.根据权利要求1所述的半导体封装，其中，所述框架还包括所述绝缘主体中的第二腔体，其中，所述第二腔体小于所述第一腔体并且在横向上与所述第一腔体间隔开，其中，所述第二腔体填充有导热和/或导电材料，所述导热和/或导电材料具有与所述第一多个金属迹线不同的成分并且在所述绝缘主体的所述第一主表面和所述第二主表面之间提供导热和/或导电路径，并且其中，所述半导体管芯电连接到填充所述绝缘主体中的所述第二腔体的所述导热和/或导电材料。
15.根据权利要求14所述的半导体封装，其中，填充所述第二腔体的所述导热和/或导电材料具有与填充所述第一腔体的所述导热和/或导电材料相同的成分。
16.根据权利要求14所述的半导体封装，其中，填充所述第一腔体的所述导热和/或导电材料包括硬化的银浆、硬化的铜浆、纳米碳材料或硬化的焊锡浆，其中，所述第一多个金属迹线包括电镀铜，并且其中，填充所述第二腔体的所述导热和/或导电材料包括硬化的银浆、硬化的铜浆、纳米碳材料或硬化的焊锡浆。
17.一种制造半导体封装的方法，所述方法包括：
在框架的绝缘主体中形成腔体，所述绝缘主体具有第一主表面和与所述第一主表面相对的第二主表面，并且在所述绝缘主体的所述第一主表面处形成第一多个金属迹线；
用导热和/或导电材料填充所述绝缘主体中的所述第一腔体，所述导热和/或导电材料具有与所述第一多个金属迹线不同的成分，所述导热和/或导电材料在所述绝缘主体的所述第一主表面和所述第二主表面之间提供导热和/或导电路径；以及
在所述绝缘主体的所述第一主表面处将半导体管芯附接到所述框架，使得所述半导体管芯电连接到所述第一多个金属迹线并且电连接到填充所述绝缘主体中的所述第一腔体的所述导热和/或导电材料。
18.根据权利要求17所述的方法，其中，用所述导热和/或导电材料填充所述绝缘主体中的所述第一腔体包括：
在所述第一腔体中和形成在所述绝缘主体的所述第一主表面处的所述第一多个金属迹线中的互连焊盘上丝网印刷导电浆。
19.根据权利要求18所述的方法，其中，所述导电浆是银浆、铜浆或焊锡浆，并且其中，在所述导电浆的所述丝网印刷之前，通过电化学沉积形成所述第一多个金属迹线。
20.根据权利要求17所述的方法，其中，在所述绝缘主体的所述第一主表面处将所述半导体管芯附接到所述框架包括：
将所述半导体管芯的高功率端子倒装芯片键合到填充所述绝缘主体中的所述第一腔体的所述导热和/或导电材料，并将所述半导体管芯的多个低功率端子倒装芯片键合到所述绝缘主体的所述第一主表面处的所述互连焊盘。
21.一种半导体封装，包括：
框架，包括绝缘主体、所述绝缘主体的第一主表面处的第一金属迹线、所述绝缘主体的与所述第一主表面相对的第二主表面处的第二金属迹线、将所述第一主表面处的所述第一金属迹线中的一些或全部电连接到所述第二主表面处的所述第二金属迹线中的一些或全部的过孔、以及形成在所述绝缘主体的无导电过孔的区域中的腔体；
填充所述绝缘主体中的所述腔体的硬化的银浆、硬化的铜浆、纳米碳材料或硬化的焊锡浆；以及
半导体管芯，所述半导体管芯在所述绝缘主体的所述第一主表面处附接到所述框架，并且电连接到所述第一金属迹线中的一些或全部并电连接到填充所述绝缘主体中的所述腔体的所述硬化的银浆、硬化的铜浆、纳米碳材料或硬化的焊锡浆。
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