CN111555725B - Amplifier linearization device - Google Patents
Amplifier linearization device Download PDFInfo
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- CN111555725B CN111555725B CN201911308366.4A CN201911308366A CN111555725B CN 111555725 B CN111555725 B CN 111555725B CN 201911308366 A CN201911308366 A CN 201911308366A CN 111555725 B CN111555725 B CN 111555725B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
Abstract
The invention provides an amplifier linearization device, which comprises an amplifier and a linearization device. The linearizer includes a first transistor including a first terminal coupled to an input of the amplifier, a second terminal coupled to a direct current power supply, and a control terminal configured to control a current flowing between the first terminal and the second terminal and to receive a direct current bias voltage different from a voltage of the first terminal. The present invention compensates for the amplifier by using a linearizer such that the linearizer and the amplifier are combined together with improved overall linearity.
Description
Technical Field
The present invention relates to an amplifier, and more particularly, to improving linearity of an amplifier by using a linearizer (linearise).
Background
Power amplifiers are known electronic devices for increasing the power of alternating current (Alternating Current, AC) signals. In general, an amplifier multiplies a voltage amplitude of an AC signal input to the amplifier by a gain factor using power from a Direct Current (DC) power supply, and provides the multiplied signal as an output.
It is desirable that the amplifier operates linearly over as wide a voltage amplitude range as possible. The ac signal output by the amplifier is proportional to the input ac signal by a gain factor within an input voltage range in which the amplifier operates linearly. The amplifier operates non-linearly over a range of input voltages where the gain factor is non-constant, which is undesirable.
Disclosure of Invention
It is therefore an object of the present invention to provide a technique for improving the linearity of an amplifier, in which the above-mentioned problems are solved by compensating for the nonlinearity of the amplifier using a linearizer (linearise).
According to one embodiment of the present invention, there is provided an amplifier linearization apparatus including an amplifier and a linearizer. The linearizer includes a first transistor including a first terminal coupled to an input of the amplifier, a second terminal coupled to a direct current power supply, and a control terminal configured to control a current flowing between the first terminal and the second terminal and to receive a direct current bias voltage different from a voltage of the first terminal.
According to another embodiment of the present invention, there is provided an amplifier linearization apparatus including an amplifier and a linearizer. The amplifier includes an input, an output, and a first set of transistors coupled between the input and the output, the first set of transistors including one or more transistors. The linearizer includes a second set of transistors coupled between the dc power supply and an input of the amplifier, the second set of transistors including one or more transistors. Wherein the first set of transistors and the second set of transistors have the same topology.
The present invention compensates for the amplifier by using a linearizer such that the linearizer and the amplifier are combined together with improved overall linearity.
These and other objects of the present invention will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments, as illustrated in the various figures and drawings.
Drawings
Fig. 1A is a block diagram illustrating an example system including an amplifier compensated by a linearizer, in accordance with some embodiments.
FIG. 1B shows a series of graphs corresponding to the system shown in FIG. 1A.
Fig. 2A is a circuit diagram of an example system including a single-ended amplifier compensated by a linearizer, in accordance with some embodiments.
Fig. 2B is a circuit diagram of an example system including a single-ended amplifier compensated by a cascode linearizer, in accordance with some embodiments.
Fig. 2C is a circuit diagram of an example system including a differential amplifier compensated with a linearizer, in accordance with some embodiments.
Fig. 3A is a circuit diagram of an example system including a cascode differential amplifier compensated with a cascode (cascode) linearizer, in accordance with some embodiments.
Fig. 3B is a circuit diagram of an example system including a cascode single-ended amplifier compensated by a cascode linear amplifier, according to some embodiments.
Fig. 4A is a circuit diagram of an example system including a single-ended amplifier compensated by a linearizer coupled to an output, in accordance with some embodiments.
Fig. 4B is a circuit diagram of an example system including a cascode differential amplifier compensated by a cascode linear amplifier coupled at an output, according to some embodiments.
Fig. 5A is a circuit diagram of an example system including a single-ended amplifier compensated with a PMOS linearizer, in accordance with some embodiments.
Fig. 5B is a circuit diagram of an example system including a single-ended amplifier compensated by PMOS and NMOS linearizers, in accordance with some embodiments.
Detailed Description
The implementation of an amplifier, such as a power amplifier used in a radio-frequency (RF) transmission system, involves a tradeoff between efficiency and linearity of the amplifier. Amplifiers with better linearity typically have poor operating efficiency and typically dissipate more than half of the total operating power as heat rather than being converted into an AC signal at the output of the amplifier. For example, class a power amplifiers can operate linearly over a wide range of input voltages, but their operating efficiency is less than 50%, and often even less than 10%, as compared to class C power amplifiers. Amplifiers with better operating efficiency typically have poor linearity with a relatively small voltage range over which the gain factor is constant. For example, a class C power amplifier may operate at an efficiency of up to 70% or more, but operate linearly over a significantly reduced input voltage range as compared to a class a amplifier. The choice of amplifier thus involves a trade-off between efficiency and linearity.
The present invention proposes a technique for compensating an amplifier by using a linearizer (linearise) to improve linearity in a system having a nonlinear amplifier. A linearizer may be coupled to the input of the amplifier and configured to provide a non-constant impedance transfer function (impedance transfer function) for the AC signal received at the input of the amplifier. The non-constant impedance transfer function of the linearizer may compensate for the non-linear response of the amplifier over a range of input voltages. For example, if the gain factor of the amplifier increases over a certain voltage range due to nonlinearity of the amplifier, the impedance transfer function of the linearizer may be compensated by decreasing over the voltage range, such that the overall linearity of the linearizer together with the amplifier is improved over the entire voltage range. Thus, the combination of the linearizer and the amplifier may be implemented with improved overall linearity compared to an amplifier alone.
Fig. 1A is a block diagram illustrating an example system 100, the system 100 including an amplifier 130 compensated by a linearizer 110, in accordance with some embodiments. Linearizer 110 is coupled in parallel with amplifier 130. Inputs 102a and 102b of system 100 are coupled to each of linearizer 110 and amplifier 130, and outputs 104a and 104b of system 100 are coupled to amplifier 130. In some embodiments, as shown in dashed lines in fig. 1A, outputs 104a and 104b may be coupled to linearizer 110.
Linearizer 110 and amplifier 130 are coupled between inputs 102a and 102b and outputs 104a and 104b. As a non-limiting example, inputs 102a and 102b may be coupled to a baseband-to-RF mixer and outputs 104a and 104b may be coupled to an RF antenna. The AC signals received at inputs 102a and 102b and generated at outputs 104a and 104b may be differential signals, with a high (+) signal received at input 102a and generated at output 104a and a low (-) signal received at input 102b and generated at output 104b. Alternatively, the AC signal may be a single ended signal. For example, input 102b and output 104b may not be included, or input 102b and output 104b may be connected to a fixed reference voltage.
Amplifier 130 may be used to multiply the signals received at inputs 102a and 102b by a gain factor and provide the results to outputs 104a and 104b. Amplifier 130 may include one or more transistors and the gain factor of amplifier 130 may be set based on the configuration of the transistors, such as the placement and connection of the transistors and the voltage bias conditions.
Linearizer 110 may be used to provide a nonlinear shunt impedance (shunt) for the AC signals received at inputs 102a and 102b of system 100. For example, the linearizer 110 may be coupled between the inputs 102a and 102b and a DC power supply. The AC signal received at inputs 102a and 102b may be conducted through linearizer 110 to a DC power supply such that linearizer 110 provides a shunt impedance for system 100. The linearizer 110 may comprise one or more transistors, and the nonlinear shunt impedance of the linearizer 110 may be set based on the configuration of the transistors (e.g., placement and connection of the transistors and voltage bias conditions).
In the system 100, the combination of the linearizer 110 and the amplifier 130 can provide an overall transfer function with improved linearity compared to the gain factor of the amplifier 130. When combined, the overall transfer function of the system 100 between the inputs 102a and 102b and the outputs 104a and 104b is significantly more constant over the AC signal voltage range than the gain factor of the amplifier 130. For example, amplifier 130 may have a nonlinear gain factor over a particular voltage range of the signals received at inputs 102a and 102 b. To compensate for the nonlinear gain factor of amplifier 130, linearizer 110 may be configured to provide a nonlinear impedance such that the overall transfer function between inputs 102a and 102b and outputs 104a and 104b has improved linearity over the particular voltage range as compared to the gain factor of amplifier 130. The gain factor of the amplifier 130, the nonlinear impedance of the linearizer 110, and the overall transfer function of the system 100 will be described herein with reference to fig. 1B.
Although not shown in fig. 1A, it should be appreciated that both the linearizer 110 and the amplifier 130 are connected to a DC power supply. For example, linearizer 110 may couple an AC signal received at inputs 102a and 102b to a DC power supply, and amplifier 130 may convert power received from the DC power supply to signal power to amplify the AC signal at outputs 104a and 104b.
FIG. 1B showsA series of graphs 150, 170, and 190 corresponding to various transfer functions of components in the system 100 as shown in fig. 1A. Graph 150 shows the impedance transfer function 154 of the linearizer 110, as well as the constant impedance transfer function 152. Graph 170 shows the gain factor 174 of the amplifier 130, as well as a constant gain factor 172. Graph 190 shows the overall transfer function 194 of the system 100 from the inputs 102a and 102 to the outputs 104a and 104b, as well as the constant transfer function 192. For example, the overall transfer function 194 is the product of the impedance transfer function 154 and the gain factor 174. The impedance transfer function 154, gain factor 174, and overall transfer function 194 are at the input voltage V IN V of (2) 1 To V 2 Drawing in a range.
As shown in graph 150, the impedance transfer function 154 of the linearizer 110 is at V 1 To V 2 Which deviates from the constant impedance transfer function 152. For example, the linearizer 110 may include one or more transistors biased at V 1 And V 2 Creating a desired nonlinear channel impedance (channel impedance). Thus, the impedance transfer function 154 is relative to the slave V 1 To V 2 Is set to the input voltage V of IN Is nonlinear.
As shown in graph 170, the gain factor 174 of the amplifier 130 is at voltage V 1 And V 2 Which deviates from the constant gain factor 172. For example, the amplifier 130 may be at a voltage V 1 And V 2 Class C power amplifiers with poor linearity in between. Thus, the gain factor 174 is relative to the slave V 1 To V 2 Is set to the input voltage V of IN Is nonlinear.
As shown in graph 190, the overall transfer function 194 of the system 100 (including the amplifier 130 and the shunt-coupled linearizer 110), at voltage V 1 And V 2 Which is substantially equal to the constant transfer function 192. The product of the impedance transfer function 154 and the gain factor 174 may be generated at a voltage V 1 And V 2 An overall transfer function with improved linearity. For example, the transistor of the linearizer 110 may be biased to produce a non-linear channel impedance of the transistor, which may cancel out the currentPressure V 1 And V 2 And non-linearities in the gain factor 174 of the intermediate amplifier 130. Since the overall transfer function 194 is the product of the impedance transfer function 154 and the gain factor 174, the overall transfer function 194 is at a voltage V compared to the gain factor 174 1 And V 2 With improved linearity therebetween.
The present invention proposes a linearizer implemented by one or more transistors coupled to an amplifier. For example, the transistors may be coupled to an input of an amplifier, with channels (channels) of the transistors configured to provide a nonlinear impedance to a signal received at the input. Fig. 2A-2C illustrate circuit diagrams of exemplary systems 200a, 200b, and 200C, each having a linearizer implemented with one or more transistors coupled to an amplifier. Each of the systems 200a, 200B, and 200c may be configured to operate in the manner described in connection with the system 100 of fig. 1A-1B.
Fig. 2A is a circuit diagram illustrating a system 200a, the system 200a including a single-ended amplifier 230a coupled between an input 202 and an output 204 that is compensated by a linearizer 210 a. System 200a is shown as a single ended system. Thus, the signal received at the input 202 and provided at the output 204 may be a single ended signal.
Amplifier 230a includes a transistor 232 that may be configured to amplify the signal received at the control terminal and provide an amplifier result at a channel terminal (channel terminal) coupled to output 204. In the example embodiment of fig. 2A, transistor 232 is a common-source configured FET and the control terminal of transistor 232 is a gate (gate) connected to input 202. The drain of transistor 232 is connected to output 204 and is also connected to a matching network 242 (e.g., a linear passive matching network). The matching network 242 may include passive components such as inductors and/or balun(s). The matching network 242 is coupled to the current mirror 240, and the current mirror 240 provides current to the bias transistor 232. In some embodiments, the drain of transistor 232 may be connected to the source of a cascode transistor (cascode transistor), the drain of which may be coupled to current mirror 240. The source of transistor 232 is coupled to a common voltage terminal, such as ground. However, the source of transistor 232 may be coupled to other components. For example, in some embodiments, the source of transistor 232 is coupled to current mirror 240.
In the illustrated common source configuration, the transistor 232 is configured to receive an AC signal at its gate, amplify the AC signal based on a gain factor, and provide a gained AC signal at its drain. For example, the gain factor may be set based on the DC bias voltages at the gate, drain, and source of transistor 232 and based on the current provided by current mirror 240. The gain factor may be non-linear over a range of AC signal voltages at the gate. At a drain coupled to the output 204, the transistor 232 may provide a gained AC signal.
It should be appreciated that some embodiments do not include current mirror 240. For example, in some embodiments, the matching network 242 may be coupled to the DC power source 206. In some embodiments, transistor 232 may receive an input or provide an output to one or more transistors of an additional amplification stage of amplifier 230a. It should be appreciated that the transistor 232 may have different amplifier configurations, such as common-gate or common-drain. In addition, the transistor 232 may be a different type of transistor, such as BJT, HEMT, IGBT or HBT, and the like, and similarly may have a configuration adapted to the corresponding transistor type, such as a common-base (common-base), a common-emitter (common-emitter), or a common-collector (common-collector).
Linearizer 210a is configured to provide a nonlinear impedance to compensate for amplifier 230a. In fig. 2A, linearizer 210a includes a transistor 212 having a channel coupled between input 202 and DC power supply 206, and having a control terminal connected to a DC bias voltage 214, DC bias voltage 214 being different from the AC signal received at input 202. The transistor 212 may be configured such that an AC signal received at the input 202 is conducted to the DC power supply 206 through the nonlinear channel impedance. The DC power source 206 may constitute an alternating current ground for the AC signal received at the input 202. For example, the AC signal received at input 202 may include an AC component that operates around a DC bias and is substantially free of an AC component at DC power source 206. Thus, while the AC signal is not fully grounded at the DC power supply 206 due to the direct current component of the signal still being present, the alternating current component of the AC signal is negligible at the DC power supply 206, just like ground. In fig. 2A, transistor 212 is a FET with its source coupled to input 202, its drain coupled to DC power supply 206, and its control terminal (gate) for controlling the current flowing between the source and drain. If the FET is biased into the saturation region, the channel impedance of the FET may be nonlinear such that the channel impedance varies according to the voltage of the AC signal at the input 202. It should be appreciated that transistor 212 may be a different type of transistor, such as BJT, HEMT, IGBT or HBT. In this example, the voltage at the control terminal of transistor 212 should be at least a threshold voltage higher than the voltage at the source to which it is coupled to input 202, and should be at least a threshold voltage less than the voltage of DC power supply 206 to which its drain is coupled.
The invention also proposes a linearizer implemented with selectable impedance. For example, one or more transistors of the linearizer may receive a selectable control terminal bias voltage (e.g., a gate bias voltage for a FET or a base bias voltage for a BJT), which enables the impedance of the linearizer to be selected. For example, the control terminal bias voltage may set the channel impedance of the transistor, which contributes to the impedance of the linearizer. In fig. 2A, a DC bias voltage 214 sets the nonlinear channel impedance of transistor 212. Accordingly, a certain desired nonlinear channel impedance for the AC signal coupled between the input 202 and the DC power supply 206 through the transistor 212 may be achieved by setting the DC bias voltage 214 accordingly. For example, the DC bias voltage 214 may set a particular nonlinear channel impedance for a received AC signal operating between a first AC voltage level and a second AC voltage level. In some embodiments, the DC bias voltage 214 may be an optional bias voltage for producing a desired nonlinear channel impedance of the transistor 212.
Implementing the linearizer with selectable impedance may reduce the overall size of the linearizer, thereby reducing manufacturing costs and improving the operating efficiency of the linearizer. In a linearizer without selectable impedance, the impedance of the linearizer may be set by the channel dimensions of the devices within the linearizer. For example, the linearizer may comprise diode-connected transistors, with the impedance of the linearizer being set by the channel dimensions (e.g., channel width) of the transistors. To compensate for the nonlinear response of the amplifier, the transistors of such linearizers need to have channel widths approximately the same size as the transistors of the amplifier to match the current density of the amplifier. However, the channel width of the transistor in the amplifier may be large, and thus when implemented as an integrated circuit, the implementation of a linearizer that compensates the amplifier will result in an increase in manufacturing cost. In addition, a large transistor channel width will result in a large transistor internal capacitance, requiring more power to turn on the transistor. Thus, the linearizer may have a higher cost and require more power to operate.
A linearizer implemented with selectable impedance, such as described herein with reference to fig. 2A, may be configured to provide a desired impedance with a smaller channel width than a linearizer without selectable impedance. The impedance of the linearizer may be set not only based on the channel width of the transistor of the linearizer but also in accordance with the selectable control terminal bias voltage of the transistor. For example, the control terminal bias voltage may be set relative to the control terminal bias voltage of one or more transistors of the amplifier to adjust for nonlinearities in the amplifier. When the control terminal bias voltage can compensate for the effect of the channel width reduction on the resistance of the linearizer, the channel width of the transistor of the linearizer can be reduced. Thus, the linearizer can be implemented with a smaller channel width than a linearizer without selectable impedance while maintaining the ability to match the current density in the amplifier, thereby reducing manufacturing costs and improving operating efficiency. In some embodiments, the channel width of the transistor of the linearizer may be between 5% and 10% of the channel width of the transistor of the amplifier.
The present invention proposes a linearizer implemented as a transistor (e.g. common gate for FET or common base for BJT) comprising a common-control terminal (common-control terminal) configuration. For example, in FIG. 2A, transistor 212 is a common-gate (FET) configured with a source coupled to input 202 and a drain coupled to DC power supply 206A. The gate of transistor 212 is coupled to a DC bias voltage that is different from the DC supply voltage and from the voltage at input 202.
The present invention proposes a linearizer implemented as a transistor with a cascode (cascode) common control terminal configuration. For example, the first and second FETs may be arranged in a common-gate configuration between the input of the amplifier and the DC power supply. Fig. 2B is a circuit diagram illustrating a system 200B, the system 200B including a single-ended amplifier 230B compensated by a cascode linearizer 210B coupled between the input 202 and the DC power source 206. As shown in fig. 2B, the linearizer 210B includes transistors 212a and 212B having a cascode topology. It should be appreciated that system 200b may be configured to operate in the manner described in connection with system 200 a. For example, amplifier 230b may be configured to operate in the manner described for amplifier 230a.
Linearizer 210b may be configured to provide a nonlinear impedance between input 202 and DC power supply 206 based on DC bias voltages 214a and 214b provided at the control terminals of transistors 212a and 212b. The DC bias voltages 214a and 214b may be configured to set the nonlinear channel impedance of each of the transistors 212a and 212b. The DC bias voltages 214a and 214b may be selectable bias voltages for producing a desired nonlinear channel impedance of the transistors 212a and 212b. Thus, the AC signal received at input 202 is conducted through the nonlinear channel impedance of transistors 212a and 212b set by DC bias voltages 214a and 214 b. It should be appreciated that the DC bias voltages 214a and 214b may be the same DC bias voltage or may be different DC bias voltages.
The invention proposes a linearizer configured for use in a differential system. Fig. 2C is a circuit diagram illustrating a system 200C that includes a differential amplifier 230C coupled between input terminals 202a and 202b and output terminals 204a and 204b that is compensated by a linearizer 210C. In contrast to the systems 200a and 200b, the signals received at the inputs 202a and 202b of the system 200c may be differential signals, with the high value component of the differential signal being received at the input 202a and the low value component of the differential signal being received at the input 202 b. As shown in fig. 2C, linearizer 210C may be configured to provide a nonlinear impedance to the differential signals received at inputs 202a and 202 b.
The amplifier 230c may be configured to operate in the manner of the amplifiers 230a and 230B described in connection with fig. 2A-2B. However, in contrast to fig. 2A and 2B, amplifier 230c is configured to amplify the differential signals received at inputs 202A and 202B. For example, amplifier 230c includes transistors 232a and 232b, wherein transistor 232a is configured to amplify a high value component of the differential signal received at input 202a and transistor 232b is configured to amplify a low value component of the differential signal received at input 202 b. As shown in fig. 2C, the control terminals of transistors 232a and 232b are coupled to inputs 202a and 202b, and the channels of transistors 232a and 232b are coupled to outputs 204a and 204b. The gain factors of transistors 232A and 232b may be set by DC biasing at the control terminals and across the channels of transistors 232A and 232b, as described in connection with fig. 2A for transistor 232. Transistors 232a and 232b are also configured to provide respective amplified components of the differential signal at outputs 204a and 204b, respectively. The DC bias conditions of transistors 232a and 232b may be substantially the same such that transistors 232a and 232b have substantially the same gain factor to avoid adding distortion to the components of the signals provided at outputs 204a and 204b.
The linearizer 210c includes a transistor 212a coupled between the input 202a and the DC power supply 206, and a transistor 212b coupled between the input 202b and the DC power supply 206. The control terminals of the transistors 212a and 212b are coupled to the DC bias voltages 214a and 214b such that the nonlinear channel impedance of the transistors 212a and 212b can be set according to the DC bias voltages 214a and 214 b. For example, the DC bias voltages 214a and 214b may be selectable bias voltages for producing a desired nonlinear channel impedance for the transistors 212a and 212b. Transistors 212a and 212b may be substantially the same size and substantially equivalent configuration, e.g., having substantially equal DC bias voltages 214a and 214b, to avoid adding distortion to the differential signals received at inputs 202a and 202 b. Distortion in the signals at the control terminals of transistors 232a and 232b of amplifier 230c will produce lower quality signals, which is detrimental to a system configured to receive the signals provided by outputs 204a and 204b of system 200 c.
The linearizer proposed by the present invention can be implemented with the same topology as the amplifier it is to compensate for. Fig. 3A-3B illustrate an exemplary system including an amplifier and a linearizer having the same topology, according to some embodiments.
Fig. 3A is a circuit diagram illustrating a system 300a, the system 300a including a cascode differential amplifier 330a coupled between input terminals 302a and 302b and output terminals 304a and 304b, compensated with a cascode (cascode) linearizer 310 a. The linearizer 310a and the amplifier 330a each have a cascode configuration and thus the same topology. In the illustrated embodiment, linearizer 310a and amplifier 330a each have a cascode topology. It should be appreciated that system 300a may be configured to operate in the manner described in connection with fig. 2C. For example, system 300a may be configured to receive differential signals at inputs 302a and 302 b.
Amplifier 330a may have a cascode topology with transistors 332a, 332b, 332c, and 332 d. Transistors 332a and 332b may have a common-control terminal (common-control terminal) configuration. For example, transistors 332a and 332b may be FETs with gates connected to DC bias voltages 334a and 334b, and DC bias voltages 334a and 334b may be the same. Transistors 332c and 332d may have a common-channel terminal (common-channel terminal) configuration. For example, transistors 332c and 332d may be FETs with gates coupled to inputs 302a and 302b and drains coupled to transistors 332a and 332b such that amplifier 330a has a cascode topology.
Linearizer 310a may include transistors 312a, 312b, 312c, and 312d configured in a cascode topology. Transistors 312a, 312b, 312c, and 312d may be biased by DC bias voltages 314a, 314b, 314c, and 314 d. The DC bias voltages 314a and 314b may be substantially equal and the DC bias voltages 314c and 314d may be substantially equal, thereby avoiding adding distortion to the signals received at the inputs 302a and 302 b. In some embodiments, the DC bias voltages 314a, 314b, 314c, and 314d may all be substantially equal to each other.
Fig. 3B is a circuit diagram illustrating a single-ended system 300B, the single-ended system 300B including a cascode single-ended amplifier 330B coupled between an input 302 and an output 304 that is compensated by a cascode linear amplifier 310B. The linearizer 310b and the amplifier 330b each have a cascode configuration and thus the same topology. The system 300B may be configured to operate in the manner described in connection with fig. 2B.
The invention proposes a linearizer coupled to the input and output of an amplifier to be compensated. Fig. 4A-4B are circuit diagrams illustrating an exemplary system including an amplifier and an output-coupled linearizer, in accordance with some embodiments.
Fig. 4A is a circuit diagram illustrating a system 400a, the system 400a including a single-ended amplifier 430a coupled between an input 402 and an output 404 that is compensated by an output-coupled linearizer 410 a. System 400a may be configured to operate in the manner described for system 200a in connection with fig. 2A. For example, linearizer 410a may be configured to provide a nonlinear impedance in parallel with amplifier 430a to a signal received at input 402. In addition, the signal received at input 402 may be coupled to output 404 through linearizer 410 a.
Since the signals conducted through linearizer 410a may not be frequency shifted, these signals may be superimposed at the output of amplifier 430a. Thus, system 400a may hold (preserve) substantially all of the signal received at input 402 and provide an amplifier signal at output 404. It should be appreciated that in some embodiments, linearizer 410a may be configured to match the phase shift (phase shift) of amplifier 430a such that a signal received at input 402 passes through linearizer 410a to output 404 in phase (in phase) with a signal passing through amplifier 430a to output 404. In some embodiments, linearizer 410a may be configured to provide a 180 degree phase offset such that a signal received at input 402 passes through linearizer 410a to output 404 in anti-phase (out of phase) with a signal passing through amplifier 430a to output 404. According to various embodiments, linearizer 410a may be configured to provide any desired phase offset to the signal received at input 402. Additionally, it should be appreciated that although the linearizer 410a and the amplifier 430a are shown as having the same non-cascode (non-cascode) topology, the linearizer 410a and the amplifier 430a may have different topologies according to various embodiments.
Fig. 4B is a circuit diagram illustrating an exemplary system 400B according to some embodiments, the exemplary system 400B including a cascode differential amplifier 430B compensated by a cascode linear amplifier 410B coupled at an output. The system 400b may be configured to operate in the manner described in connection with fig. 4A. For example, linearizer 410b, coupled between inputs 402a and 402b and outputs 404a and 404b, may be configured to provide a nonlinear impedance in parallel with amplifier 430b. In contrast to fig. 4A, however, system 400b is configured to receive differential signals at inputs 402a and 402b, and linearizer 410b and amplifier 430b have a cascode topology. It should be appreciated that linearizer 410b and amplifier 430b may be configured to operate in the manner described in connection with linearizer 310a and amplifier 330a of fig. 3A.
Fig. 5A is a circuit diagram illustrating an exemplary system 500a, the system 500a including a single-ended amplifier 530a compensated with a PMOS linearizer 510a, in accordance with some embodiments. The system 500a may be configured to operate in the manner described in connection with fig. 2A. For example, linearizer 510a may be configured to provide a nonlinear impedance in parallel with amplifier 530a. However, in contrast to the linearizer 210a of fig. 2A, the linearizer 510a includes a PMOS transistor 512 having a control terminal biased by a DC bias voltage 514. In some embodiments, the DC bias voltage 514 may be a negative supply voltage from the DC power supply 506. It should be appreciated that linearizer 510a may be configured to operate in the manner described in connection with linearizer 210a of fig. 2A. In this example, the voltage at the control terminal of PMOS transistor 512 should be at least a threshold voltage less than the voltage at the source to which it is coupled to input 202, and should be at least a threshold voltage higher than the voltage of DC power supply 506 to which its drain is coupled.
Fig. 5B is a circuit diagram illustrating an exemplary system 500B according to some embodiments, the exemplary system 500B including a single-ended amplifier 530B compensated by PMOS and NMOS linearizers 510B. The system 500b may be configured to operate in the manner described in connection with fig. 2A. For example, linearizer 510b may be configured to provide a nonlinear impedance in parallel with amplifier 530b. However, in contrast to the linearizer 210a of fig. 2A, the linearizer 510b includes an NMOS transistor 512A and a PMOS transistor 512b. The NMOS transistor 512A is biased by a DC bias voltage 514a, which DC bias voltage 514a may be configured in the manner described in connection with fig. 2A for the DC bias voltage 214. PMOS transistor 512b is biased by DC bias voltage 514b, which DC bias voltage 514b may be configured in the manner described in connection with DC bias voltage 514 of fig. 5A.
The various aspects of the devices and techniques described herein may be used alone, in combination, or in a variety of arrangements not specifically discussed in the embodiments described in the foregoing and is therefore not limited in its application to the details and arrangement of components set forth in the foregoing description or illustrated in the drawings. For example, aspects described in one embodiment may be combined in any manner with aspects described in other embodiments.
It should be appreciated that the above-described transistors may be implemented in any of a variety of ways. For example, one or more of the transistors may be implemented as bipolar junction transistors or field-effect transistors (FETs), such as metal-oxide semiconductor field-effect transistor, MOSFETs, junction field-effect transistors (JFETs), heterostructure field-effect transistors (heterostructure field-effect transistor, HFETs), heterojunction bipolar transistors (heterojunction bipolar transistor, HBTs), and high electron mobility transistors (high electron mobility transistor, HEMTs). Where one or more transistors described herein are implemented as BJTs, the gate, source and drain terminals described above for such transistors may be base, emitter and collector terminals, respectively.
In addition, it should be understood that the amplifiers described herein may include multiple cascode stages of transistors in a common source, common control terminal, and/or common source common gate configuration. In some embodiments, amplifier 130 may comprise a class C power amplifier. In some embodiments, the amplifiers described herein may include power amplifiers belonging to any of the A, B, AB, C, D, E, F, G and H classes. In some embodiments, amplifier 130 may comprise a low noise amplifier.
Additionally, it should be appreciated that the illustrated embodiment omitting current mirror 240 may also be adapted to include current mirror 240.
Ordinal terms such as "first," "second," "third," and the like in the claims to modify a claim element does not by itself connote any priority, precedence, or order of one claim element over another or the temporal order in which steps of a method are performed, but are used merely as labels to distinguish one claim element having a same name from another element having a same name.
Also, the phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting. The use of "including," "comprising," "having," "containing," or "involving," and variations thereof herein, is meant to encompass the items listed thereafter and equivalents thereof as well as additional items.
By "coupled" or "connected" is meant that the circuit elements or signals may be connected directly to each other or through intermediate components.
The terms "about," "substantially," and "about" may in some embodiments mean within ±20% of the target value, in some embodiments within ±10% of the target value, in some embodiments within ±5% of the target value, and in some embodiments within ±2% of the target value. The terms "substantially," "about," and "approximately" may include target values.
Claims (17)
1. An amplifier linearization apparatus, comprising:
an amplifier; and
a linearizer comprising a first transistor comprising:
a first terminal coupled to an input of the amplifier;
a second terminal configured to receive a dc power supply voltage transmitted from a dc power supply to the second terminal; and
a control terminal configured to control a current flowing between the first terminal and the second terminal and configured to receive a dc bias voltage different from a voltage of the first terminal, wherein the dc bias voltage is a bias voltage selectable from a plurality of dc bias voltages.
2. The apparatus of claim 1, wherein, in response to receiving the dc bias voltage, the first transistor is configured to control an impedance between the first terminal and the second terminal to produce a desired nonlinear channel impedance at a particular voltage interval to cancel a nonlinear gain factor of the amplifier.
3. The apparatus of claim 1, wherein the amplifier comprises a first transistor having a common channel terminal configuration.
4. The apparatus of claim 3, wherein the amplifier further comprises a second transistor having a common control terminal configuration.
5. The apparatus of claim 4, wherein the first transistor of the amplifier and the second transistor of the amplifier are field effect transistor FETs having common source and common gate configurations, respectively.
6. The apparatus of claim 1, wherein the linearizer further comprises a second transistor, the first transistor coupled to an input of the amplifier through the second transistor, the second transistor comprising:
a first terminal coupled to an input of the amplifier;
a second terminal coupled to the first terminal of the first transistor; and
a control terminal configured to control a current flowing between the first terminal of the second transistor and the second terminal of the second transistor, and configured to receive another direct current bias voltage different from a voltage of the first terminal of the second transistor.
7. The apparatus of claim 1, wherein the second terminal of the first transistor is coupled to an output of the amplifier.
8. The apparatus of claim 1, wherein the voltage at the control terminal is:
at least a threshold voltage of the first transistor greater than a voltage at the first terminal and at least the threshold voltage less than a voltage at the second terminal; or alternatively
At least the threshold voltage less than the voltage at the first terminal and at least the threshold voltage greater than the voltage at the second terminal.
9. An amplifier linearization apparatus, comprising:
an amplifier, comprising:
an input end;
an output end; and
a first set of transistors coupled between the input and the output, the first set of transistors including one or more transistors; and
a linearizer comprising:
a second set of transistors coupled between a dc power source and the input of the amplifier, the second set of transistors comprising one or more transistors;
wherein the first set of transistors and the second set of transistors have the same topology,
wherein the second set of transistors is configured to receive a dc supply voltage that is transferred from the dc supply to the second set of transistors.
10. The apparatus of claim 9, wherein the first set of transistors and the second set of transistors each comprise a cascode topology or each comprise a non-cascode topology.
11. The apparatus of claim 10, wherein the first and second sets of transistors each comprise a cascode topology, and wherein the respective first and second transistors of the first set of transistors comprise a common control terminal configuration and a common channel terminal configuration.
12. The apparatus of claim 11, wherein channels of a first transistor and a second transistor of the second set of transistors are coupled to each other between the input of the amplifier and the dc power supply.
13. The apparatus of claim 12, wherein the first and second transistors of the first set of transistors are field effect transistor FETs comprising a common gate configuration and a common source configuration, respectively.
14. The apparatus of claim 10, wherein the first and second sets of transistors each comprise a non-cascode topology, and wherein a first transistor of the first set of transistors comprises a common-channel terminal configuration.
15. The apparatus of claim 14, wherein a channel terminal of a first transistor of the second set of transistors is coupled to the dc power supply and an input of the amplifier.
16. The apparatus of claim 15, wherein the first transistor of the first set of transistors is a field effect transistor, FET, comprising a common source configuration.
17. The apparatus of claim 9, wherein the second set of transistors is coupled between the input and the output of the amplifier.
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| US16/273,261 | 2019-02-12 | ||
| US16/273,261 US11070176B2 (en) | 2018-02-13 | 2019-02-12 | Amplifier linearization and related apparatus thereof |
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| CN108768312A (en) * | 2018-07-23 | 2018-11-06 | 上海亮牛半导体科技有限公司 | Utilize the circuit structure and method of controllable impedance and improvement power amplifier linearity |
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| KR20050066955A (en) * | 2003-12-26 | 2005-06-30 | 한국전자통신연구원 | Predistortion linealizer for power amplifier |
| KR100930200B1 (en) * | 2007-03-29 | 2009-12-07 | 삼성전기주식회사 | Power Amplifier with Linearizer |
| US7656229B2 (en) * | 2008-01-28 | 2010-02-02 | Qualcomm, Incorporated | Method and apparatus for reducing intermodulation distortion in an electronic device having an amplifier circuit |
| US7936220B2 (en) * | 2008-12-12 | 2011-05-03 | Qualcomm, Incorporated | Techniques for improving amplifier linearity |
| US8564274B2 (en) * | 2009-01-24 | 2013-10-22 | Micron Technology, Inc. | Reference voltage generation for single-ended communication channels |
| US8102213B2 (en) * | 2009-07-23 | 2012-01-24 | Qualcomm, Incorporated | Multi-mode low noise amplifier with transformer source degeneration |
| US8237507B1 (en) * | 2011-03-14 | 2012-08-07 | Broadcom Corporation | Method and system for transmitter linearization |
| US8624568B2 (en) * | 2011-09-30 | 2014-01-07 | Texas Instruments Incorporated | Low noise voltage regulator and method with fast settling and low-power consumption |
| US9035697B2 (en) * | 2013-03-15 | 2015-05-19 | Qualcomm Incorporated | Split amplifiers with improved linearity |
| KR102131002B1 (en) * | 2013-10-01 | 2020-08-06 | 한국과학기술원 | Envelope tracking power transmitter using common-gate voltage modulation linearizer |
| KR101565663B1 (en) * | 2013-12-30 | 2015-11-03 | 삼성전기주식회사 | Power amplifier |
| US10187016B2 (en) * | 2016-09-19 | 2019-01-22 | Qorvo Us, Inc. | Amplifier with improved linearity |
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| US6262631B1 (en) * | 1998-04-30 | 2001-07-17 | The Whitaker Corporation | Silicon power bipolar junction transistor with an integrated linearizer |
| CN108768312A (en) * | 2018-07-23 | 2018-11-06 | 上海亮牛半导体科技有限公司 | Utilize the circuit structure and method of controllable impedance and improvement power amplifier linearity |
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| CN111555725A (en) | 2020-08-18 |
| TW202030973A (en) | 2020-08-16 |
| TWI745794B (en) | 2021-11-11 |
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